Loop vectorizer not working with LLVM 3.7?

[simonster]

This may be a known issue, but I can't get anything to vectorize with LLVM 3.7, e.g. there are no vector instructions in:

function f(x)
    @simd for i = 1:length(x)
        @inbounds x[i] *= 2
    end
end
code_llvm(f, (Vector{Float64},))

Version is:

julia> versioninfo()
Julia Version 0.5.0-dev+63
Commit 4a2298d* (2015-09-12 22:48 UTC)
Platform Info:
  System: Darwin (x86_64-apple-darwin14.4.0)
  CPU: Intel(R) Core(TM) i7-4850HQ CPU @ 2.30GHz
  WORD_SIZE: 64
  BLAS: libopenblas (USE64BITINT DYNAMIC_ARCH NO_AFFINITY Haswell)
  LAPACK: libopenblas
  LIBM: libopenlibm
  LLVM: libLLVM-3.7.0

Of course this works properly with LLVM 3.3.

[pao]

cc @ArchRobison for @simd expertise

[ArchRobison]

I can replicate the problem. I'll take a look.

[ArchRobison]

Something is very wrong with the target machine identification. With JULIA_LLVM_ARGS=-debug-only=loop-vectorize, usr/bin/julia-debug seems to be underrating my "Haswell" box:

LV: The Widest register is: 32 bits.
LV: The target has no vector registers.

Though when I compile other code, I see 64-bit instructions being used. I'll poke around some more.

[mdcfrancis]

Possibly related ?

#13121

[yuyichao]

@ArchRobison Any update? I've tried to set JULIA_LLVM_ARGS=-debug-only=loop-vectorize but got,

yuyichao% JULIA_LLVM_ARGS=-debug-only=loop-vectorize julia-debug 
Julia: Unknown command line argument '-debug-only=loop-vectorize'.  Try: 'Julia -help'
Julia: Did you mean '-debug-pass=loop-vectorize'?

Is there any other compile options I need to set for this?

[ArchRobison]

I'm likely not going to be able to look at it further until next week, owing to a C++ committee deadline on Friday for proposals. So I encourage you to look into it.

Counter-intuitively, to get the "-debug-only" functionality, LLVM has to be built with assertions enabled. Add LLVM_ASSERTIONS = 1 to your Make.user, rebuild, and then JULIA_LLVM_ARGS=-debug-only=loop-vectorize should get you the extra output from usr/bin/julia-debug.

[yuyichao]

Thanks.

The issue does seem to be the register width since UInt8 can be successfully vectorized (using avx2 instructions ..... = = .....).

However, it doesn't seems to be just this. With -debug-only=subtarget it clearly shows that this CPU has AVX2

Features:+64bit,+sse2
CPU:broadwell

Subtarget features: SSELevel 9, 3DNowLevel 0, 64bit 1

I'll try to poke around but I'm not sure if I can find the issue.

[ArchRobison]

I'm back on this. Here's what I suspect is the proximate cause in codegen.cpp

#ifndef LLVM37
    jl_TargetMachine->addAnalysisPasses(*FPM);
#endif

Evidently addAnalysisPasses disappeared to make way for the latest fashion. After studying julia/deps/srccache/llvm-3.7.0/lib/CodeGen/LLVMTargetMachine.cpp, it looks like we need to call createTargetTransformInfoWrapperPass and possibly more, though I'm not sure yet.