Dwarf: implement .eh_frame

Author: jacobly0

lib/std/leb128.zig

@@ -125,7 +125,7 @@ pub const readILEB128 = readIleb128;
 pub fn writeIleb128(writer: anytype, arg: anytype) !void {
     const Arg = @TypeOf(arg);
     const Int = switch (Arg) {
-        comptime_int => std.math.IntFittingRange(-arg - 1, arg),
+        comptime_int => std.math.IntFittingRange(-@abs(arg), @abs(arg)),
         else => Arg,
     };
     const Signed = if (@typeInfo(Int).Int.bits < 8) i8 else Int;

lib/std/os/linux/x86_64.zig

@@ -114,14 +114,15 @@ pub fn clone() callconv(.Naked) usize {
         \\      movq %%rcx,(%%rsi)
         \\      syscall
         \\      testq %%rax,%%rax
-        \\      jnz 1f
+        \\      jz 1f
+        \\      retq
+        \\1:    .cfi_undefined %%rip
         \\      xorl %%ebp,%%ebp
         \\      popq %%rdi
         \\      callq *%%r9
         \\      movl %%eax,%%edi
         \\      movl $60,%%eax // SYS_exit
         \\      syscall
-        \\1:    ret
         \\
     );
 }

lib/std/start.zig

@@ -249,6 +249,7 @@ fn _start() callconv(.Naked) noreturn {
     // linker explicitly.
     asm volatile (switch (native_arch) {
             .x86_64 =>
+            \\ .cfi_undefined %%rip
             \\ xorl %%ebp, %%ebp
             \\ movq %%rsp, %%rdi
             \\ andq $-16, %%rsp

src/arch/x86_64/CodeGen.zig

@@ -1491,6 +1491,46 @@ fn asmPseudo(self: *Self, ops: Mir.Inst.Ops) !void {
     });
 }
 
+fn asmPseudoRegister(self: *Self, ops: Mir.Inst.Ops, reg: Register) !void {
+    assert(std.mem.startsWith(u8, @tagName(ops), "pseudo_") and
+        std.mem.endsWith(u8, @tagName(ops), "_r"));
+    _ = try self.addInst(.{
+        .tag = .pseudo,
+        .ops = ops,
+        .data = .{ .r = .{ .r1 = reg } },
+    });
+}
+
+fn asmPseudoImmediate(self: *Self, ops: Mir.Inst.Ops, imm: Immediate) !void {
+    assert(std.mem.startsWith(u8, @tagName(ops), "pseudo_") and
+        std.mem.endsWith(u8, @tagName(ops), "_i_s"));
+    _ = try self.addInst(.{
+        .tag = .pseudo,
+        .ops = ops,
+        .data = .{ .i = .{ .i = @bitCast(imm.signed) } },
+    });
+}
+
+fn asmPseudoRegisterRegister(self: *Self, ops: Mir.Inst.Ops, reg1: Register, reg2: Register) !void {
+    assert(std.mem.startsWith(u8, @tagName(ops), "pseudo_") and
+        std.mem.endsWith(u8, @tagName(ops), "_rr"));
+    _ = try self.addInst(.{
+        .tag = .pseudo,
+        .ops = ops,
+        .data = .{ .rr = .{ .r1 = reg1, .r2 = reg2 } },
+    });
+}
+
+fn asmPseudoRegisterImmediate(self: *Self, ops: Mir.Inst.Ops, reg: Register, imm: Immediate) !void {
+    assert(std.mem.startsWith(u8, @tagName(ops), "pseudo_") and
+        std.mem.endsWith(u8, @tagName(ops), "_ri_s"));
+    _ = try self.addInst(.{
+        .tag = .pseudo,
+        .ops = ops,
+        .data = .{ .ri = .{ .r1 = reg, .i = @bitCast(imm.signed) } },
+    });
+}
+
 fn asmRegister(self: *Self, tag: Mir.Inst.FixedTag, reg: Register) !void {
     _ = try self.addInst(.{
         .tag = tag[1],
@@ -1877,7 +1917,10 @@ fn gen(self: *Self) InnerError!void {
     const cc = abi.resolveCallingConvention(fn_info.cc, self.target.*);
     if (cc != .Naked) {
         try self.asmRegister(.{ ._, .push }, .rbp);
+        try self.asmPseudoImmediate(.pseudo_cfi_adjust_cfa_offset_i_s, Immediate.s(8));
+        try self.asmPseudoRegisterImmediate(.pseudo_cfi_rel_offset_ri_s, .rbp, Immediate.s(0));
         try self.asmRegisterRegister(.{ ._, .mov }, .rbp, .rsp);
+        try self.asmPseudoRegister(.pseudo_cfi_def_cfa_register_r, .rbp);
         const backpatch_push_callee_preserved_regs = try self.asmPlaceholder();
         const backpatch_frame_align = try self.asmPlaceholder();
         const backpatch_frame_align_extra = try self.asmPlaceholder();
@@ -1962,6 +2005,7 @@ fn gen(self: *Self) InnerError!void {
         const backpatch_stack_dealloc = try self.asmPlaceholder();
         const backpatch_pop_callee_preserved_regs = try self.asmPlaceholder();
         try self.asmRegister(.{ ._, .pop }, .rbp);
+        try self.asmPseudoRegisterImmediate(.pseudo_cfi_def_cfa_ri_s, .rsp, Immediate.s(8));
         try self.asmOpOnly(.{ ._, .ret });
 
         const frame_layout = try self.computeFrameLayout(cc);
@@ -14038,7 +14082,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
         var mnem_it = mem.tokenizeAny(u8, line, " \t");
         var prefix: Instruction.Prefix = .none;
         const mnem_str = while (mnem_it.next()) |mnem_str| {
-            if (mem.startsWith(u8, mnem_str, "#")) continue :next_line;
+            if (mnem_str[0] == '#') continue :next_line;
             if (mem.startsWith(u8, mnem_str, "//")) continue :next_line;
             if (std.meta.stringToEnum(Instruction.Prefix, mnem_str)) |pre| {
                 if (prefix != .none) return self.fail("extra prefix: '{s}'", .{mnem_str});
@@ -14063,8 +14107,14 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
             }
             label_gop.value_ptr.target = @intCast(self.mir_instructions.len);
         } else continue;
+        if (mnem_str[0] == '.') {
+            if (prefix != .none) return self.fail("prefixed directive: '{s} {s}'", .{ @tagName(prefix), mnem_str });
+            prefix = .directive;
+        }
 
-        var mnem_size: ?Memory.Size = if (mem.endsWith(u8, mnem_str, "b"))
+        var mnem_size: ?Memory.Size = if (prefix == .directive)
+            null
+        else if (mem.endsWith(u8, mnem_str, "b"))
             .byte
         else if (mem.endsWith(u8, mnem_str, "w"))
             .word
@@ -14095,7 +14145,9 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
             mnem_size = fixed_mnem_size;
         }
         const mnem_name = @tagName(mnem_tag);
-        const mnem_fixed_tag: Mir.Inst.FixedTag = for (std.enums.values(Mir.Inst.Fixes)) |fixes| {
+        const mnem_fixed_tag: Mir.Inst.FixedTag = if (prefix == .directive)
+            .{ ._, .pseudo }
+        else for (std.enums.values(Mir.Inst.Fixes)) |fixes| {
             const fixes_name = @tagName(fixes);
             const space_i = mem.indexOfScalar(u8, fixes_name, ' ');
             const fixes_prefix = if (space_i) |i|
@@ -14116,7 +14168,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
         } else {
             assert(prefix != .none); // no combination of fixes produced a known mnemonic
             return self.fail("invalid prefix for mnemonic: '{s} {s}'", .{
-                @tagName(prefix), mnem_str,
+                @tagName(prefix), mnem_name,
             });
         };
 
@@ -14324,7 +14376,62 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
             } else return self.fail("invalid operand: '{s}'", .{op_str});
         } else if (op_it.next()) |op_str| return self.fail("extra operand: '{s}'", .{op_str});
 
-        (switch (ops[0]) {
+        (if (prefix == .directive) switch (mnem_tag) {
+            .@".cfi_def_cfa" => if (ops[0] == .reg and ops[1] == .imm and ops[2] == .none)
+                self.asmPseudoRegisterImmediate(.pseudo_cfi_def_cfa_ri_s, ops[0].reg, ops[1].imm)
+            else
+                error.InvalidInstruction,
+            .@".cfi_def_cfa_register" => if (ops[0] == .reg and ops[1] == .none)
+                self.asmPseudoRegister(.pseudo_cfi_def_cfa_register_r, ops[0].reg)
+            else
+                error.InvalidInstruction,
+            .@".cfi_def_cfa_offset" => if (ops[0] == .imm and ops[1] == .none)
+                self.asmPseudoImmediate(.pseudo_cfi_def_cfa_offset_i_s, ops[0].imm)
+            else
+                error.InvalidInstruction,
+            .@".cfi_adjust_cfa_offset" => if (ops[0] == .imm and ops[1] == .none)
+                self.asmPseudoImmediate(.pseudo_cfi_adjust_cfa_offset_i_s, ops[0].imm)
+            else
+                error.InvalidInstruction,
+            .@".cfi_offset" => if (ops[0] == .reg and ops[1] == .imm and ops[2] == .none)
+                self.asmPseudoRegisterImmediate(.pseudo_cfi_offset_ri_s, ops[0].reg, ops[1].imm)
+            else
+                error.InvalidInstruction,
+            .@".cfi_val_offset" => if (ops[0] == .reg and ops[1] == .imm and ops[2] == .none)
+                self.asmPseudoRegisterImmediate(.pseudo_cfi_val_offset_ri_s, ops[0].reg, ops[1].imm)
+            else
+                error.InvalidInstruction,
+            .@".cfi_rel_offset" => if (ops[0] == .reg and ops[1] == .imm and ops[2] == .none)
+                self.asmPseudoRegisterImmediate(.pseudo_cfi_rel_offset_ri_s, ops[0].reg, ops[1].imm)
+            else
+                error.InvalidInstruction,
+            .@".cfi_register" => if (ops[0] == .reg and ops[1] == .reg and ops[2] == .none)
+                self.asmPseudoRegisterRegister(.pseudo_cfi_register_rr, ops[0].reg, ops[1].reg)
+            else
+                error.InvalidInstruction,
+            .@".cfi_restore" => if (ops[0] == .reg and ops[1] == .none)
+                self.asmPseudoRegister(.pseudo_cfi_restore_r, ops[0].reg)
+            else
+                error.InvalidInstruction,
+            .@".cfi_undefined" => if (ops[0] == .reg and ops[1] == .none)
+                self.asmPseudoRegister(.pseudo_cfi_undefined_r, ops[0].reg)
+            else
+                error.InvalidInstruction,
+            .@".cfi_same_value" => if (ops[0] == .reg and ops[1] == .none)
+                self.asmPseudoRegister(.pseudo_cfi_same_value_r, ops[0].reg)
+            else
+                error.InvalidInstruction,
+            .@".cfi_remember_state" => if (ops[0] == .none)
+                self.asmPseudo(.pseudo_cfi_remember_state_none)
+            else
+                error.InvalidInstruction,
+            .@".cfi_restore_state" => if (ops[0] == .none)
+                self.asmPseudo(.pseudo_cfi_restore_state_none)
+            else
+                error.InvalidInstruction,
+            .@".cfi_escape" => error.InvalidInstruction,
+            else => unreachable,
+        } else switch (ops[0]) {
             .none => self.asmOpOnly(mnem_fixed_tag),
             .reg => |reg0| switch (ops[1]) {
                 .none => self.asmRegister(mnem_fixed_tag, reg0),
@@ -19210,14 +19317,6 @@ fn fail(self: *Self, comptime format: []const u8, args: anytype) InnerError {
     return error.CodegenFail;
 }
 
-fn failSymbol(self: *Self, comptime format: []const u8, args: anytype) InnerError {
-    @branchHint(.cold);
-    assert(self.err_msg == null);
-    const gpa = self.gpa;
-    self.err_msg = try ErrorMsg.create(gpa, self.src_loc, format, args);
-    return error.CodegenFail;
-}
-
 fn parseRegName(name: []const u8) ?Register {
     if (@hasDecl(Register, "parseRegName")) {
         return Register.parseRegName(name);

src/arch/x86_64/Emit.zig

@@ -30,6 +30,59 @@ pub fn emitMir(emit: *Emit) Error!void {
         var lowered_relocs = lowered.relocs;
         for (lowered.insts, 0..) |lowered_inst, lowered_index| {
             const start_offset: u32 = @intCast(emit.code.items.len);
+            if (lowered_inst.prefix == .directive) {
+                switch (emit.debug_output) {
+                    .dwarf => |dwarf| switch (lowered_inst.encoding.mnemonic) {
+                        .@".cfi_def_cfa" => try dwarf.genDebugFrame(start_offset, .{ .def_cfa = .{
+                            .reg = lowered_inst.ops[0].reg.dwarfNum(),
+                            .off = lowered_inst.ops[1].imm.signed,
+                        } }),
+                        .@".cfi_def_cfa_register" => try dwarf.genDebugFrame(start_offset, .{
+                            .def_cfa_register = lowered_inst.ops[0].reg.dwarfNum(),
+                        }),
+                        .@".cfi_def_cfa_offset" => try dwarf.genDebugFrame(start_offset, .{
+                            .def_cfa_offset = lowered_inst.ops[0].imm.signed,
+                        }),
+                        .@".cfi_adjust_cfa_offset" => try dwarf.genDebugFrame(start_offset, .{
+                            .adjust_cfa_offset = lowered_inst.ops[0].imm.signed,
+                        }),
+                        .@".cfi_offset" => try dwarf.genDebugFrame(start_offset, .{ .offset = .{
+                            .reg = lowered_inst.ops[0].reg.dwarfNum(),
+                            .off = lowered_inst.ops[1].imm.signed,
+                        } }),
+                        .@".cfi_val_offset" => try dwarf.genDebugFrame(start_offset, .{ .val_offset = .{
+                            .reg = lowered_inst.ops[0].reg.dwarfNum(),
+                            .off = lowered_inst.ops[1].imm.signed,
+                        } }),
+                        .@".cfi_rel_offset" => try dwarf.genDebugFrame(start_offset, .{ .rel_offset = .{
+                            .reg = lowered_inst.ops[0].reg.dwarfNum(),
+                            .off = lowered_inst.ops[1].imm.signed,
+                        } }),
+                        .@".cfi_register" => try dwarf.genDebugFrame(start_offset, .{ .register = .{
+                            lowered_inst.ops[0].reg.dwarfNum(),
+                            lowered_inst.ops[1].reg.dwarfNum(),
+                        } }),
+                        .@".cfi_restore" => try dwarf.genDebugFrame(start_offset, .{
+                            .restore = lowered_inst.ops[0].reg.dwarfNum(),
+                        }),
+                        .@".cfi_undefined" => try dwarf.genDebugFrame(start_offset, .{
+                            .undefined = lowered_inst.ops[0].reg.dwarfNum(),
+                        }),
+                        .@".cfi_same_value" => try dwarf.genDebugFrame(start_offset, .{
+                            .same_value = lowered_inst.ops[0].reg.dwarfNum(),
+                        }),
+                        .@".cfi_remember_state" => try dwarf.genDebugFrame(start_offset, .remember_state),
+                        .@".cfi_restore_state" => try dwarf.genDebugFrame(start_offset, .restore_state),
+                        .@".cfi_escape" => try dwarf.genDebugFrame(start_offset, .{
+                            .escape = lowered_inst.ops[0].bytes,
+                        }),
+                        else => unreachable,
+                    },
+                    .plan9 => {},
+                    .none => {},
+                }
+                continue;
+            }
             try lowered_inst.encode(emit.code.writer(), .{});
             const end_offset: u32 = @intCast(emit.code.items.len);
             while (lowered_relocs.len > 0 and

src/arch/x86_64/Encoding.zig

@@ -220,6 +220,21 @@ pub fn format(
 }
 
 pub const Mnemonic = enum {
+    // Directives
+    @".cfi_def_cfa",
+    @".cfi_def_cfa_register",
+    @".cfi_def_cfa_offset",
+    @".cfi_adjust_cfa_offset",
+    @".cfi_offset",
+    @".cfi_val_offset",
+    @".cfi_rel_offset",
+    @".cfi_register",
+    @".cfi_restore",
+    @".cfi_undefined",
+    @".cfi_same_value",
+    @".cfi_remember_state",
+    @".cfi_restore_state",
+    @".cfi_escape",
     // zig fmt: off
     // General-purpose
     adc, add, @"and",
@@ -442,6 +457,7 @@ pub const Op = enum {
     imm8s, imm16s, imm32s,
     al, ax, eax, rax,
     cl,
+    rip, eip, ip,
     r8, r16, r32, r64,
     rm8, rm16, rm32, rm64,
     r32_m8, r32_m16, r64_m16,
@@ -487,7 +503,12 @@ pub const Op = enum {
                     256 => .ymm,
                     else => unreachable,
                 },
-                .ip => unreachable,
+                .ip => switch (reg) {
+                    .rip => .rip,
+                    .eip => .eip,
+                    .ip => .ip,
+                    else => unreachable,
+                },
             },
 
             .mem => |mem| switch (mem) {
@@ -531,13 +552,15 @@ pub const Op = enum {
                 else
                     .imm64,
             },
+
+            .bytes => unreachable,
         };
     }
 
     pub fn immBitSize(op: Op) u64 {
         return switch (op) {
             .none, .o16, .o32, .o64, .moffs, .m, .sreg => unreachable,
-            .al, .cl, .r8, .rm8, .r32_m8 => unreachable,
+            .al, .cl, .rip, .eip, .ip, .r8, .rm8, .r32_m8 => unreachable,
             .ax, .r16, .rm16 => unreachable,
             .eax, .r32, .rm32, .r32_m16 => unreachable,
             .rax, .r64, .rm64, .r64_m16 => unreachable,
@@ -560,9 +583,9 @@ pub const Op = enum {
             .rel8, .rel16, .rel32 => unreachable,
             .m8, .m16, .m32, .m64, .m80, .m128, .m256 => unreachable,
             .al, .cl, .r8, .rm8 => 8,
-            .ax, .r16, .rm16 => 16,
-            .eax, .r32, .rm32, .r32_m8, .r32_m16 => 32,
-            .rax, .r64, .rm64, .r64_m16, .mm, .mm_m64 => 64,
+            .ax, .ip, .r16, .rm16 => 16,
+            .eax, .eip, .r32, .rm32, .r32_m8, .r32_m16 => 32,
+            .rax, .rip, .r64, .rm64, .r64_m16, .mm, .mm_m64 => 64,
             .st => 80,
             .xmm0, .xmm, .xmm_m8, .xmm_m16, .xmm_m32, .xmm_m64, .xmm_m128 => 128,
             .ymm, .ymm_m256 => 256,
@@ -574,7 +597,7 @@ pub const Op = enum {
             .none, .o16, .o32, .o64, .moffs, .m, .sreg => unreachable,
             .unity, .imm8, .imm8s, .imm16, .imm16s, .imm32, .imm32s, .imm64 => unreachable,
             .rel8, .rel16, .rel32 => unreachable,
-            .al, .cl, .r8, .ax, .r16, .eax, .r32, .rax, .r64 => unreachable,
+            .al, .cl, .r8, .ax, .ip, .r16, .eax, .eip, .r32, .rax, .rip, .r64 => unreachable,
             .st, .mm, .xmm0, .xmm, .ymm => unreachable,
             .m8, .rm8, .r32_m8, .xmm_m8 => 8,
             .m16, .rm16, .r32_m16, .r64_m16, .xmm_m16 => 16,
@@ -602,8 +625,9 @@ pub const Op = enum {
     pub fn isRegister(op: Op) bool {
         // zig fmt: off
         return switch (op) {
-            .cl,
             .al, .ax, .eax, .rax,
+            .cl,
+            .ip, .eip, .rip,
             .r8, .r16, .r32, .r64,
             .rm8, .rm16, .rm32, .rm64,
             .r32_m8, .r32_m16, .r64_m16,
@@ -664,6 +688,7 @@ pub const Op = enum {
             .mm, .mm_m64 => .mmx,
             .xmm0, .xmm, .xmm_m8, .xmm_m16, .xmm_m32, .xmm_m64, .xmm_m128 => .sse,
             .ymm, .ymm_m256 => .sse,
+            .rip, .eip, .ip => .ip,
         };
     }