x86_64: fix packedStore miscomp by spilling EFLAGS

Fixes #20113.

First, postpone operand resolve from airStore into packedStore/store.
Then, spill EFLAGS before AND in packedStore as AND instructions
clobber EFLAGS, which may break EFLAGS operands.

Bug: #20113
Signed-off-by: Bingwu Zhang <[email protected]>

Author: xtexx

src/arch/x86_64/CodeGen.zig

@@ -88054,6 +88054,8 @@ fn packedStore(self: *CodeGen, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue)
         const part_mask = (@as(u64, std.math.maxInt(u64)) >> @intCast(64 - part_bit_size)) <<
             @intCast(part_bit_off);
         const part_mask_not = part_mask ^ (@as(u64, std.math.maxInt(u64)) >> @intCast(64 - limb_abi_bits));
+        // AND clobbers EFLAGS
+        try self.spillEflagsIfOccupied();
         if (limb_abi_size <= 4) {
             try self.asmMemoryImmediate(.{ ._, .@"and" }, limb_mem, .u(part_mask_not));
         } else if (std.math.cast(i32, @as(i64, @bitCast(part_mask_not)))) |small| {
@@ -88178,8 +88180,8 @@ fn airStore(self: *CodeGen, inst: Air.Inst.Index, safety: bool) !void {
         const reg_locks = self.register_manager.lockRegsAssumeUnused(3, .{ .rdi, .rsi, .rcx });
         defer for (reg_locks) |lock| self.register_manager.unlockReg(lock);
 
-        const src_mcv = try self.resolveInst(bin_op.rhs);
-        const ptr_mcv = try self.resolveInst(bin_op.lhs);
+        const src_mcv = MCValue{ .air_ref = bin_op.rhs };
+        const ptr_mcv = MCValue{ .air_ref = bin_op.lhs };
         const ptr_ty = self.typeOf(bin_op.lhs);
 
         const ptr_info = ptr_ty.ptrInfo(zcu);