aarch64: more progress

 - factor out `loadReg`
 - support all general system control registers in inline asm
 - fix asserts after iterating field offsets
 - fix typo in `slice_elem_val`
 - fix translation of argument locations

Author: jacobly0

src/codegen/aarch64.zig

@@ -113,9 +113,7 @@ pub fn generate(
             },
             .stack_slot => |stack_slot| {
                 assert(stack_slot.base == .sp);
-                passed_vi.setParent(&isel, .{
-                    .stack_slot = named_stack_args.withOffset(stack_slot.offset),
-                });
+                passed_vi.changeStackSlot(&isel, named_stack_args.withOffset(stack_slot.offset));
             },
             .address, .value, .constant => unreachable,
         }

src/codegen/aarch64/Assemble.zig

@@ -215,6 +215,7 @@ fn nextToken(as: *Assemble, buf: *[token_buf_len]u8, comptime opts: struct {
 
 const SymbolSpec = union(enum) {
     reg: struct { format: aarch64.encoding.Register.Format, allow_sp: bool = false },
+    systemreg,
     imm: struct {
         type: std.builtin.Type.Int,
         multiple_of: comptime_int = 1,
@@ -227,6 +228,7 @@ const SymbolSpec = union(enum) {
     fn Storage(comptime spec: SymbolSpec) type {
         return switch (spec) {
             .reg => aarch64.encoding.Register,
+            .systemreg => aarch64.encoding.Register.System,
             .imm => |imm| @Type(.{ .int = imm.type }),
             .extend => Instruction.DataProcessingRegister.AddSubtractExtendedRegister.Option,
             .shift => Instruction.DataProcessingRegister.Shift.Op,
@@ -238,8 +240,7 @@ const SymbolSpec = union(enum) {
         const Result = Storage(spec);
         switch (spec) {
             .reg => |reg_spec| {
-                var buf: [token_buf_len]u8 = undefined;
-                const reg = Result.parse(std.ascii.lowerString(&buf, token[0..@min(token.len, buf.len)])) orelse {
+                const reg = Result.parse(token) orelse {
                     log.debug("invalid register: \"{f}\"", .{std.zig.fmtString(token)});
                     return null;
                 };
@@ -253,6 +254,14 @@ const SymbolSpec = union(enum) {
                 }
                 return reg;
             },
+            .systemreg => {
+                const systemreg = Result.parse(token) orelse {
+                    log.debug("invalid system register: \"{f}\"", .{std.zig.fmtString(token)});
+                    return null;
+                };
+                assert(systemreg.op0 >= 2);
+                return systemreg;
+            },
             .imm => |imm_spec| {
                 const imm = std.fmt.parseInt(Result, token, 0) catch {
                     log.debug("invalid immediate: \"{f}\"", .{std.zig.fmtString(token)});

src/codegen/aarch64/Select.zig

@@ -851,11 +851,21 @@
     },
     // C6.2.228 MRS
     .{
-        .pattern = "MRS <Xt>, CTR_EL0",
+        .pattern = "MRS <Xt>, <systemreg>",
         .symbols = .{
             .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
+            .systemreg = .systemreg,
         },
-        .encode = .{ .mrs, .Xt, 0b11, 0b011, 0b0000, 0b0000, 0b001 },
+        .encode = .{ .mrs, .Xt, .systemreg },
+    },
+    // C6.2.230 MSR (register)
+    .{
+        .pattern = "MSR <systemreg>, <Xt>",
+        .symbols = .{
+            .systemreg = .systemreg,
+            .Xt = .{ .reg = .{ .format = .{ .integer = .doubleword } } },
+        },
+        .encode = .{ .msr, .systemreg, .Xt },
     },
     // C6.2.234 NEG
     .{

src/codegen/aarch64/encoding.zig

@@ -471,7 +471,6 @@ fn testPointerToVoidReturnType2() *const void {
 }
 
 test "array 2D const double ptr" {
-    if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
     if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
     if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;
@@ -484,7 +483,6 @@ test "array 2D const double ptr" {
 }
 
 test "array 2D const double ptr with offset" {
-    if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
     if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
     if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;
@@ -497,7 +495,6 @@ test "array 2D const double ptr with offset" {
 }
 
 test "array 3D const double ptr with offset" {
-    if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
     if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
     if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;

src/codegen/aarch64/instructions.zon

@@ -1816,7 +1816,6 @@ test "peer type resolution: C pointer and @TypeOf(null)" {
 }
 
 test "peer type resolution: three-way resolution combines error set and optional" {
-    if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
     if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_spirv) return error.SkipZigTest;

test/behavior/basic.zig

@@ -436,7 +436,6 @@ test "pointer sentinel with optional element" {
 }
 
 test "pointer sentinel with +inf" {
-    if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
     if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;