From cd12454fed9c4e9b23434ffcdb9cea1a10319bfe Mon Sep 17 00:00:00 2001 From: Luis Ubieda Date: Wed, 9 Apr 2025 18:00:26 -0400 Subject: [PATCH 1/8] sensor: adxl345: Fix conditional instantiation of RTIO ctx and IODEV With actual parameter to determine whether the driver requires it: Streaming mode enabled. Signed-off-by: Luis Ubieda --- drivers/sensor/adi/adxl345/adxl345.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/sensor/adi/adxl345/adxl345.c b/drivers/sensor/adi/adxl345/adxl345.c index 14463392bb7e2..80b7211baec39 100644 --- a/drivers/sensor/adi/adxl345/adxl345.c +++ b/drivers/sensor/adi/adxl345/adxl345.c @@ -594,8 +594,8 @@ static int adxl345_init(const struct device *dev) #define ADXL345_DEFINE(inst) \ IF_ENABLED(CONFIG_ADXL345_STREAM, (ADXL345_RTIO_DEFINE(inst))); \ static struct adxl345_dev_data adxl345_data_##inst = { \ - COND_CODE_1(adxl345_iodev_##inst, (.rtio_ctx = &adxl345_rtio_ctx_##inst, \ - .iodev = &adxl345_iodev_##inst,), ()) \ + IF_ENABLED(CONFIG_ADXL345_STREAM, (.rtio_ctx = &adxl345_rtio_ctx_##inst, \ + .iodev = &adxl345_iodev_##inst,)) \ }; \ static const struct adxl345_dev_config adxl345_config_##inst = \ COND_CODE_1(DT_INST_ON_BUS(inst, spi), (ADXL345_CONFIG_SPI(inst)), \ From 9ecaca7a8797b35d564f650a0c1e8c8f294e45c2 Mon Sep 17 00:00:00 2001 From: Luis Ubieda Date: Wed, 9 Apr 2025 18:02:11 -0400 Subject: [PATCH 2/8] sensor: adxl345: Prevent clearing SQE flags set while prepping SQEs SQE flags are adjusted when preparing write/read ops, therefore an OR operation is required. Signed-off-by: Luis Ubieda --- drivers/sensor/adi/adxl345/adxl345_stream.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/sensor/adi/adxl345/adxl345_stream.c b/drivers/sensor/adi/adxl345/adxl345_stream.c index ac62f3fbf6a2a..2ad28a4f2c12b 100644 --- a/drivers/sensor/adi/adxl345/adxl345_stream.c +++ b/drivers/sensor/adi/adxl345/adxl345_stream.c @@ -211,7 +211,7 @@ static void adxl345_process_fifo_samples_cb(struct rtio *r, const struct rtio_sq rtio_sqe_prep_tiny_write(write_fifo_addr, data->iodev, RTIO_PRIO_NORM, ®_addr, 1, NULL); - write_fifo_addr->flags = RTIO_SQE_TRANSACTION; + write_fifo_addr->flags |= RTIO_SQE_TRANSACTION; rtio_sqe_prep_read(read_fifo_data, data->iodev, RTIO_PRIO_NORM, read_buf + data->fifo_total_bytes, SAMPLE_SIZE, current_sqe); @@ -222,7 +222,7 @@ static void adxl345_process_fifo_samples_cb(struct rtio *r, const struct rtio_sq if (i == fifo_samples-1) { struct rtio_sqe *complete_op = rtio_sqe_acquire(data->rtio_ctx); - read_fifo_data->flags = RTIO_SQE_CHAINED; + read_fifo_data->flags |= RTIO_SQE_CHAINED; rtio_sqe_prep_callback(complete_op, adxl345_fifo_read_cb, (void *)dev, current_sqe); } @@ -341,10 +341,10 @@ static void adxl345_process_status1_cb(struct rtio *r, const struct rtio_sqe *sq const uint8_t reg_addr = ADXL345_REG_READ(ADXL345_FIFO_STATUS_REG); rtio_sqe_prep_tiny_write(write_fifo_addr, data->iodev, RTIO_PRIO_NORM, ®_addr, 1, NULL); - write_fifo_addr->flags = RTIO_SQE_TRANSACTION; + write_fifo_addr->flags |= RTIO_SQE_TRANSACTION; rtio_sqe_prep_read(read_fifo_data, data->iodev, RTIO_PRIO_NORM, data->fifo_ent, 1, current_sqe); - read_fifo_data->flags = RTIO_SQE_CHAINED; + read_fifo_data->flags |= RTIO_SQE_CHAINED; if (cfg->bus_type == ADXL345_BUS_I2C) { read_fifo_data->iodev_flags |= RTIO_IODEV_I2C_STOP | RTIO_IODEV_I2C_RESTART; } @@ -379,9 +379,9 @@ void adxl345_stream_irq_handler(const struct device *dev) uint8_t reg = ADXL345_REG_READ(ADXL345_INT_SOURCE); rtio_sqe_prep_tiny_write(write_status_addr, data->iodev, RTIO_PRIO_NORM, ®, 1, NULL); - write_status_addr->flags = RTIO_SQE_TRANSACTION; + write_status_addr->flags |= RTIO_SQE_TRANSACTION; rtio_sqe_prep_read(read_status_reg, data->iodev, RTIO_PRIO_NORM, &data->status1, 1, NULL); - read_status_reg->flags = RTIO_SQE_CHAINED; + read_status_reg->flags |= RTIO_SQE_CHAINED; if (cfg->bus_type == ADXL345_BUS_I2C) { read_status_reg->iodev_flags |= RTIO_IODEV_I2C_STOP | RTIO_IODEV_I2C_RESTART; From 51e60ce397fbf7fad1029eb968f2b8d9cd8b716d Mon Sep 17 00:00:00 2001 From: Luis Ubieda Date: Thu, 10 Apr 2025 13:07:22 -0400 Subject: [PATCH 3/8] sensor: adxl345: fix: Overriding of ODR setting in DTS property This patch fixes previous overriding of ODR setting through DTS (it would always be 25-Hz, irrespective of what the DTS property said). While doing so, create dt-binding enum to improve settings clarity. Signed-off-by: Luis Ubieda --- drivers/sensor/adi/adxl345/adxl345.c | 1 - drivers/sensor/adi/adxl345/adxl345.h | 14 +++++---- dts/bindings/sensor/adi,adxl345-common.yaml | 34 +++++++++++++-------- include/zephyr/dt-bindings/sensor/adxl345.h | 29 ++++++++++++++++++ 4 files changed, 58 insertions(+), 20 deletions(-) create mode 100644 include/zephyr/dt-bindings/sensor/adxl345.h diff --git a/drivers/sensor/adi/adxl345/adxl345.c b/drivers/sensor/adi/adxl345/adxl345.c index 80b7211baec39..0bf2f9e50ad99 100644 --- a/drivers/sensor/adi/adxl345/adxl345.c +++ b/drivers/sensor/adi/adxl345/adxl345.c @@ -562,7 +562,6 @@ static int adxl345_init(const struct device *dev) .fifo_config.fifo_mode = ADXL345_FIFO_STREAMED, \ .fifo_config.fifo_trigger = ADXL345_INT2, \ .fifo_config.fifo_samples = SAMPLE_NUM, \ - .odr = ADXL345_RATE_25HZ, \ #define ADXL345_CONFIG_SPI(inst) \ { \ diff --git a/drivers/sensor/adi/adxl345/adxl345.h b/drivers/sensor/adi/adxl345/adxl345.h index 8bc25f5034028..e3f26734abf7b 100644 --- a/drivers/sensor/adi/adxl345/adxl345.h +++ b/drivers/sensor/adi/adxl345/adxl345.h @@ -14,6 +14,8 @@ #include #include +#include + #ifdef CONFIG_ADXL345_STREAM #include #endif /* CONFIG_ADXL345_STREAM */ @@ -117,12 +119,12 @@ #define ADXL345_BUS_SPI 1 enum adxl345_odr { - ADXL345_ODR_12HZ = 0x7, - ADXL345_ODR_25HZ, - ADXL345_ODR_50HZ, - ADXL345_ODR_100HZ, - ADXL345_ODR_200HZ, - ADXL345_ODR_400HZ + ADXL345_ODR_12HZ = ADXL345_DT_ODR_12_5, + ADXL345_ODR_25HZ = ADXL345_DT_ODR_25, + ADXL345_ODR_50HZ = ADXL345_DT_ODR_50, + ADXL345_ODR_100HZ = ADXL345_DT_ODR_100, + ADXL345_ODR_200HZ = ADXL345_DT_ODR_200, + ADXL345_ODR_400HZ = ADXL345_DT_ODR_400, }; enum adxl345_fifo_trigger { diff --git a/dts/bindings/sensor/adi,adxl345-common.yaml b/dts/bindings/sensor/adi,adxl345-common.yaml index 6a3f301e2a778..5ffa5fabce07f 100644 --- a/dts/bindings/sensor/adi,adxl345-common.yaml +++ b/dts/bindings/sensor/adi,adxl345-common.yaml @@ -1,27 +1,35 @@ # Copyright (c) 2022 Analog Devices Inc. # SPDX-License-Identifier: Apache-2.0 +description: | + ADXL345 3-axis accelerometer + When setting the accelerometer DTS properties, make sure to include + adxl345.h and use the macros defined there. + + Example: + #include + + adxl345: adxl345@1d { + ... + + odr = ; + }; + include: sensor-device.yaml properties: odr: type: int - default: 0 + default: 10 description: | Accelerometer sampling frequency (ODR). Default is power on reset value. - 0 # 12.5Hz - 1 # 25Hz - 2 # 50Hz - 3 # 100Hz - 4 # 200Hz - 5 # 400Hz enum: - - 0 - - 1 - - 2 - - 3 - - 4 - - 5 + - 7 # ADXL345_DT_ODR_12_5 + - 8 # ADXL345_DT_ODR_25 + - 9 # ADXL345_DT_ODR_50 + - 10 # ADXL345_DT_ODR_100 + - 11 # ADXL345_DT_ODR_200 + - 12 # ADXL345_DT_ODR_400 int2-gpios: type: phandle-array diff --git a/include/zephyr/dt-bindings/sensor/adxl345.h b/include/zephyr/dt-bindings/sensor/adxl345.h new file mode 100644 index 0000000000000..67f52992580a3 --- /dev/null +++ b/include/zephyr/dt-bindings/sensor/adxl345.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2025 Croxel Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADI_ADX345_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_ADI_ADX345_H_ + +/** + * @defgroup ADXL345 ADI DT Options + * @ingroup sensor_interface + * @{ + */ + +/** + * @defgroup ADXL345_ODR Output Rate options + * @{ + */ +#define ADXL345_DT_ODR_12_5 7 +#define ADXL345_DT_ODR_25 8 +#define ADXL345_DT_ODR_50 9 +#define ADXL345_DT_ODR_100 10 +#define ADXL345_DT_ODR_200 11 +#define ADXL345_DT_ODR_400 12 +/** @} */ + +/** @} */ + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADI_ADX345_H_ */ From bce2d1522cc581ac85f34e10df196d9d769f3a8a Mon Sep 17 00:00:00 2001 From: Luis Ubieda Date: Thu, 10 Apr 2025 13:11:20 -0400 Subject: [PATCH 4/8] sensor: adxl345: rename ADXL345_ODR_12HZ to ADXL345_ODR_12_5HZ To better reflect the actual ODR setting. Signed-off-by: Luis Ubieda --- drivers/sensor/adi/adxl345/adxl345.c | 4 ++-- drivers/sensor/adi/adxl345/adxl345.h | 2 +- drivers/sensor/adi/adxl345/adxl345_decoder.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/sensor/adi/adxl345/adxl345.c b/drivers/sensor/adi/adxl345/adxl345.c index 0bf2f9e50ad99..f517e92e489ee 100644 --- a/drivers/sensor/adi/adxl345/adxl345.c +++ b/drivers/sensor/adi/adxl345/adxl345.c @@ -208,7 +208,7 @@ int adxl345_set_op_mode(const struct device *dev, enum adxl345_op_mode op_mode) * Set Output data rate. * @param dev - The device structure. * @param odr - Output data rate. - * Accepted values: ADXL345_ODR_12HZ + * Accepted values: ADXL345_ODR_12_5HZ * ADXL345_ODR_25HZ * ADXL345_ODR_50HZ * ADXL345_ODR_100HZ @@ -233,7 +233,7 @@ static int adxl345_attr_set_odr(const struct device *dev, switch (val->val1) { case 12: - odr = ADXL345_ODR_12HZ; + odr = ADXL345_ODR_12_5HZ; break; case 25: odr = ADXL345_ODR_25HZ; diff --git a/drivers/sensor/adi/adxl345/adxl345.h b/drivers/sensor/adi/adxl345/adxl345.h index e3f26734abf7b..d6935645c8ef6 100644 --- a/drivers/sensor/adi/adxl345/adxl345.h +++ b/drivers/sensor/adi/adxl345/adxl345.h @@ -119,7 +119,7 @@ #define ADXL345_BUS_SPI 1 enum adxl345_odr { - ADXL345_ODR_12HZ = ADXL345_DT_ODR_12_5, + ADXL345_ODR_12_5HZ = ADXL345_DT_ODR_12_5, ADXL345_ODR_25HZ = ADXL345_DT_ODR_25, ADXL345_ODR_50HZ = ADXL345_DT_ODR_50, ADXL345_ODR_100HZ = ADXL345_DT_ODR_100, diff --git a/drivers/sensor/adi/adxl345/adxl345_decoder.c b/drivers/sensor/adi/adxl345/adxl345_decoder.c index 1f39fb9d1d141..aee7af41a325b 100644 --- a/drivers/sensor/adi/adxl345/adxl345_decoder.c +++ b/drivers/sensor/adi/adxl345/adxl345_decoder.c @@ -91,7 +91,7 @@ static inline void adxl345_accel_convert_q31(q31_t *out, int16_t sample, int32_t #define SENSOR_SCALING_FACTOR (SENSOR_G / (16 * 1000 / 100)) static const uint32_t accel_period_ns[] = { - [ADXL345_ODR_12HZ] = UINT32_C(1000000000) / 12, + [ADXL345_ODR_12_5HZ] = UINT32_C(1000000000) / 12, [ADXL345_ODR_25HZ] = UINT32_C(1000000000) / 25, [ADXL345_ODR_50HZ] = UINT32_C(1000000000) / 50, [ADXL345_ODR_100HZ] = UINT32_C(1000000000) / 100, From a9c0a0da1b1fa6d4da1ba087a30a588c8c57d813 Mon Sep 17 00:00:00 2001 From: Luis Ubieda Date: Thu, 10 Apr 2025 14:55:00 -0400 Subject: [PATCH 5/8] sensor: adxl345: Allow fifo-watermark configurable through dts Allow for users to define the fifo-watermark on a per-instance basis through device-tree properties. This setting is validated at build time, so missing it when required, or setting an invalid value should not end up in a run-time errror (as in: it runs but nothing happens). Signed-off-by: Luis Ubieda --- drivers/sensor/adi/adxl345/adxl345.c | 18 +++++++++++++++--- dts/bindings/sensor/adi,adxl345-common.yaml | 6 ++++++ 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/sensor/adi/adxl345/adxl345.c b/drivers/sensor/adi/adxl345/adxl345.c index f517e92e489ee..4bd9f927cd6f1 100644 --- a/drivers/sensor/adi/adxl345/adxl345.c +++ b/drivers/sensor/adi/adxl345/adxl345.c @@ -482,7 +482,7 @@ static int adxl345_init(const struct device *dev) #ifdef CONFIG_ADXL345_TRIGGER rc = adxl345_configure_fifo(dev, ADXL345_FIFO_STREAMED, ADXL345_INT2, - SAMPLE_NUM); + cfg->fifo_config.fifo_samples); if (rc) { return rc; } @@ -561,7 +561,7 @@ static int adxl345_init(const struct device *dev) .odr = DT_INST_PROP(inst, odr), \ .fifo_config.fifo_mode = ADXL345_FIFO_STREAMED, \ .fifo_config.fifo_trigger = ADXL345_INT2, \ - .fifo_config.fifo_samples = SAMPLE_NUM, \ + .fifo_config.fifo_samples = DT_INST_PROP_OR(inst, fifo_watermark, 0), #define ADXL345_CONFIG_SPI(inst) \ { \ @@ -590,7 +590,19 @@ static int adxl345_init(const struct device *dev) (ADXL345_CFG_IRQ(inst)), ()) \ } -#define ADXL345_DEFINE(inst) \ +#define ADXL345_DEFINE(inst) \ + \ + BUILD_ASSERT(!IS_ENABLED(CONFIG_ADXL345_STREAM) || \ + DT_INST_NODE_HAS_PROP(inst, fifo_watermark), \ + "Streaming requires fifo-watermark property. Please set it in the" \ + "device-tree node properties"); \ + BUILD_ASSERT(COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, fifo_watermark), \ + ((DT_INST_PROP(inst, fifo_watermark) > 0) && \ + (DT_INST_PROP(inst, fifo_watermark) < 32)), \ + (true)), \ + "fifo-watermark must be between 1 and 32. Please set it in " \ + "the device-tree node properties"); \ + \ IF_ENABLED(CONFIG_ADXL345_STREAM, (ADXL345_RTIO_DEFINE(inst))); \ static struct adxl345_dev_data adxl345_data_##inst = { \ IF_ENABLED(CONFIG_ADXL345_STREAM, (.rtio_ctx = &adxl345_rtio_ctx_##inst, \ diff --git a/dts/bindings/sensor/adi,adxl345-common.yaml b/dts/bindings/sensor/adi,adxl345-common.yaml index 5ffa5fabce07f..d9f8b5c146024 100644 --- a/dts/bindings/sensor/adi,adxl345-common.yaml +++ b/dts/bindings/sensor/adi,adxl345-common.yaml @@ -31,6 +31,12 @@ properties: - 11 # ADXL345_DT_ODR_200 - 12 # ADXL345_DT_ODR_400 + fifo-watermark: + type: int + description: | + Specify the FIFO watermark level in frame count. + Valid range: 1 - 31 + int2-gpios: type: phandle-array description: | From 1f5e9904d3756e6022924b0fbff4b6d92e8f4470 Mon Sep 17 00:00:00 2001 From: Luis Ubieda Date: Thu, 10 Apr 2025 15:23:11 -0400 Subject: [PATCH 6/8] sensor: adxl345: Optimize RTIO SQE/CQE pool based on fifo-watermark Since it's directly related (we can't just burst-read the fifo at once). This patch includes a comment block explaining this rationale. Signed-off-by: Luis Ubieda --- drivers/sensor/adi/adxl345/adxl345.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/sensor/adi/adxl345/adxl345.c b/drivers/sensor/adi/adxl345/adxl345.c index 4bd9f927cd6f1..4204fdbb41542 100644 --- a/drivers/sensor/adi/adxl345/adxl345.c +++ b/drivers/sensor/adi/adxl345/adxl345.c @@ -537,12 +537,12 @@ static int adxl345_init(const struct device *dev) (I2C_DT_IODEV_DEFINE(adxl345_iodev_##inst, DT_DRV_INST(inst));), \ ()) - /* Conditionally set the RTIO size based on the presence of SPI/I2C - * lines 541 - 542. - * The sizes of sqe and cqe pools are increased due to the amount of - * multibyte reads needed for watermark using 31 samples - * (adx345_stram - line 203), using smaller amounts of samples - * to trigger an interrupt can decrease the pool sizes. + /** RTIO SQE/CQE pool size depends on the fifo-watermark because we + * can't just burst-read all the fifo data at once. Datasheet specifies + * we need to get one frame at a time (through the Data registers), + * therefore, we set all the sequence at once to properly pull each + * frame, and then end up calling the completion event so the + * application receives it). */ #define ADXL345_RTIO_DEFINE(inst) \ /* Conditionally include SPI and/or I2C parts based on their presence */ \ @@ -552,10 +552,9 @@ static int adxl345_init(const struct device *dev) COND_CODE_1(DT_INST_ON_BUS(inst, i2c), \ (ADXL345_RTIO_I2C_DEFINE(inst)), \ ()) \ - COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, spi_dt_spec) && \ - DT_INST_NODE_HAS_PROP(inst, i2c_dt_spec), \ - (RTIO_DEFINE(adxl345_rtio_ctx_##inst, 128, 128);), \ - (RTIO_DEFINE(adxl345_rtio_ctx_##inst, 64, 64);)) \ + RTIO_DEFINE(adxl345_rtio_ctx_##inst, \ + 2 * DT_INST_PROP(inst, fifo_watermark) + 2, \ + 2 * DT_INST_PROP(inst, fifo_watermark) + 2); #define ADXL345_CONFIG(inst) \ .odr = DT_INST_PROP(inst, odr), \ From ebd468005680b026d5d8d5c253058ac691ee6ff1 Mon Sep 17 00:00:00 2001 From: Luis Ubieda Date: Thu, 10 Apr 2025 22:28:10 -0400 Subject: [PATCH 7/8] sensor: adxl345: Formatting improvements on macrobatics No functional changes, only formatting changes. Signed-off-by: Luis Ubieda --- drivers/sensor/adi/adxl345/adxl345.c | 112 +++++++++++++-------------- 1 file changed, 56 insertions(+), 56 deletions(-) diff --git a/drivers/sensor/adi/adxl345/adxl345.c b/drivers/sensor/adi/adxl345/adxl345.c index 4204fdbb41542..289fb1aa6fe72 100644 --- a/drivers/sensor/adi/adxl345/adxl345.c +++ b/drivers/sensor/adi/adxl345/adxl345.c @@ -519,22 +519,22 @@ static int adxl345_init(const struct device *dev) } #ifdef CONFIG_ADXL345_TRIGGER -#define ADXL345_CFG_IRQ(inst) \ +#define ADXL345_CFG_IRQ(inst) \ .interrupt = GPIO_DT_SPEC_INST_GET(inst, int2_gpios), #else #define ADXL345_CFG_IRQ(inst) #endif /* CONFIG_ADXL345_TRIGGER */ -#define ADXL345_RTIO_SPI_DEFINE(inst) \ - COND_CODE_1(CONFIG_SPI_RTIO, \ - (SPI_DT_IODEV_DEFINE(adxl345_iodev_##inst, DT_DRV_INST(inst), \ - SPI_WORD_SET(8) | SPI_TRANSFER_MSB | \ - SPI_MODE_CPOL | SPI_MODE_CPHA, 0U);), \ +#define ADXL345_RTIO_SPI_DEFINE(inst) \ + COND_CODE_1(CONFIG_SPI_RTIO, \ + (SPI_DT_IODEV_DEFINE(adxl345_iodev_##inst, DT_DRV_INST(inst), \ + SPI_WORD_SET(8) | SPI_TRANSFER_MSB | \ + SPI_MODE_CPOL | SPI_MODE_CPHA, 0U);), \ ()) -#define ADXL345_RTIO_I2C_DEFINE(inst) \ - COND_CODE_1(CONFIG_I2C_RTIO, \ - (I2C_DT_IODEV_DEFINE(adxl345_iodev_##inst, DT_DRV_INST(inst));), \ +#define ADXL345_RTIO_I2C_DEFINE(inst) \ + COND_CODE_1(CONFIG_I2C_RTIO, \ + (I2C_DT_IODEV_DEFINE(adxl345_iodev_##inst, DT_DRV_INST(inst));), \ ()) /** RTIO SQE/CQE pool size depends on the fifo-watermark because we @@ -544,49 +544,49 @@ static int adxl345_init(const struct device *dev) * frame, and then end up calling the completion event so the * application receives it). */ -#define ADXL345_RTIO_DEFINE(inst) \ - /* Conditionally include SPI and/or I2C parts based on their presence */ \ - COND_CODE_1(DT_INST_ON_BUS(inst, spi), \ - (ADXL345_RTIO_SPI_DEFINE(inst)), \ - ()) \ - COND_CODE_1(DT_INST_ON_BUS(inst, i2c), \ - (ADXL345_RTIO_I2C_DEFINE(inst)), \ - ()) \ +#define ADXL345_RTIO_DEFINE(inst) \ + /* Conditionally include SPI and/or I2C parts based on their presence */ \ + COND_CODE_1(DT_INST_ON_BUS(inst, spi), \ + (ADXL345_RTIO_SPI_DEFINE(inst)), \ + ()) \ + COND_CODE_1(DT_INST_ON_BUS(inst, i2c), \ + (ADXL345_RTIO_I2C_DEFINE(inst)), \ + ()) \ RTIO_DEFINE(adxl345_rtio_ctx_##inst, \ 2 * DT_INST_PROP(inst, fifo_watermark) + 2, \ 2 * DT_INST_PROP(inst, fifo_watermark) + 2); -#define ADXL345_CONFIG(inst) \ - .odr = DT_INST_PROP(inst, odr), \ - .fifo_config.fifo_mode = ADXL345_FIFO_STREAMED, \ - .fifo_config.fifo_trigger = ADXL345_INT2, \ +#define ADXL345_CONFIG(inst) \ + .odr = DT_INST_PROP(inst, odr), \ + .fifo_config.fifo_mode = ADXL345_FIFO_STREAMED, \ + .fifo_config.fifo_trigger = ADXL345_INT2, \ .fifo_config.fifo_samples = DT_INST_PROP_OR(inst, fifo_watermark, 0), -#define ADXL345_CONFIG_SPI(inst) \ - { \ - .bus = {.spi = SPI_DT_SPEC_INST_GET(inst, \ - SPI_WORD_SET(8) | \ - SPI_TRANSFER_MSB | \ - SPI_MODE_CPOL | \ - SPI_MODE_CPHA, \ - 0)}, \ - .bus_is_ready = adxl345_bus_is_ready_spi, \ - .reg_access = adxl345_reg_access_spi, \ - .bus_type = ADXL345_BUS_SPI, \ - ADXL345_CONFIG(inst) \ - COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, int2_gpios), \ - (ADXL345_CFG_IRQ(inst)), ()) \ +#define ADXL345_CONFIG_SPI(inst) \ + { \ + .bus = {.spi = SPI_DT_SPEC_INST_GET(inst, \ + SPI_WORD_SET(8) | \ + SPI_TRANSFER_MSB | \ + SPI_MODE_CPOL | \ + SPI_MODE_CPHA, \ + 0)}, \ + .bus_is_ready = adxl345_bus_is_ready_spi, \ + .reg_access = adxl345_reg_access_spi, \ + .bus_type = ADXL345_BUS_SPI, \ + ADXL345_CONFIG(inst) \ + COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, int2_gpios), \ + (ADXL345_CFG_IRQ(inst)), ()) \ } -#define ADXL345_CONFIG_I2C(inst) \ - { \ - .bus = {.i2c = I2C_DT_SPEC_INST_GET(inst)}, \ - .bus_is_ready = adxl345_bus_is_ready_i2c, \ - .reg_access = adxl345_reg_access_i2c, \ - .bus_type = ADXL345_BUS_I2C, \ - ADXL345_CONFIG(inst) \ - COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, int2_gpios), \ - (ADXL345_CFG_IRQ(inst)), ()) \ +#define ADXL345_CONFIG_I2C(inst) \ + { \ + .bus = {.i2c = I2C_DT_SPEC_INST_GET(inst)}, \ + .bus_is_ready = adxl345_bus_is_ready_i2c, \ + .reg_access = adxl345_reg_access_i2c, \ + .bus_type = ADXL345_BUS_I2C, \ + ADXL345_CONFIG(inst) \ + COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, int2_gpios), \ + (ADXL345_CFG_IRQ(inst)), ()) \ } #define ADXL345_DEFINE(inst) \ @@ -602,17 +602,17 @@ static int adxl345_init(const struct device *dev) "fifo-watermark must be between 1 and 32. Please set it in " \ "the device-tree node properties"); \ \ - IF_ENABLED(CONFIG_ADXL345_STREAM, (ADXL345_RTIO_DEFINE(inst))); \ - static struct adxl345_dev_data adxl345_data_##inst = { \ - IF_ENABLED(CONFIG_ADXL345_STREAM, (.rtio_ctx = &adxl345_rtio_ctx_##inst, \ - .iodev = &adxl345_iodev_##inst,)) \ - }; \ - static const struct adxl345_dev_config adxl345_config_##inst = \ - COND_CODE_1(DT_INST_ON_BUS(inst, spi), (ADXL345_CONFIG_SPI(inst)), \ - (ADXL345_CONFIG_I2C(inst))); \ - \ - SENSOR_DEVICE_DT_INST_DEFINE(inst, adxl345_init, NULL, \ - &adxl345_data_##inst, &adxl345_config_##inst, POST_KERNEL,\ - CONFIG_SENSOR_INIT_PRIORITY, &adxl345_api_funcs); \ + IF_ENABLED(CONFIG_ADXL345_STREAM, (ADXL345_RTIO_DEFINE(inst))); \ + static struct adxl345_dev_data adxl345_data_##inst = { \ + IF_ENABLED(CONFIG_ADXL345_STREAM, (.rtio_ctx = &adxl345_rtio_ctx_##inst, \ + .iodev = &adxl345_iodev_##inst,)) \ + }; \ + static const struct adxl345_dev_config adxl345_config_##inst = \ + COND_CODE_1(DT_INST_ON_BUS(inst, spi), (ADXL345_CONFIG_SPI(inst)), \ + (ADXL345_CONFIG_I2C(inst))); \ + \ + SENSOR_DEVICE_DT_INST_DEFINE(inst, adxl345_init, NULL, \ + &adxl345_data_##inst, &adxl345_config_##inst, POST_KERNEL, \ + CONFIG_SENSOR_INIT_PRIORITY, &adxl345_api_funcs); DT_INST_FOREACH_STATUS_OKAY(ADXL345_DEFINE) From 873b090b56c937ff5ac698a280818515a7af6681 Mon Sep 17 00:00:00 2001 From: Luis Ubieda Date: Thu, 10 Apr 2025 14:59:29 -0400 Subject: [PATCH 8/8] shields: pmod_acl: Set default ODR and watermark values So applications working with this shield will continue to work as before. Signed-off-by: Luis Ubieda --- boards/shields/pmod_acl/pmod_acl.overlay | 2 ++ 1 file changed, 2 insertions(+) diff --git a/boards/shields/pmod_acl/pmod_acl.overlay b/boards/shields/pmod_acl/pmod_acl.overlay index 935655b1971a2..3cc0a947ef33d 100644 --- a/boards/shields/pmod_acl/pmod_acl.overlay +++ b/boards/shields/pmod_acl/pmod_acl.overlay @@ -12,5 +12,7 @@ reg = <0x0>; spi-max-frequency = ; status = "okay"; + odr = <25>; + fifo-watermark = <31>; }; };