From 82fcb0dc9949ae4c8f1cff474cfa2f1dfd53aae0 Mon Sep 17 00:00:00 2001 From: Guido Roncarolo Date: Tue, 2 Jul 2024 11:15:21 +0200 Subject: [PATCH 1/3] boards: shield: Support touch for the NXP LCD-PAR-S035 LCD on MCXN947 NXP LCD-PAR-S035 LCD supports touch: enable it The reset pin of the LCD and the touch controller are shared so we set alt-addr to select GT911 I2C address by probing Co-authored-by: Pascal Mareau Co-authored-by: Guido Roncarolo --- boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi | 14 +++++++++++++- boards/shields/lcd_par_s035/Kconfig.defconfig | 5 +++++ .../boards/frdm_mcxn947_mcxn947_cpu0.overlay | 17 +++++++++++++++++ .../lcd_par_s035/lcd_par_s035_8080.overlay | 17 +++++++++++++++++ 4 files changed, 52 insertions(+), 1 deletion(-) create mode 100644 boards/shields/lcd_par_s035/boards/frdm_mcxn947_mcxn947_cpu0.overlay diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi index 77708792e49d2..14340aa2b40b2 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi @@ -52,6 +52,18 @@ status = "disabled"; }; }; + + nxp_flexio_connector: flexio-connector { + compatible = "gpio-nexus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = < + 0 0 &gpio4 6 0 /* Pin 6, INT */ + 1 0 &gpio4 0 0 /* Pin 0, BOGUS RESET */ + >; + }; + }; &flexcomm1_lpspi1 { @@ -59,7 +71,7 @@ pinctrl-names = "default"; }; -&flexcomm2_lpi2c2 { +flexio_i2c: &flexcomm2_lpi2c2 { pinctrl-0 = <&pinmux_flexcomm2_lpi2c>; pinctrl-names = "default"; clock-frequency = ; diff --git a/boards/shields/lcd_par_s035/Kconfig.defconfig b/boards/shields/lcd_par_s035/Kconfig.defconfig index 07f0bb7bab1af..603f47d9a002a 100644 --- a/boards/shields/lcd_par_s035/Kconfig.defconfig +++ b/boards/shields/lcd_par_s035/Kconfig.defconfig @@ -4,6 +4,11 @@ if SHIELD_LCD_PAR_S035 if LVGL +# Configure LVGL to use touchscreen with KSCAN API + +config INPUT + default y + # Enable double buffering config LV_Z_DOUBLE_VDB default y diff --git a/boards/shields/lcd_par_s035/boards/frdm_mcxn947_mcxn947_cpu0.overlay b/boards/shields/lcd_par_s035/boards/frdm_mcxn947_mcxn947_cpu0.overlay new file mode 100644 index 0000000000000..051236f2fc07c --- /dev/null +++ b/boards/shields/lcd_par_s035/boards/frdm_mcxn947_mcxn947_cpu0.overlay @@ -0,0 +1,17 @@ +/* + * Copyright 2024, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +&flexio_i2c { + status = "okay"; + gt911_lcd_par_s035: gt911-lcd_par_s035@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + irq-gpios = <&nxp_flexio_connector 0 GPIO_ACTIVE_HIGH>; + /delete-property/ reset-gpios; + alt-addr = <0x14>; + }; +}; diff --git a/boards/shields/lcd_par_s035/lcd_par_s035_8080.overlay b/boards/shields/lcd_par_s035/lcd_par_s035_8080.overlay index eaf7b8b9c03fb..2d26fc5c865d4 100644 --- a/boards/shields/lcd_par_s035/lcd_par_s035_8080.overlay +++ b/boards/shields/lcd_par_s035/lcd_par_s035_8080.overlay @@ -10,6 +10,13 @@ chosen { zephyr,display = &st7796s; }; + + lvgl_pointer { + compatible = "zephyr,lvgl-pointer-input"; + input = <>911_lcd_par_s035>; + swap-xy; + invert-y; + }; }; &nxp_flexio_lcd { @@ -39,3 +46,13 @@ color-invert; }; }; + +&flexio_i2c { + status = "okay"; + gt911_lcd_par_s035: gt911-lcd_par_s035@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + irq-gpios = <&nxp_flexio_connector 0 GPIO_ACTIVE_HIGH>; // INT + reset-gpios = <&nxp_flexio_connector 1 GPIO_ACTIVE_HIGH>; // RESET + }; +}; From a49ebaf2f4952fd7aa24f36b6376b38c0899a8b1 Mon Sep 17 00:00:00 2001 From: Guido Roncarolo Date: Mon, 19 Aug 2024 09:11:15 +0200 Subject: [PATCH 2/3] remove duplicate full definition Signed-off-by: Guido Roncarolo --- .../lcd_par_s035/boards/frdm_mcxn947_mcxn947_cpu0.overlay | 3 --- 1 file changed, 3 deletions(-) diff --git a/boards/shields/lcd_par_s035/boards/frdm_mcxn947_mcxn947_cpu0.overlay b/boards/shields/lcd_par_s035/boards/frdm_mcxn947_mcxn947_cpu0.overlay index 051236f2fc07c..4f84dc05b36d2 100644 --- a/boards/shields/lcd_par_s035/boards/frdm_mcxn947_mcxn947_cpu0.overlay +++ b/boards/shields/lcd_par_s035/boards/frdm_mcxn947_mcxn947_cpu0.overlay @@ -8,9 +8,6 @@ &flexio_i2c { status = "okay"; gt911_lcd_par_s035: gt911-lcd_par_s035@5d { - compatible = "goodix,gt911"; - reg = <0x5d>; - irq-gpios = <&nxp_flexio_connector 0 GPIO_ACTIVE_HIGH>; /delete-property/ reset-gpios; alt-addr = <0x14>; }; From f81099621d3c5315dfc769cd1a951fd5ca4c12b2 Mon Sep 17 00:00:00 2001 From: Guido Roncarolo Date: Mon, 19 Aug 2024 09:17:41 +0200 Subject: [PATCH 3/3] use yaml Signed-off-by: Guido Roncarolo --- boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi | 4 +-- dts/bindings/gpio/nxp,flexio-lcd.yaml | 41 +++++++++++++++++++++++ 2 files changed, 43 insertions(+), 2 deletions(-) create mode 100644 dts/bindings/gpio/nxp,flexio-lcd.yaml diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi index 14340aa2b40b2..d6a7b0bc9f847 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi @@ -54,12 +54,12 @@ }; nxp_flexio_connector: flexio-connector { - compatible = "gpio-nexus"; + compatible = "nxp,flexio-lcd"; #gpio-cells = <2>; gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; gpio-map = < - 0 0 &gpio4 6 0 /* Pin 6, INT */ + 0 0 &gpio4 6 0 /* Pin 5, INT */ 1 0 &gpio4 0 0 /* Pin 0, BOGUS RESET */ >; }; diff --git a/dts/bindings/gpio/nxp,flexio-lcd.yaml b/dts/bindings/gpio/nxp,flexio-lcd.yaml new file mode 100644 index 0000000000000..ceaafac38398e --- /dev/null +++ b/dts/bindings/gpio/nxp,flexio-lcd.yaml @@ -0,0 +1,41 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + + +compatible: "nxp,flexio-lcd" + +description: | + GPIO pins exposed on NXP FlexIO LCD interface. These pins are + exposed on a 32 pin. The pins have the + following assignments: + + Pin Number Usage + 1 VDD (3v3) + 2 GND + 3 FC2_I2C_SCL-FXIO_HDR + 4 FC2_I2C_SDA-FXIO_HDR + 5 LCD_INT + 6 LCD_GPIO + 7 LCD_RST + 8 LCD_DC + 9 LCD_CS + 10 LCD_WR + 11 LCD_RD + 12 LCD_TE + 13-15 FXIO_HDR + 16 D19 + 17 D20 + 18 D21 + 19 D22 + 20 D23 + 21 D24 + 22 D25 + 23 D26 + 24 D27 + 25 D28 + 26 D29 + 27 D30 + 28 D31 + 29-32 NC + +include: [gpio-nexus.yaml, base.yaml]