From e02896345e82c0ec3f89b9bd3ea13f45786c08bc Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 13 Jun 2022 14:24:54 -0400 Subject: [PATCH 1/8] samples: remove intel_s1000_crb samples Remove all samples specific to the intel_s1000_crb board. The board is no longer supported. Signed-off-by: Anas Nashif --- .../intel_s1000_crb/audio/CMakeLists.txt | 13 - .../boards/intel_s1000_crb/audio/README.rst | 109 ----- samples/boards/intel_s1000_crb/audio/audio.py | 84 ---- .../boards/intel_s1000_crb/audio/config.yml | 12 - samples/boards/intel_s1000_crb/audio/prj.conf | 14 - .../boards/intel_s1000_crb/audio/sample.yaml | 6 - .../intel_s1000_crb/audio/src/audio_core.c | 171 ------- .../intel_s1000_crb/audio/src/audio_core.h | 65 --- .../intel_s1000_crb/audio/src/audio_driver.c | 442 ------------------ .../intel_s1000_crb/audio/src/audio_proc.c | 47 -- .../intel_s1000_crb/audio/src/framework.c | 32 -- .../intel_s1000_crb/audio/src/tuning_driver.c | 124 ----- .../intel_s1000_crb/audio/src/usb_transport.c | 162 ------- .../intel_s1000_crb/audio/src/usb_transport.h | 30 -- .../intel_s1000_crb/dmic/CMakeLists.txt | 8 - .../boards/intel_s1000_crb/dmic/README.rst | 44 -- samples/boards/intel_s1000_crb/dmic/prj.conf | 7 - .../boards/intel_s1000_crb/dmic/sample.yaml | 6 - .../intel_s1000_crb/dmic/src/dmic_sample.c | 145 ------ .../boards/intel_s1000_crb/i2s/CMakeLists.txt | 24 - samples/boards/intel_s1000_crb/i2s/README.rst | 138 ------ .../intel_s1000_crb/i2s/cable_rework.png | Bin 7372 -> 0 bytes samples/boards/intel_s1000_crb/i2s/prj.conf | 16 - .../boards/intel_s1000_crb/i2s/sample.yaml | 8 - .../intel_s1000_crb/i2s/src/i2s_sample.c | 330 ------------- .../intel_s1000_crb/intel_s1000_crb.rst | 10 - 26 files changed, 2047 deletions(-) delete mode 100644 samples/boards/intel_s1000_crb/audio/CMakeLists.txt delete mode 100644 samples/boards/intel_s1000_crb/audio/README.rst delete mode 100644 samples/boards/intel_s1000_crb/audio/audio.py delete mode 100644 samples/boards/intel_s1000_crb/audio/config.yml delete mode 100644 samples/boards/intel_s1000_crb/audio/prj.conf delete mode 100644 samples/boards/intel_s1000_crb/audio/sample.yaml delete mode 100644 samples/boards/intel_s1000_crb/audio/src/audio_core.c delete mode 100644 samples/boards/intel_s1000_crb/audio/src/audio_core.h delete mode 100644 samples/boards/intel_s1000_crb/audio/src/audio_driver.c delete mode 100644 samples/boards/intel_s1000_crb/audio/src/audio_proc.c delete mode 100644 samples/boards/intel_s1000_crb/audio/src/framework.c delete mode 100644 samples/boards/intel_s1000_crb/audio/src/tuning_driver.c delete mode 100644 samples/boards/intel_s1000_crb/audio/src/usb_transport.c delete mode 100644 samples/boards/intel_s1000_crb/audio/src/usb_transport.h delete mode 100644 samples/boards/intel_s1000_crb/dmic/CMakeLists.txt delete mode 100644 samples/boards/intel_s1000_crb/dmic/README.rst delete mode 100644 samples/boards/intel_s1000_crb/dmic/prj.conf delete mode 100644 samples/boards/intel_s1000_crb/dmic/sample.yaml delete mode 100644 samples/boards/intel_s1000_crb/dmic/src/dmic_sample.c delete mode 100644 samples/boards/intel_s1000_crb/i2s/CMakeLists.txt delete mode 100644 samples/boards/intel_s1000_crb/i2s/README.rst delete mode 100644 samples/boards/intel_s1000_crb/i2s/cable_rework.png delete mode 100644 samples/boards/intel_s1000_crb/i2s/prj.conf delete mode 100644 samples/boards/intel_s1000_crb/i2s/sample.yaml delete mode 100644 samples/boards/intel_s1000_crb/i2s/src/i2s_sample.c delete mode 100644 samples/boards/intel_s1000_crb/intel_s1000_crb.rst diff --git a/samples/boards/intel_s1000_crb/audio/CMakeLists.txt b/samples/boards/intel_s1000_crb/audio/CMakeLists.txt deleted file mode 100644 index d03e1996c2040..0000000000000 --- a/samples/boards/intel_s1000_crb/audio/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(BOARD intel_s1000_crb) -cmake_minimum_required(VERSION 3.20.0) -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(intel_s1000_crb_audio) - -target_sources(app PRIVATE src/audio_driver.c) -target_sources(app PRIVATE src/audio_core.c) -target_sources(app PRIVATE src/audio_proc.c) -target_sources(app PRIVATE src/tuning_driver.c) -target_sources(app PRIVATE src/usb_transport.c) -target_sources(app PRIVATE src/framework.c) diff --git a/samples/boards/intel_s1000_crb/audio/README.rst b/samples/boards/intel_s1000_crb/audio/README.rst deleted file mode 100644 index 0645989e7adc1..0000000000000 --- a/samples/boards/intel_s1000_crb/audio/README.rst +++ /dev/null @@ -1,109 +0,0 @@ -.. _audio_app-sample: - -Sue Creek 2-Way Audio Sample Application -######################################## - -Overview -******** - -This sample application demonstrates audio capture and playback on an -Sue Creek S1000 CRB from Intel with control from a Linux host connected -over USB. -The application uses the following drivers - -- DMIC driver (For microphone audio capture) -- I2S driver (For audio input from host, - audio output to host and audio output to codec) -- Codec driver -- USB driver and USB HID stack - -Sue Creek is the master on the I2S interfaces. -The host is a slave on I2S and is expected to send and receive audio at a -sampling frequency of 48KHz, 32 bits per sample. - -This sample application captures 8 channels of audio one from each of the -8 microphones. -The first 2 channels are buffered and forwarded to the host. -Simultaneously, 2 channels of audio from the host are buffered and forwarded -to the codec. -This bidirectional forwarding of audio demonstrates a 2-way audio stream -between the Sue Creek board's microphones/audio line-out and -the host. - -After the app starts, one may use the ALSA aplay/arecord commands on -a Linux host connected to Sue Creek board over the I2S bus to play and -record audio. - -.. code-block:: bash - - $ aplay -f S32_LE -r 48000 -c 2 -D - $ arecord -f S32_LE -r 48000 -c 2 -D - -The same (or a different) Linux host may be connected to the USB interface -of Sue Creek board. This host will then be able to send control commands -over USB. In this sample application, control of starting and stopping audio -transfers is implemented. - -Requirements -************ - -This application uses an Sue Creek Customer Reference Board (CRB) -with a circular 8 microphone array board. -The Microphone array board contains a TI TLV320DAC3101 DAC for line-level -audio output. - -Cable Rework -============ - -A rework of the host to CRB cable is required for playing audio from host. -Pin 12 needs to be wired to Pin 29 on the 40-pin connector of the cable. - -.. image:: ../i2s/cable_rework.png - :width: 442px - :alt: Cable rework to play audio from host - -Building -******** - -.. zephyr-app-commands:: - :zephyr-app: samples/boards/intel_s1000_crb/audio - :board: - :goals: build - :compact: - -Running -******* - -Upon power up and downloading the application image (or booting the board -with the image in flash), the application starts without user intervention -and audio is transferred from the microphones to the connected host and -from the host to the audio codec output. - -If a Linux host is connected via USB to the Sue Creek board, -the python script ``audio.py`` can be used to stop/[re]start audio transfer. - -.. code-block:: bash - - $ cd $ZEPHYR_BASE/samples/boards/intel_s1000_crb/audio - $ sudo -E python3 audio.py stop - $ sudo -E python3 audio.py start - -Sample Output -============= - -Console output --------------- - -.. code-block:: console - - [00:00:00.370,000] tuning: Starting tuning driver I/O thread ... - [00:00:00.370,000] audio_io: Starting Audio Driver thread ,,, - [00:00:00.370,000] audio_io: Configuring Host Audio Streams ... - [00:00:00.370,000] audio_io: Configuring Peripheral Audio Streams ... - [00:00:00.370,000] audio_proc: Starting small block processing thread ... - [00:00:00.370,000] audio_proc: Starting large block processing thread ... - [00:00:00.370,000] audio_io: Initializing Audio Core Engine ... - [00:00:00.370,000] audio_io: Starting Audio I/O... - [00:00:00.420,000] framework: Starting framework background thread ... - [00:00:06.520,000] audio_io: Stopped Audio I/O... - [00:00:11.200,000] audio_io: Starting Audio I/O... diff --git a/samples/boards/intel_s1000_crb/audio/audio.py b/samples/boards/intel_s1000_crb/audio/audio.py deleted file mode 100644 index 27d6d746cee75..0000000000000 --- a/samples/boards/intel_s1000_crb/audio/audio.py +++ /dev/null @@ -1,84 +0,0 @@ -#!/usr/bin/env python3 -# -# Copyright (c) 2019 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# -# Author: Sathish Kuttan - -# This script sends a command to either start or stop audio streams -# to an Intel Sue Creek S1000 target connected to a Linux host -# over USB. -# The target should be running the sample audio application from the -# sample project to which this script belongs. - -import hid -import yaml -import os -import argparse - -class Device: - def __init__(self): - """ - Reads configuration file to determine the USB VID/PID of - the Sue Creek target. - When the script is run using sudo permission, the - manufacturer and product strings are printed - """ - config_file = os.path.join(os.path.dirname(__file__), 'config.yml') - with open(config_file, 'r') as ymlfile: - config = yaml.safe_load(ymlfile) - self.name = config['general']['name'] - self.usb_vid = config['usb']['vid'] - self.usb_pid = config['usb']['pid'] - self.hid_dev = hid.device() - if self.hid_dev is None: - print('Device not found') - else: - self.hid_dev.open(self.usb_vid, self.usb_pid) - - def start_audio(self): - """ - Sends a command to start the audio transfers - in the Sue Creek target. - """ - # space for 1 byte report id, 2 bytes of padding and 1 byte report size - command = 'start_audio'.encode('utf-8') + b'\x00' - command += b'\x00' * (56 - len(command)) - cmd_len = len(command) // 4 + 1 - command = b'\x01\x00' + cmd_len.to_bytes(2, byteorder='little') + \ - command - command = b'\x01\x00\x00\x38' + command - print('Starting Audio on %s ...' % self.hid_dev.get_product_string()) - self.hid_dev.send_feature_report(command) - self.hid_dev.read(len(command)) - - def stop_audio(self): - """ - Sends a command to stop the running audio transfers - in the Sue Creek target. - """ - # space for 1 byte report id, 2 bytes of padding and 1 byte report size - command = 'stop_audio'.encode('utf-8') + b'\x00' - command += b'\x00' * (56 - len(command)) - cmd_len = len(command) // 4 + 1 - command = b'\x02\x00' + cmd_len.to_bytes(2, byteorder='little') + \ - command - command = b'\x01\x00\x00\x38' + command - print('Stopping Audio on %s ...' % self.hid_dev.get_product_string()) - self.hid_dev.send_feature_report(command) - self.hid_dev.read(len(command)) - -def main(): - parser = argparse.ArgumentParser(epilog='NOTE: use sudo -E %(prog)s to run the script') - parser.add_argument('command', choices=['start', 'stop'], - help='start or stop audio streams') - args = parser.parse_args() - sue_creek = Device() - if args.command == 'start': - sue_creek.start_audio() - if args.command == 'stop': - sue_creek.stop_audio() - -if __name__ == '__main__': - main() diff --git a/samples/boards/intel_s1000_crb/audio/config.yml b/samples/boards/intel_s1000_crb/audio/config.yml deleted file mode 100644 index 753681408efa7..0000000000000 --- a/samples/boards/intel_s1000_crb/audio/config.yml +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2019 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# -# Author: Sathish Kuttan - -general: - name: Sue Creek - -usb: - vid: 0x8087 # Vendor ID: Intel Corporation - pid: 0x0b1a # Product ID diff --git a/samples/boards/intel_s1000_crb/audio/prj.conf b/samples/boards/intel_s1000_crb/audio/prj.conf deleted file mode 100644 index f058b33be95db..0000000000000 --- a/samples/boards/intel_s1000_crb/audio/prj.conf +++ /dev/null @@ -1,14 +0,0 @@ -CONFIG_LOG=y -CONFIG_SOC_LOG_LEVEL_WRN=y -CONFIG_AUDIO_CODEC_LOG_LEVEL_WRN=y -CONFIG_I2S_LOG_LEVEL_WRN=y -CONFIG_DMA_LOG_LEVEL_WRN=y -CONFIG_GPIO=y -CONFIG_I2S=y -CONFIG_I2C=y -CONFIG_DMA=y -CONFIG_AUDIO=y -CONFIG_USB_DEVICE_STACK=y -CONFIG_USB_DEVICE_HID=y -CONFIG_HID_INTERRUPT_EP_MPS=64 -CONFIG_USB_HID_POLL_INTERVAL_MS=1 diff --git a/samples/boards/intel_s1000_crb/audio/sample.yaml b/samples/boards/intel_s1000_crb/audio/sample.yaml deleted file mode 100644 index cb0868487d662..0000000000000 --- a/samples/boards/intel_s1000_crb/audio/sample.yaml +++ /dev/null @@ -1,6 +0,0 @@ -sample: - name: 2-way Audio Forwarding Sample -tests: - sample.board.intel_s1000_crb.audio: - platform_allow: intel_s1000_crb - tags: audio diff --git a/samples/boards/intel_s1000_crb/audio/src/audio_core.c b/samples/boards/intel_s1000_crb/audio/src/audio_core.c deleted file mode 100644 index fe23152d31116..0000000000000 --- a/samples/boards/intel_s1000_crb/audio/src/audio_core.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) 2019 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define LOG_LEVEL LOG_LEVEL_INF -#include -LOG_MODULE_REGISTER(audio_core); - -#include -#include "audio_core.h" - -/* - * stereo mic in - * stereo host in - * stereo speaker out - * stereo host out - */ -#define AUDIO_ACTIVE_CHANNELS 2 - -/* core audio processing buffers with interleaved samples */ -static int32_t mic_input[AUDIO_ACTIVE_CHANNELS][AUDIO_SAMPLES_PER_FRAME]; -static int32_t host_input[AUDIO_ACTIVE_CHANNELS][AUDIO_SAMPLES_PER_FRAME]; - -static bool tuning_reply_ready; -static uint32_t *tuning_command_buffer; -static uint32_t tuning_cmd_buf_size_in_words; - -#define CMD_START_AUDIO 1 -#define CMD_STOP_AUDIO 2 - -int audio_core_initialize(void) -{ - return 0; -} - -int audio_core_process_mic_source(int32_t *buffer, int channels) -{ - int sample; - int channel; - int32_t *read; - - read = buffer; - - /* copy audio samples from mic source buffer to mic_input */ - for (sample = 0; sample < AUDIO_SAMPLES_PER_FRAME; sample++) { - for (channel = 0; channel < AUDIO_ACTIVE_CHANNELS; channel++) { - mic_input[channel][sample] = read[channel]; - } - read += channels; - } - - return 0; -} - -int audio_core_process_host_source(int32_t *buffer, int channels) -{ - int sample; - int channel; - int32_t *read; - - read = buffer; - - /* copy audio samples from host source buffer to host_input */ - for (sample = 0; sample < AUDIO_SAMPLES_PER_FRAME; sample++) { - for (channel = 0; channel < AUDIO_ACTIVE_CHANNELS; channel++) { - host_input[channel][sample] = read[channel]; - } - read += channels; - } - - return 0; -} - -int audio_core_process_speaker_sink(int32_t *buffer, int channels) -{ - int sample; - int channel; - int32_t *write; - - write = buffer; - - /* copy audio samples from host_input to speaker sink buffer */ - for (sample = 0; sample < AUDIO_SAMPLES_PER_FRAME; sample++) { - for (channel = 0; channel < AUDIO_ACTIVE_CHANNELS; channel++) { - write[channel] = host_input[channel][sample]; - } - write += channels; - } - - return 0; -} - -int audio_core_process_host_sink(int32_t *buffer, int channels) -{ - int sample; - int channel; - int32_t *write; - - write = buffer; - - /* copy audio samples from mic_input to host sink buffer */ - for (sample = 0; sample < AUDIO_SAMPLES_PER_FRAME; sample++) { - for (channel = 0; channel < AUDIO_ACTIVE_CHANNELS; channel++) { - write[channel] = mic_input[channel][sample]; - } - write += channels; - } - - return 0; -} - -int audio_core_notify_frame_tick(void) -{ - return 0; -} - -int audio_core_tuning_interface_init(uint32_t *command_buffer, uint32_t size_in_words) -{ - tuning_command_buffer = command_buffer; - tuning_cmd_buf_size_in_words = size_in_words; - return 0; -} - -int audio_core_notify_tuning_cmd(void) -{ - uint32_t first_word = *((uint32_t *)tuning_command_buffer); - uint32_t command = (first_word << 16) >> 16; - - switch (command) { - case CMD_START_AUDIO: - audio_driver_start(); - break; - - case CMD_STOP_AUDIO: - audio_driver_stop(); - break; - - default: - LOG_INF("Unknown command %d", command); - } - - tuning_reply_ready = true; - return 0; -} - -bool audio_core_is_tuning_reply_ready(void) -{ - if (tuning_reply_ready == true) { - tuning_reply_ready = false; - return true; - } - - return false; -} - -int audio_core_process_background_tasks(void) -{ - return 0; -} - -int audio_core_process_small_blocks(void) -{ - return 0; -} - -int audio_core_process_large_blocks(void) -{ - return 0; -} diff --git a/samples/boards/intel_s1000_crb/audio/src/audio_core.h b/samples/boards/intel_s1000_crb/audio/src/audio_core.h deleted file mode 100644 index 5087e22e7d20e..0000000000000 --- a/samples/boards/intel_s1000_crb/audio/src/audio_core.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2019 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef AUDIO_CORE__H -#define AUDIO_CORE__H - -/* scheduling priority used by each thread */ -#define TUN_DRV_IO_THREAD_PRIORITY -3 -#define AUDIO_DRIVER_THREAD_PRIORITY 2 -#define AUDIO_SM_BLOCK_PROC_THREAD_PRIORITY 3 -#define AUDIO_LG_BLOCK_PROC_THREAD_PRIORITY 4 -#define FRAMEWORK_BG_THREAD_PRIORITY 99 - -/* size of stack area used by each thread */ -#define AUDIO_DRIVER_THREAD_STACKSIZE 2048 -#define TUN_DRV_IO_THREAD_STACK_SIZE 1024 -#define FRAMEWORK_BG_THREAD_STACK_SIZE 1024 -#define AUDIO_SM_BLOCK_PROC_THREAD_STACK_SIZE 1024 -#define AUDIO_LG_BLOCK_PROC_THREAD_STACK_SIZE 1024 - -/* input audio channels */ -#define AUDIO_MIC_INPUT_CHANNEL_COUNT 8 -#define AUDIO_HOST_INPUT_CHANNEL_COUNT 2 -#define AUDIO_INPUT_CHANNEL_COUNT \ - (AUDIO_MIC_INPUT_CHANNEL_COUNT + \ - AUDIO_HOST_OUTPUT_CHANNEL_COUNT) - -/* output audio channels */ -#define AUDIO_SPEAKER_OUTPUT_CHANNEL_COUNT 2 -#define AUDIO_HOST_OUTPUT_CHANNEL_COUNT 2 -#define AUDIO_OUTPUT_CHANNEL_COUNT \ - (AUDIO_SPEAKER_OUTPUT_CHANNEL_COUNT + \ - AUDIO_HOST_OUTPUT_CHANNEL_COUNT) - -/* samples per frame */ -#define AUDIO_SAMPLES_PER_FRAME 192 - -int audio_core_initialize(void); -int audio_core_process_mic_source(int32_t *buffer, int channels); -int audio_core_process_host_source(int32_t *buffer, int channels); -int audio_core_process_speaker_sink(int32_t *buffer, int channels); -int audio_core_process_host_sink(int32_t *buffer, int channels); -int audio_core_notify_frame_tick(void); - -/* tuning interface prototypes */ -int audio_core_tuning_interface_init(uint32_t *command_buffer, - uint32_t size_in_words); -int audio_core_notify_tuning_cmd(void); -bool audio_core_is_tuning_reply_ready(void); - -/* audio driver prototypes */ -int audio_driver_start(void); -int audio_driver_stop(void); - -/* tick for processing background tasks, called from the background thread */ -int audio_core_process_background_tasks(void); - -/* tick for processing small audio blocks */ -int audio_core_process_small_blocks(void); -int audio_core_process_large_blocks(void); - -#endif /* AUDIO_CORE__H */ diff --git a/samples/boards/intel_s1000_crb/audio/src/audio_driver.c b/samples/boards/intel_s1000_crb/audio/src/audio_driver.c deleted file mode 100644 index f81e3f4db739e..0000000000000 --- a/samples/boards/intel_s1000_crb/audio/src/audio_driver.c +++ /dev/null @@ -1,442 +0,0 @@ -/* - * Copyright (c) 2019 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define LOG_LEVEL LOG_LEVEL_INF -#include -LOG_MODULE_REGISTER(audio_io); - -#include - -#include -#include -#include - -#include -#include -#include "audio_core.h" - -#define DMIC_DEV_NAME "PDM" -#define SPK_OUT_DEV_NAME "I2S_1" -#define HOST_INOUT_DEV_NAME "I2S_2" - -#define NUM_HOST_CHANNELS 2 -#define NUM_SPK_CHANNELS 2 -#define NUM_MIC_CHANNELS 8 - -#define AUDIO_SAMPLE_FREQ 48000 -#define AUDIO_SAMPLE_WIDTH 32 - -#define HOST_FRAME_SAMPLES (AUDIO_SAMPLES_PER_FRAME * NUM_HOST_CHANNELS) -#define MIC_FRAME_SAMPLES (AUDIO_SAMPLES_PER_FRAME * NUM_MIC_CHANNELS) -#define SPK_FRAME_SAMPLES (AUDIO_SAMPLES_PER_FRAME * NUM_SPK_CHANNELS) - -#define HOST_FRAME_BYTES (HOST_FRAME_SAMPLES * AUDIO_SAMPLE_WIDTH / 8) -#define MIC_FRAME_BYTES (MIC_FRAME_SAMPLES * AUDIO_SAMPLE_WIDTH / 8) -#define SPK_FRAME_BYTES (SPK_FRAME_SAMPLES * AUDIO_SAMPLE_WIDTH / 8) - -#define SPK_OUT_BUF_COUNT 2 -#define MIC_IN_BUF_COUNT 2 -#define HOST_INOUT_BUF_COUNT 4 /* 2 for TX and 2 for RX */ - -static void audio_drv_thread(void); - -__attribute__((section(".dma_buffers"))) static struct { - int32_t host_inout[HOST_INOUT_BUF_COUNT][HOST_FRAME_SAMPLES]; - int32_t spk_out[SPK_OUT_BUF_COUNT][SPK_FRAME_SAMPLES]; - int32_t mic_in[MIC_IN_BUF_COUNT][MIC_FRAME_SAMPLES]; -} audio_buffers; - -static const struct device *codec_dev; -static const struct device *i2s_spk_out_dev; -static const struct device *i2s_host_dev; -static const struct device *dmic_device; - -static struct k_mem_slab mic_in_mem_slab; -static struct k_mem_slab host_inout_mem_slab; -static struct k_mem_slab spk_out_mem_slab; - -K_SEM_DEFINE(audio_drv_sync_sem, 0, 1); -static bool audio_io_started; - -K_THREAD_DEFINE(audio_drv_thread_id, AUDIO_DRIVER_THREAD_STACKSIZE, - audio_drv_thread, NULL, NULL, NULL, - AUDIO_DRIVER_THREAD_PRIORITY, 0, 0); - -static void audio_driver_process_audio_input(void) -{ - int32_t *host_in_buf; - int32_t *mic_in_buf; - size_t size; - int ret; - - /* read capture input buffer */ - ret = dmic_read(dmic_device, 0, (void **)&mic_in_buf, &size, SYS_FOREVER_MS); - if (ret) { - LOG_ERR("dmic_device read failed %d", ret); - return; - } - - /* read playback input buffer */ - ret = i2s_read(i2s_host_dev, (void **)&host_in_buf, &size); - if (ret) { - LOG_ERR("i2s_host_dev read failed %d", ret); - return; - } - - audio_core_process_mic_source(mic_in_buf, NUM_MIC_CHANNELS); - audio_core_process_host_source(host_in_buf, NUM_HOST_CHANNELS); - - /* free the consumed buffers */ - k_mem_slab_free(&mic_in_mem_slab, (void **)&mic_in_buf); - k_mem_slab_free(&host_inout_mem_slab, (void **)&host_in_buf); -} - -static void audio_driver_process_audio_output(void) -{ - int32_t *spk_out_buf; - int32_t *host_out_buf; - int ret; - - ret = k_mem_slab_alloc(&spk_out_mem_slab, (void *)&spk_out_buf, - K_NO_WAIT); - if (ret) { - LOG_ERR("speaker out buffer alloc failed %d mem_slab %p", - ret, &spk_out_mem_slab); - } - - ret = k_mem_slab_alloc(&host_inout_mem_slab, (void *)&host_out_buf, - K_NO_WAIT); - if (ret) { - LOG_ERR("host out audio buffer alloc failed %d", ret); - } - - audio_core_process_speaker_sink(spk_out_buf, NUM_SPK_CHANNELS); - audio_core_process_host_sink(host_out_buf, NUM_HOST_CHANNELS); - - /* write buffer */ - ret = i2s_write(i2s_spk_out_dev, (void *)spk_out_buf, SPK_FRAME_BYTES); - if (ret) { - LOG_ERR("i2s_write for speaker failed %d", ret); - } - - ret = i2s_write(i2s_host_dev, (void *)host_out_buf, HOST_FRAME_BYTES); - if (ret) { - LOG_ERR("i2s_write for host failed %d", ret); - } -} - -static int audio_driver_send_zeros_frame(void) -{ - int ret = 0; - void *spk_out_buf; - void *host_out_buf; - - /* allocate speaker output buffer */ - ret = k_mem_slab_alloc(&spk_out_mem_slab, &spk_out_buf, K_NO_WAIT); - if (ret) { - LOG_ERR("Buffer alloc for spk output failed %d", ret); - return ret; - } - - /* allocate host output buffer */ - ret = k_mem_slab_alloc(&host_inout_mem_slab, &host_out_buf, K_NO_WAIT); - if (ret) { - LOG_ERR("Buffer alloc for host output failed %d", ret); - return ret; - } - - /* fill buffer with zeros */ - memset(spk_out_buf, 0, SPK_FRAME_BYTES); - memset(host_out_buf, 0, HOST_FRAME_BYTES); - - ret = i2s_write(i2s_spk_out_dev, spk_out_buf, SPK_FRAME_BYTES); - if (ret) { - LOG_ERR("i2s_write for spk output failed %d", ret); - return ret; - } - - ret = i2s_write(i2s_host_dev, host_out_buf, HOST_FRAME_BYTES); - if (ret) { - LOG_ERR("i2s_write for host output failed %d", ret); - return ret; - } - - return ret; -} - -static int audio_driver_start_host_streams(void) -{ - int ret = 0; - - /* trigger transmission */ - ret = i2s_trigger(i2s_host_dev, I2S_DIR_TX, I2S_TRIGGER_START); - if (ret) { - LOG_ERR("I2S TX failed with code %d", ret); - } - - /* trigger reception */ - ret = i2s_trigger(i2s_host_dev, I2S_DIR_RX, I2S_TRIGGER_START); - if (ret) { - LOG_ERR("I2S RX failed with code %d", ret); - } - - return ret; -} - -static int audio_driver_stop_host_streams(void) -{ - int ret; - - /* stop transmission */ - ret = i2s_trigger(i2s_host_dev, I2S_DIR_TX, I2S_TRIGGER_STOP); - if (ret) { - LOG_ERR("I2S TX failed with code %d", ret); - } - - /* stop reception */ - ret = i2s_trigger(i2s_host_dev, I2S_DIR_RX, I2S_TRIGGER_STOP); - if (ret) { - LOG_ERR("I2S RX failed with code %d", ret); - } - - return ret; -} - -static void audio_driver_config_host_streams(void) -{ - int ret; - struct i2s_config i2s_cfg; - - i2s_host_dev = device_get_binding(HOST_INOUT_DEV_NAME); - if (!i2s_host_dev) { - LOG_ERR("unable to find device %s", HOST_INOUT_DEV_NAME); - return; - } - - /* Configure */ - i2s_cfg.word_size = AUDIO_SAMPLE_WIDTH; - i2s_cfg.channels = NUM_HOST_CHANNELS; - i2s_cfg.format = I2S_FMT_DATA_FORMAT_I2S | I2S_FMT_CLK_NF_NB; - i2s_cfg.options = I2S_OPT_FRAME_CLK_MASTER | I2S_OPT_BIT_CLK_MASTER; - i2s_cfg.frame_clk_freq = AUDIO_SAMPLE_FREQ; - i2s_cfg.block_size = HOST_FRAME_BYTES; - i2s_cfg.mem_slab = &host_inout_mem_slab; - i2s_cfg.timeout = 0; - - k_mem_slab_init(&host_inout_mem_slab, &audio_buffers.host_inout[0][0], - HOST_FRAME_BYTES, HOST_INOUT_BUF_COUNT); - - /* Configure host input/output I2S */ - ret = i2s_configure(i2s_host_dev, I2S_DIR_RX, &i2s_cfg); - if (ret != 0) { - LOG_ERR("i2s_configure RX failed with %d error", ret); - } -} - -static void audio_driver_config_periph_streams(void) -{ - int ret; - struct i2s_config i2s_cfg; - struct audio_codec_cfg codec = { - .dai_type = AUDIO_DAI_TYPE_I2S, - .dai_cfg.i2s = { - .word_size = AUDIO_SAMPLE_WIDTH, - .channels = NUM_SPK_CHANNELS, - .format = I2S_FMT_DATA_FORMAT_I2S | - I2S_FMT_CLK_NF_NB, - .options = I2S_OPT_FRAME_CLK_SLAVE | - I2S_OPT_BIT_CLK_SLAVE, - .frame_clk_freq = AUDIO_SAMPLE_FREQ, - .block_size = SPK_FRAME_BYTES, - .timeout = 0, - }, - }; - struct pcm_stream_cfg stream = { - .pcm_rate = AUDIO_SAMPLE_FREQ, - .pcm_width = AUDIO_SAMPLE_WIDTH, - .block_size = MIC_FRAME_BYTES, - .mem_slab = &mic_in_mem_slab, - }; - struct dmic_cfg cfg = { - .io = { - .min_pdm_clk_freq = 1024000, - .max_pdm_clk_freq = 4800000, - .min_pdm_clk_dc = 48, - .max_pdm_clk_dc = 52, - .pdm_clk_pol = 0, - .pdm_data_pol = 0, - }, - .streams = &stream, - .channel = { - .req_chan_map_lo = - dmic_build_channel_map(0, 0, PDM_CHAN_RIGHT) | - dmic_build_channel_map(1, 0, PDM_CHAN_LEFT) | - dmic_build_channel_map(2, 2, PDM_CHAN_RIGHT) | - dmic_build_channel_map(3, 2, PDM_CHAN_LEFT) | - dmic_build_channel_map(4, 1, PDM_CHAN_RIGHT) | - dmic_build_channel_map(5, 1, PDM_CHAN_LEFT) | - dmic_build_channel_map(6, 3, PDM_CHAN_RIGHT) | - dmic_build_channel_map(7, 3, PDM_CHAN_LEFT), - .req_num_chan = NUM_MIC_CHANNELS, - .req_num_streams = 1, - }, - }; - - k_mem_slab_init(&mic_in_mem_slab, &audio_buffers.mic_in[0][0], - MIC_FRAME_BYTES, MIC_IN_BUF_COUNT); - dmic_device = device_get_binding(DMIC_DEV_NAME); - if (!dmic_device) { - LOG_ERR("unable to find device %s", DMIC_DEV_NAME); - return; - } - - ret = dmic_configure(dmic_device, &cfg); - if (ret != 0) { - LOG_ERR("dmic_configure failed with %d error", ret); - } - - i2s_spk_out_dev = device_get_binding(SPK_OUT_DEV_NAME); - if (!i2s_spk_out_dev) { - LOG_ERR("unable to find device %s", SPK_OUT_DEV_NAME); - return; - } - - codec_dev = device_get_binding(DT_LABEL(DT_INST(0, ti_tlv320dac))); - if (!codec_dev) { - LOG_ERR("unable to find device %s", DT_LABEL(DT_INST(0, ti_tlv320dac))); - return; - } - - /* Configure */ - i2s_cfg.word_size = AUDIO_SAMPLE_WIDTH; - i2s_cfg.channels = NUM_SPK_CHANNELS; - i2s_cfg.format = I2S_FMT_DATA_FORMAT_I2S | I2S_FMT_CLK_NF_NB; - i2s_cfg.options = I2S_OPT_FRAME_CLK_MASTER | I2S_OPT_BIT_CLK_MASTER; - i2s_cfg.frame_clk_freq = AUDIO_SAMPLE_FREQ; - i2s_cfg.block_size = SPK_FRAME_BYTES; - i2s_cfg.mem_slab = &spk_out_mem_slab; - i2s_cfg.timeout = 0; - k_mem_slab_init(&spk_out_mem_slab, &audio_buffers.spk_out[0][0], - SPK_FRAME_BYTES, SPK_OUT_BUF_COUNT); - - ret = i2s_configure(i2s_spk_out_dev, I2S_DIR_TX, &i2s_cfg); - if (ret != 0) { - LOG_ERR("i2s_configure TX failed with %d error", ret); - } - - /* configure codec */ - codec.mclk_freq = soc_get_ref_clk_freq(); - audio_codec_configure(codec_dev, &codec); -} - -static void audio_driver_start_periph_streams(void) -{ - int ret; - - /* start codec output */ - audio_codec_start_output(codec_dev); - - ret = i2s_trigger(i2s_spk_out_dev, I2S_DIR_TX, I2S_TRIGGER_START); - if (ret) { - LOG_ERR("I2S TX failed with code %d", ret); - } - - ret = dmic_trigger(dmic_device, DMIC_TRIGGER_START); - if (ret) { - LOG_ERR("dmic_trigger failed with code %d", ret); - } -} - -static void audio_driver_stop_periph_streams(void) -{ - int ret; - - ret = i2s_trigger(i2s_spk_out_dev, I2S_DIR_TX, I2S_TRIGGER_STOP); - if (ret) { - LOG_ERR("I2S TX failed with code %d", ret); - } - - /* trigger transmission */ - ret = dmic_trigger(dmic_device, DMIC_TRIGGER_STOP); - if (ret) { - LOG_ERR("dmic_trigger failed with code %d", ret); - } -} - -int audio_driver_start(void) -{ - if (audio_io_started == true) { - LOG_INF("Audio I/O already started ..."); - return 0; - } - - LOG_INF("Starting Audio I/O..."); - - /* - * start the playback path first followed by the capture path - * This ensures that by the time the capture frame tick is - * processed, the playback input samples are ready and playback - * output samples are transmitted - */ - audio_driver_send_zeros_frame(); - audio_driver_send_zeros_frame(); - - audio_driver_start_host_streams(); - audio_driver_start_periph_streams(); - - audio_io_started = true; - k_sem_give(&audio_drv_sync_sem); - - return 0; -} - -int audio_driver_stop(void) -{ - if (audio_io_started == false) { - LOG_INF("Audio I/O already stopped ..."); - return 0; - } - - k_sem_take(&audio_drv_sync_sem, K_FOREVER); - audio_driver_stop_host_streams(); - audio_driver_stop_periph_streams(); - audio_io_started = false; - LOG_INF("Stopped Audio I/O..."); - - return 0; -} - -static void audio_drv_thread(void) -{ - LOG_INF("Starting Audio Driver thread ,,,"); - - LOG_INF("Configuring Host Audio Streams ..."); - audio_driver_config_host_streams(); - - LOG_INF("Configuring Peripheral Audio Streams ..."); - audio_driver_config_periph_streams(); - - LOG_INF("Initializing Audio Core Engine ..."); - audio_core_initialize(); - - LOG_DBG("mic_in_mem_slab %p", &mic_in_mem_slab); - LOG_DBG("spk_out_mem_slab %p", &spk_out_mem_slab); - LOG_DBG("host_inout_mem_slab %p", &host_inout_mem_slab); - - audio_driver_start(); - - while (true) { - k_sem_take(&audio_drv_sync_sem, K_FOREVER); - - audio_driver_process_audio_input(); - - audio_driver_process_audio_output(); - - k_sem_give(&audio_drv_sync_sem); - - audio_core_notify_frame_tick(); - } -} diff --git a/samples/boards/intel_s1000_crb/audio/src/audio_proc.c b/samples/boards/intel_s1000_crb/audio/src/audio_proc.c deleted file mode 100644 index f74cb24a3373c..0000000000000 --- a/samples/boards/intel_s1000_crb/audio/src/audio_proc.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2019 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define LOG_LEVEL LOG_LEVEL_INF -#include -LOG_MODULE_REGISTER(audio_proc); - -#include - -#include "audio_core.h" - -K_SEM_DEFINE(audio_proc_small_block_sem, 0, 1); -K_SEM_DEFINE(audio_proc_large_block_sem, 0, 1); - -static void audio_proc_small_block_thread(void); -static void audio_proc_large_block_thread(void); - -K_THREAD_DEFINE(audio_proc_sm_blk_tid, AUDIO_SM_BLOCK_PROC_THREAD_STACK_SIZE, - audio_proc_small_block_thread, NULL, NULL, NULL, - AUDIO_SM_BLOCK_PROC_THREAD_PRIORITY, 0, 0); - -K_THREAD_DEFINE(audio_proc_lg_blk_tid, AUDIO_LG_BLOCK_PROC_THREAD_STACK_SIZE, - audio_proc_large_block_thread, NULL, NULL, NULL, - AUDIO_LG_BLOCK_PROC_THREAD_PRIORITY, 0, 0); - -static void audio_proc_small_block_thread(void) -{ - LOG_INF("Starting small block processing thread ..."); - - while (true) { - k_sem_take(&audio_proc_small_block_sem, K_FOREVER); - audio_core_process_small_blocks(); - } -} - -static void audio_proc_large_block_thread(void) -{ - LOG_INF("Starting large block processing thread ..."); - - while (true) { - k_sem_take(&audio_proc_large_block_sem, K_FOREVER); - audio_core_process_large_blocks(); - } -} diff --git a/samples/boards/intel_s1000_crb/audio/src/framework.c b/samples/boards/intel_s1000_crb/audio/src/framework.c deleted file mode 100644 index cfc810a951aeb..0000000000000 --- a/samples/boards/intel_s1000_crb/audio/src/framework.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2019 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define LOG_LEVEL LOG_LEVEL_INF -#include -LOG_MODULE_REGISTER(framework); - -#include - -#include "audio_core.h" - -extern int tun_drv_packet_handler(void); -static int framework_background_thread(void); - -K_THREAD_DEFINE(framework_bg_thread_id, FRAMEWORK_BG_THREAD_STACK_SIZE, - framework_background_thread, NULL, NULL, NULL, - FRAMEWORK_BG_THREAD_PRIORITY, 0, 0); - -static int framework_background_thread(void) -{ - LOG_INF("Starting framework background thread ..."); - - while (true) { - tun_drv_packet_handler(); - audio_core_process_background_tasks(); - } - - return 0; -} diff --git a/samples/boards/intel_s1000_crb/audio/src/tuning_driver.c b/samples/boards/intel_s1000_crb/audio/src/tuning_driver.c deleted file mode 100644 index 6f41b9afd8c7c..0000000000000 --- a/samples/boards/intel_s1000_crb/audio/src/tuning_driver.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2019 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define LOG_LEVEL LOG_LEVEL_INF -#include -LOG_MODULE_REGISTER(tuning); - -#include - -#include -#include - -#include "audio_core.h" -#include "usb_transport.h" - -static void tun_drv_process_command(uint8_t *data, uint32_t len); - -/* Buffer size in "words" for the tuning commands and replies */ -#define TUN_DRV_CMD_MAX_WORDS (264) -#define TUN_DRV_CMD_MAX_BYTES (TUN_DRV_CMD_MAX_WORDS << 2) - -#define TUN_DRV_ALERT_Q_LEN ((TUN_DRV_CMD_MAX_BYTES +\ - USB_TPORT_HID_REPORT_DATA_LEN - 1) /\ - USB_TPORT_HID_REPORT_DATA_LEN) - -static struct { - /* room for transport header */ - union usb_hid_report_hdr header; - - /* command buffer for the tuning interface */ - uint8_t buffer[TUN_DRV_CMD_MAX_BYTES]; - - /* length of valid data in the buffer */ - uint32_t len; - - /* index into the buffer where incoming data is copied */ - uint32_t index; -} __packed command_buffer; - -/* Allocate a synchronization semaphore */ -K_SEM_DEFINE(tun_drv_sem, 0, 1); - -static int tun_drv_io_thread(void); - -K_THREAD_DEFINE(tun_drv_io_thread_id, TUN_DRV_IO_THREAD_STACK_SIZE, - tun_drv_io_thread, NULL, NULL, NULL, TUN_DRV_IO_THREAD_PRIORITY, - 0, 0); - -static int tun_drv_io_thread(void) -{ - LOG_INF("Starting tuning driver I/O thread ..."); - - /* initialize the audio core's tuning interface */ - audio_core_tuning_interface_init((uint32_t *)command_buffer.buffer, - TUN_DRV_CMD_MAX_WORDS); - - /* initialize the tuning transport protocol driver */ - usb_transport_init(tun_drv_process_command); - - while (true) { - k_sem_take(&tun_drv_sem, K_FOREVER); - - /* notify audio core on tuning command reception */ - audio_core_notify_tuning_cmd(); - } - - return 0; -} - -int tun_drv_packet_handler(void) -{ - int ret = 0; - uint32_t len; - uint32_t first_word; - - if (audio_core_is_tuning_reply_ready() == false) { - return ret; - } - - first_word = *((uint32_t *)command_buffer.buffer); - len = (first_word >> 16) << 2; - - ret = usb_transport_send_reply(command_buffer.buffer, len); - if (ret) { - LOG_ERR("usb_transport_send_reply error %d", ret); - } - return ret; -} - -static void tun_drv_process_command(uint8_t *data, uint32_t len) -{ - uint32_t first_word; - - if (command_buffer.len == 0) { - /* extract command length */ - first_word = *((uint32_t *)data); - command_buffer.len = (first_word >> 16) << 2; - - /* ensure total length does not exceed max */ - if (command_buffer.len > TUN_DRV_CMD_MAX_BYTES) { - command_buffer.len = TUN_DRV_CMD_MAX_BYTES; - } - } - - if ((command_buffer.index + len) >= command_buffer.len) { - len = command_buffer.len - command_buffer.index; - } - - if (len) { - /* copy the received data into the tuning packet buffer */ - memcpy(&command_buffer.buffer[command_buffer.index], data, len); - command_buffer.index += len; - } - - if (command_buffer.index == command_buffer.len) { - /* reset index and length */ - command_buffer.index = command_buffer.len = 0; - /* notify tuning driver thread */ - k_sem_give(&tun_drv_sem); - } -} diff --git a/samples/boards/intel_s1000_crb/audio/src/usb_transport.c b/samples/boards/intel_s1000_crb/audio/src/usb_transport.c deleted file mode 100644 index af40f0a4c27d1..0000000000000 --- a/samples/boards/intel_s1000_crb/audio/src/usb_transport.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (c) 2019 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define LOG_LEVEL LOG_LEVEL_INF -#include -LOG_MODULE_REGISTER(usb_transport); - -#include - -#include -#include - -#include "usb_transport.h" - -/* callback function list */ -static int usb_transport_set_report(const struct device *dev, - struct usb_setup_packet *setup, - int32_t *len, uint8_t **data); -static void usb_transport_host_ready(const struct device *dev); - -static const struct hid_ops usb_transport_callbacks = { - .set_report = usb_transport_set_report, - .int_in_ready = usb_transport_host_ready, -}; - -/* create an HID report descriptor with input and output reports */ -static const uint8_t usb_transport_hid_report_desc[] = { - /* Usage page: vendor defined */ - HID_ITEM(HID_ITEM_TAG_USAGE_PAGE, HID_ITEM_TYPE_GLOBAL, 2), 0x00, 0xFF, - - /* Usage: vendor specific */ - HID_USAGE(0x01), - /* Collection: Application Collection */ - HID_COLLECTION(HID_COLLECTION_APPLICATION), - /* Logical Minimum: 0 */ - HID_LOGICAL_MIN8(0x00), - /* Logical Maximum: 255 */ - HID_LOGICAL_MAX8(0xFF), - /* Report Size: 8 bits */ - HID_REPORT_SIZE(8), - /* Report Count (in bytes) */ - HID_REPORT_COUNT(USB_TPORT_HID_REPORT_COUNT - 1), - - /* Report ID: 1 */ - HID_REPORT_ID(USB_TPORT_HID_REPORT_ID), - /* Vendor Usage 2 */ - HID_USAGE(0x02), - /* Input: Data, Variable, Absolute & Buffered bytes*/ - HID_INPUT(0x86), - - /* Report ID: 1 */ - HID_REPORT_ID(USB_TPORT_HID_REPORT_ID), - /* Vendor Usage 2 */ - HID_USAGE(0x02), - /* Output: Data, Variable, Absolute & Buffered bytes*/ - HID_OUTPUT(0x86), - - /* End collection */ - HID_END_COLLECTION, -}; - -static usb_transport_receive_callback_t receive_data_cb; - -static const struct device *hid_device; - -int usb_transport_init(usb_transport_receive_callback_t callback) -{ - int ret; - - hid_device = device_get_binding("HID_0"); - - if (hid_device == NULL) { - LOG_ERR("USB HID Device not found"); - return -ENODEV; - } - - /* register a HID device and the callback functions */ - usb_hid_register_device(hid_device, usb_transport_hid_report_desc, - sizeof(usb_transport_hid_report_desc), - &usb_transport_callbacks); - - receive_data_cb = callback; - - ret = usb_enable(NULL); - if (ret != 0) { - LOG_ERR("Failed to enable USB"); - return -EIO; - } - - /* initialize USB interface and HID class */ - return usb_hid_init(hid_device); -} - -int usb_transport_send_reply(uint8_t *data, uint32_t len) -{ - int ret = 0; - uint32_t written = 0; - union usb_hid_report_hdr *header; - - /* roll back buffer to point to header */ - data = data - sizeof(union usb_hid_report_hdr); - header = (union usb_hid_report_hdr *)data; - - /* send reply in one or more HID reports */ - while (len) { - /* populate header */ - header->byte.report_id = USB_TPORT_HID_REPORT_ID; - header->byte.unused[0] = header->byte.unused[1] = 0; - if (len < USB_TPORT_HID_REPORT_DATA_LEN) { - header->byte.byte_count = len; - len = 0; - } else { - header->byte.byte_count = USB_TPORT_HID_REPORT_DATA_LEN; - len -= USB_TPORT_HID_REPORT_DATA_LEN; - } - - ret = hid_int_ep_write(hid_device, (uint8_t *)header, - USB_TPORT_HID_REPORT_COUNT, &written); - - if (ret) { - LOG_DBG("usb_write failed with error %d", ret); - break; - } - - if (written != USB_TPORT_HID_REPORT_COUNT) { - /* usb_write is expected to send all data */ - LOG_ERR("usb_write: requested %u sent %u", - USB_TPORT_HID_REPORT_COUNT, written); - ret = -EIO; - break; - } - - /* move pointer to fill next header */ - header = (union usb_hid_report_hdr *)((uint8_t *)header + - USB_TPORT_HID_REPORT_DATA_LEN); - } - - return ret; -} - -static int usb_transport_set_report(const struct device *dev, - struct usb_setup_packet *setup, - int32_t *len, uint8_t **data) -{ - uint8_t *buffer; - int32_t size; - - /* strip the HID header */ - buffer = *data + sizeof(union usb_hid_report_hdr); - size = *len - sizeof(union usb_hid_report_hdr); - - receive_data_cb(buffer, size); - return 0; -} - -static void usb_transport_host_ready(const struct device *dev) -{ - LOG_DBG("usb_transport_host_ready"); -} diff --git a/samples/boards/intel_s1000_crb/audio/src/usb_transport.h b/samples/boards/intel_s1000_crb/audio/src/usb_transport.h deleted file mode 100644 index e4614b9ca560b..0000000000000 --- a/samples/boards/intel_s1000_crb/audio/src/usb_transport.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2019 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef TUNING_USB_TRANSPORT_H -#define TUNING_USB_TRANSPORT_H - -#define USB_TPORT_HID_REPORT_ID (1) -#define USB_TPORT_HID_REPORT_COUNT (56) -#define USB_TPORT_HID_REPORT_DATA_LEN \ - (USB_TPORT_HID_REPORT_COUNT - sizeof(union usb_hid_report_hdr)) - -/* 4 byte header in every HID report */ -union usb_hid_report_hdr { - struct { - uint8_t report_id; - uint8_t unused[2]; - uint8_t byte_count; - } __packed byte; - uint32_t word; -}; - -typedef void (*usb_transport_receive_callback_t)(uint8_t *data, uint32_t len); - -int usb_transport_init(usb_transport_receive_callback_t callback); -int usb_transport_send_reply(uint8_t *data, uint32_t len); - -#endif /* TUNING_USB_TRANSPORT_H */ diff --git a/samples/boards/intel_s1000_crb/dmic/CMakeLists.txt b/samples/boards/intel_s1000_crb/dmic/CMakeLists.txt deleted file mode 100644 index d94afa520babb..0000000000000 --- a/samples/boards/intel_s1000_crb/dmic/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(BOARD intel_s1000_crb) -cmake_minimum_required(VERSION 3.20.0) -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(intel_s1000_crb_dmic) - -target_sources(app PRIVATE src/dmic_sample.c) diff --git a/samples/boards/intel_s1000_crb/dmic/README.rst b/samples/boards/intel_s1000_crb/dmic/README.rst deleted file mode 100644 index cd042d58a3ec0..0000000000000 --- a/samples/boards/intel_s1000_crb/dmic/README.rst +++ /dev/null @@ -1,44 +0,0 @@ -.. _dmic_app-sample: - -Intel® S1000 Digital Microphone Sample Application -################################################## - -Overview -******** - -This sample application uses a digital microphone driver to receive interleaved -audio samples from a microphone array. - -This app configures the digital microphone driver, starts the driver, -receives a number of frames and then stops the driver. This process is -repeated a few times. - -Requirements -************ - -This application uses an Intel® S1000 Customer Reference Board (CRB) -with a circular 8 microphone array - -Building and Running -******************** - -.. zephyr-app-commands:: - :zephyr-app: samples/boards/intel_s1000_crb/dmic - :board: - :goals: build - :compact: - -Sample Output -============= - -Console output --------------- - -.. code-block:: console - - [00:00:00.348,954] dmic_sample.dmic_sample_app: Starting DMIC sample app ... - [00:00:00.510,004] dmic_sample.dmic_sample_app: Iteration 1/4 complete, 100 audio frames received. - [00:00:00.670,004] dmic_sample.dmic_sample_app: Iteration 2/4 complete, 100 audio frames received. - [00:00:00.830,004] dmic_sample.dmic_sample_app: Iteration 3/4 complete, 100 audio frames received. - [00:00:00.990,004] dmic_sample.dmic_sample_app: Iteration 4/4 complete, 100 audio frames received. - [00:00:00.990,005] dmic_sample.dmic_sample_app: Exiting DMIC sample app ... diff --git a/samples/boards/intel_s1000_crb/dmic/prj.conf b/samples/boards/intel_s1000_crb/dmic/prj.conf deleted file mode 100644 index 71cc3677527a1..0000000000000 --- a/samples/boards/intel_s1000_crb/dmic/prj.conf +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_LOG=y - -CONFIG_DMA=y - -CONFIG_USB_DEVICE_STACK=n -CONFIG_I2C=y -CONFIG_AUDIO=y diff --git a/samples/boards/intel_s1000_crb/dmic/sample.yaml b/samples/boards/intel_s1000_crb/dmic/sample.yaml deleted file mode 100644 index 0691852ea5e74..0000000000000 --- a/samples/boards/intel_s1000_crb/dmic/sample.yaml +++ /dev/null @@ -1,6 +0,0 @@ -sample: - name: DMIC Audio Sample -tests: - sample.board.intel_s1000_crb.dmic: - platform_allow: intel_s1000_crb - tags: dmic diff --git a/samples/boards/intel_s1000_crb/dmic/src/dmic_sample.c b/samples/boards/intel_s1000_crb/dmic/src/dmic_sample.c deleted file mode 100644 index 2a4faecf031eb..0000000000000 --- a/samples/boards/intel_s1000_crb/dmic/src/dmic_sample.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2019 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -#define LOG_LEVEL LOG_LEVEL_INF -#include -LOG_MODULE_REGISTER(dmic_sample); - -#define AUDIO_SAMPLE_FREQ 48000 -#define AUDIO_SAMPLE_WIDTH 32 -#define SAMPLES_PER_FRAME (64) - -#define NUM_MIC_CHANNELS 8 -#define MIC_FRAME_SAMPLES (SAMPLES_PER_FRAME * NUM_MIC_CHANNELS) -#define MIC_FRAME_BYTES (MIC_FRAME_SAMPLES * AUDIO_SAMPLE_WIDTH / 8) - -#define DMIC_DEV_NAME "PDM" -#define MIC_IN_BUF_COUNT 2 - -#define FRAMES_PER_ITERATION 100 -#define NUM_ITERATIONS 4 -#define DELAY_BTW_ITERATIONS K_MSEC(20) - -static struct k_mem_slab dmic_mem_slab; -__attribute__((section(".dma_buffers"))) -static char audio_buffers[MIC_FRAME_BYTES][MIC_IN_BUF_COUNT]; -static const struct device *dmic_device; - -static void dmic_init(void) -{ - int ret; - struct pcm_stream_cfg stream = { - .pcm_rate = AUDIO_SAMPLE_FREQ, - .pcm_width = AUDIO_SAMPLE_WIDTH, - .block_size = MIC_FRAME_BYTES, - .mem_slab = &dmic_mem_slab, - }; - struct dmic_cfg cfg = { - .io = { - .min_pdm_clk_freq = 1024000, - .max_pdm_clk_freq = 4800000, - .min_pdm_clk_dc = 48, - .max_pdm_clk_dc = 52, - .pdm_clk_pol = 0, - .pdm_data_pol = 0, - }, - .streams = &stream, - .channel = { - .req_chan_map_lo = - dmic_build_channel_map(0, 0, PDM_CHAN_RIGHT) | - dmic_build_channel_map(1, 0, PDM_CHAN_LEFT) | - dmic_build_channel_map(2, 2, PDM_CHAN_RIGHT) | - dmic_build_channel_map(3, 2, PDM_CHAN_LEFT) | - dmic_build_channel_map(4, 1, PDM_CHAN_RIGHT) | - dmic_build_channel_map(5, 1, PDM_CHAN_LEFT) | - dmic_build_channel_map(6, 3, PDM_CHAN_RIGHT) | - dmic_build_channel_map(7, 3, PDM_CHAN_LEFT), - .req_num_chan = NUM_MIC_CHANNELS, - .req_num_streams = 1, - }, - }; - - k_mem_slab_init(&dmic_mem_slab, audio_buffers, MIC_FRAME_BYTES, - MIC_IN_BUF_COUNT); - dmic_device = device_get_binding(DMIC_DEV_NAME); - if (!dmic_device) { - LOG_ERR("unable to find device %s", DMIC_DEV_NAME); - return; - } - - ret = dmic_configure(dmic_device, &cfg); - if (ret != 0) { - LOG_ERR("dmic_configure failed with %d error", ret); - } -} - -static void dmic_start(void) -{ - int ret; - - LOG_DBG("starting dmic"); - ret = dmic_trigger(dmic_device, DMIC_TRIGGER_START); - if (ret) { - LOG_ERR("dmic_trigger failed with code %d", ret); - } -} - -static void dmic_receive(void) -{ - int frame_counter = 0; - int32_t *mic_in_buf; - size_t size; - int ret; - - while (frame_counter++ < FRAMES_PER_ITERATION) { - ret = dmic_read(dmic_device, 0, (void **)&mic_in_buf, &size, - SYS_FOREVER_MS); - if (ret) { - LOG_ERR("dmic_read failed %d", ret); - } else { - LOG_DBG("dmic_read buffer %p size %u frame %d", - mic_in_buf, size, frame_counter); - k_mem_slab_free(&dmic_mem_slab, (void **)&mic_in_buf); - } - } -} - -static void dmic_stop(void) -{ - int ret; - - ret = dmic_trigger(dmic_device, DMIC_TRIGGER_STOP); - if (ret) { - LOG_ERR("dmic_trigger failed with code %d", ret); - } else { - LOG_DBG("dmic stopped"); - } -} - -static void dmic_sample_app(void *p1, void *p2, void *p3) -{ - int loop_count = 0; - - dmic_init(); - - LOG_INF("Starting DMIC sample app ..."); - while (loop_count++ < NUM_ITERATIONS) { - dmic_start(); - dmic_receive(); - dmic_stop(); - k_sleep(DELAY_BTW_ITERATIONS); - LOG_INF("Iteration %d/%d complete, %d audio frames received.", - loop_count, NUM_ITERATIONS, - FRAMES_PER_ITERATION); - } - LOG_INF("Exiting DMIC sample app ..."); -} - -K_THREAD_DEFINE(dmic_sample, 1024, dmic_sample_app, NULL, NULL, NULL, 10, 0, - 0); diff --git a/samples/boards/intel_s1000_crb/i2s/CMakeLists.txt b/samples/boards/intel_s1000_crb/i2s/CMakeLists.txt deleted file mode 100644 index 40bda102d6c88..0000000000000 --- a/samples/boards/intel_s1000_crb/i2s/CMakeLists.txt +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(BOARD intel_s1000_crb) -cmake_minimum_required(VERSION 3.20.0) -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(i2s) - -target_sources(app PRIVATE src/i2s_sample.c) - -if (AUDIO_PLAY_FROM_HOST) -add_compile_definitions(AUDIO_PLAY_FROM_HOST) -else () -target_link_libraries(app PUBLIC -lm) -target_link_libraries(app PUBLIC -lc) -target_link_libraries(app PUBLIC -Wl,-u,__extendsfdf2) -target_link_libraries(app PUBLIC -Wl,-u,__truncdfsf2) -target_link_libraries(app PUBLIC -Wl,-u,__divsf3) -target_link_libraries(app PUBLIC -Wl,-u,__divdf3) -target_link_libraries(app PUBLIC -Wl,-u,__adddf3) -target_link_libraries(app PUBLIC -Wl,-u,__subdf3) -target_link_libraries(app PUBLIC -Wl,-u,__ieee754_sqrtf) -target_link_libraries(app PUBLIC -Wl,-u,__ieee754_remainderf) -target_link_libraries(app PUBLIC -Wl,-u,__nedf2) -endif () diff --git a/samples/boards/intel_s1000_crb/i2s/README.rst b/samples/boards/intel_s1000_crb/i2s/README.rst deleted file mode 100644 index df6ce277a8ce1..0000000000000 --- a/samples/boards/intel_s1000_crb/i2s/README.rst +++ /dev/null @@ -1,138 +0,0 @@ -.. _i2s_app-sample: - -Intel® S1000 I2S Audio Sample Application -######################################### - -Overview -******** - -This sample application demonstrates audio playback on an Intel® S1000 CRB. -The application uses the following drivers - -- I2S driver -- Codec driver - -Two instances of the I2S driver are used. - -- I2S_1 is used as the output interface to play audio to the onboard codec. -- I2S_2 is used as the input interface to receive audio from a connected host. - -Intel® S1000 is the master on both I2S interfaces. -The host is a slave on the I2S and is expected to send a stereo audio at a -sampling frequency of 48KHz, 32 bits per sample. - -The app can be built in one of two modes and the mode selection is done by -providing a command line flag to ``west build`` or ``cmake``. - -1. **Audio Playback from Host** - - In this mode, the audio is played from the host. For example, on Linux hosts, - the ALSA ``aplay`` utility may be used to send Audio over the I2S bus to - S1000. - The app receives the audio from the host and forwards it to over another I2S - interface to the codec to play it out on the audio jack. - A copy of the same audio is also looped back to the host. - - This mode is chosen when ``-DAUDIO_PLAY_FROM_HOST=Y`` is specified in the - ``west build`` or ``cmake`` command. - - In this mode, the app forwards the audio forever, and does not exit. - After the app starts, one may use the ALSA aplay command on a Linux host - connected to S1000 over the I2S bus. - - ``aplay -f S32_LE -r 48000 -c 2 -D `` - -#. **Tone playback from S1000** - - In this mode, a sequence of tones is generated by the app and played out over - the I2S bus connected to the codec. - - This mode is chosen when ``-DAUDIO_PLAY_FROM_HOST=N`` is specified in the - ``west build`` or ``cmake`` command. - - In this mode, the app exits after the tone sequence is played. - For the duration of tone playback, the app uses the I2S interface connected - to the host for generating audio frame timing. The audio frames thus received - are looped back on the same I2S interface. - - If a host is connected on this I2S, it may still play audio and record the - looped back audio. However, only the audio tones generated within the app - will be sent to the codec. - -Requirements -************ - -This application uses an Intel® S1000 Customer Reference Board (CRB) -with a circular 8 microphone array board. -The Microphone array board contains a TI TLV320DAC3101 DAC for line-level -Audio output. - -Cable Rework -============ - -A rework of the host to CRB cable is required for playing audio from host. -Pin 12 needs to be wired to Pin 29 on the 40-pin connector of the cable. -This rework is not needed for playing tones generated by the app on S1000. - -.. image:: ./cable_rework.png - :width: 442px - :alt: Cable rework to play audio from host - -Building and Running -******************** - -Audio Playback from a Host -========================== - -.. zephyr-app-commands:: - :zephyr-app: samples/boards/intel_s1000_crb/i2s - :board: - :goals: build - :gen-args: -DAUDIO_PLAY_FROM_HOST=Y - :compact: - -Tone Sequence Playback -====================== - -.. zephyr-app-commands:: - :zephyr-app: samples/boards/intel_s1000_crb/i2s - :board: - :goals: build - :gen-args: -DAUDIO_PLAY_FROM_HOST=N - :compact: - -Sample Output -============= - -Console output (Audio Playback from Host) ------------------------------------------ - -.. code-block:: console - - [00:00:00.344,026] i2s_sample: Starting I2S audio sample app in host playback mode... - [00:00:00.346,481] i2s_sample: Play audio from the host over I2S using - [00:00:00.346,481] i2s_sample: aplay -f S32_LE -r 48000 -c 2 -D - -Console output (Tone Playback from S1000) ------------------------------------------ - -.. code-block:: console - - [00:00:00.344,028] i2s_sample: Starting I2S audio sample app in tone playback mode... - [00:00:00.347,860] i2s_sample: Tone 1046 Hz - [00:00:01.355,860] i2s_sample: Tone 1174 Hz - [00:00:02.363,860] i2s_sample: Tone 1318 Hz - [00:00:03.371,860] i2s_sample: Tone 1396 Hz - [00:00:04.379,860] i2s_sample: Tone 1567 Hz - [00:00:05.387,860] i2s_sample: Tone 1759 Hz - [00:00:06.395,860] i2s_sample: Tone 1864 Hz - [00:00:07.403,857] i2s_sample: Tone 2093 Hz - [00:00:08.411,859] i2s_sample: Tone 2093 Hz - [00:00:09.419,860] i2s_sample: Tone 1864 Hz - [00:00:10.427,860] i2s_sample: Tone 1759 Hz - [00:00:00.698,442] i2s_sample: Tone 1567 Hz - [00:00:01.706,442] i2s_sample: Tone 1396 Hz - [00:00:02.714,442] i2s_sample: Tone 1318 Hz - [00:00:03.722,442] i2s_sample: Tone 1174 Hz - [00:00:04.730,439] i2s_sample: Tone 1046 Hz - [00:00:05.737,095] i2s_sample: Exiting I2S audio sample app ... diff --git a/samples/boards/intel_s1000_crb/i2s/cable_rework.png b/samples/boards/intel_s1000_crb/i2s/cable_rework.png deleted file mode 100644 index 61e8d051c651dcb521aa2c968e9de9ffba28b949..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 7372 zcmeHsWmH>hw{E&AQlz*AcS@1sP$Z@J#tRfH1PD+d6iUzn356C27PPn&cW2{LECeeq zEl`S7ptw6{vF|wdyT8uQJMNF0k&&^oveta3JoBB;lNGM7t4>A?CI*2(WSSZ(&p@C% z2;lgVhyeI>UKgPSftV9CRg{c;Gqx6yo<=`133qog?Ht73u*4H_$AV2chzghzC#jtE zY>c09%sj_6bhzaFU2LhxgYbSedR*?S>+k(gsHwI8gSGkZmNHx<`rgzNQC5q4<`fU{ zwS%cNxY27~ya}nA4%^qF+HI-YVm_`8h#m0&$gjgG>Yvy93vAL**KOoB62$pGzn&>g z_=EO%O_G-W`u_ggDm$m;rM7wF7QG)i=QnLX^0#O-HdIMhg;mj*TPFTEPc+ zve9RcBx1_G#E*tleezr<<}%ZNClgGxe+ zSHH+m_IF+h8%3BOA=Li1m1+bSGA(2n)UA>sr>;w|$-_}@3xb3$%#oGIE~w*ghk z(N46y8r@JpYml<7z2FZ#NU#1l2@Ye*IC<=Q^%QZ1luV2Y%4JNbMB1JC}#G5}~Up51N^AHTMHq921TL!;CUB{`$=Jy|+ zep69#r@SphvYW!UrC398U)wos|i+tS4eh+3jK9h6X86`@`MyJ2Yl_&Ht8sKo->m{dJCD#{YhFL)rbdL@_zRGh}#%WCs0p?wq+PWAZ!(7mUrMx9vb9Ui(u^FfCZVnw15p8f72mID|j9 zqrUrgwUyGR=8Zz7ed&3`h}-ZYq?<{o=+wn|42}wDn`yVQYq_givsVatG4QNm{ZSFxr}ou z641v6S$o{9)_xm*>PpuH(;}%iCmt-8FU69qWX@NDTH)I#Dt=wl*E~hT;MI zIEE)mp>Deei>%bTjp^g7aj#nzqb5xf#y2#usrSV<<^_x0>Z}j;NbSroZ*McpVbUUA z#MPc3eO2Wo?qb(tr}gp%yub$u;tsxtpXmw?pG39jBuzt3Q|%`g-a&VcQ}hD|g3q<+ z+Qu`2^)d&FU+FT+!=dKC9g3+L@4k~)l7EpN{q-k}o#~~opAGq7#0ywyvi%Y4i-dHN zj>qbH)yc=cxcBE;&)eL;MJUs|^gL}ZFDBO_xv;Hys6xX-@a8YyWuvdw=$!|zVup@3 zgGt$lBVO=7MC8m*0%j9!a>BvQ zccAvX#@kh7=JQtHdfCserTd@j(+&2LSW@XAqZ8pPQA)zqK-wL>cy0bZ2W4IR#eD1O z%2+_jw>FUg$#zaRtS;*cg}s{Tsyi$Qag~>ElwKh-<&3!h?uB(L(_i97Qo}wQ^6@!| z$yUKH*ZskUgjEHEBCX}%RWdV9;_qDN!Org7IUOUxq>*e|B>gw>5$1rU$ug0=mFI+F zg4bO`!X(#jR8rZvCyilY9OI_Dd>Z=3Y=w7-w6Ca_9c+`PW5^CzWLkfUNr`N9Cm!CZ zf1FT#=1cImRT?^4y>4s;eMuugN!HI!Zv?;+r2m}z+rm~YC;d0%cVh1k4KSrFLIo@8 zQr&`_wF1rJ;yUrM@Z4T@`l(cJaS#!5^|eh0q5rm%`W7-9_G9?d(f(p|3I7`>D%Q#o z?6}tROmz)z0)pnZ!FQzPWoAz+d*ct8~`GVBTfYAFUFK zHGBBi<3-j}czUL_8@C{CmrNH*s%u8t(FAw);{{Unx)7KX@?6qQt}*wRVjRd)zqp?} zf3J<$fAATo^_xjdzsn{#St{hH~gT%64w%m*fb zLdwJDvI&*j`r+M!slqvKC=9R6r2Rpz@bKqtHZiZbAl+Fx)++*OppPx+yzYP+GH?ut zvo%lu{aA`XZ}()Y9%gBKRbgiHqqEqO$c#wfa?LG5U=y|gWuRA09cfy@&-QvPyg{F) zJeOj57UHzFjlp;2Ya5(@QaoBiPBVIdC{e=WY4(YDBg-tsmHPR>d<_tsWU zKOQfiSN&S`tz_sdf97KN`DpyElh60fgV1`E{Bs2DPj1N6CBi-*$*2{*J5T=6)0+=v zwD9icnw=T|Yt6;i8({A$PT65V+`XaX=^y`*kft?XDCDbyy+bPM-r zqyGZr8NO4I^)05B(-vvoXN#%||$l+EG{lZ;C09Pr` z@wy--seZH+8RpPxt+%&)^>E|}Li%#bbXbq$1tm6J zZ#Ls}RU@#NrY=46h$RTh6MRFAPew}meWfq*_tq9ZC^0F?78}LrctX%%V8~_KzvT_D zTt2zj8{o_SSX89$5&ga6@aV{?bQ#h79eAHyj89AicXTL@NG2ku&6U5*)@*83SHTvO z$ImHS+7UO?hvGvU>IPOKbjTmXNdY4f4-)FezRrY1ccSn}k|2@LR~0?2{i7<2qhqTU zS`g(ERV~N|$*Dt+e6Ws=&hI~eCIg}b;EoDvwx$Kf1@1F-jHD|UqSwfFpJIJ zOuS=l3ffufWD`y%xj5cpqRJh7#W@{o&nPJ=SzJ=WcxhfQd7tI+-J;3xo-p#Bbx-Hg zy`SlBxkW{Ux0mn7M5KXPSXk!johH9mncNS+EaEr;R4tHxH}YsEi@m0hjZ>C!hS}k3UHS*w2u?KJ?q&Byn5q@M_&_XM4Wl0xR3N z(#PbrwpthhAzArvN$Ok~%>W*S&yBv8yw9dc+PM^iM|j_QsRNmYF|dzr_djud3A?7Wsd#dVFw}*wS}nbweY}C+pm`TdzMn8 z{F6uSfZ77FL2{iZOqYkLK4aU}YUMf1{rzl#Hm1*`0DD)(a~{iO78~)!ox%INc`}Z zmJU$r3wcCXPY^vcfYN6Pd1Cz*#j#&StDvAT*MXGV*x1lFF_HF_V$mUE-%U0!FbLY* zbn)~GQM^-9sb*oplohbAX<9MUwIn<>qoJ#-_Uu`{1=R*TYQe-yGDG(lKhhY2iMuH6 zz~YcB&7p`JA-W-=Y%r3v3mo$yknrX>p}=>uwb|5NolK-j?^@% z#!7eWk+og!52c+mme;s^5nKE5!)c?amJL9a!3i~J!ByI|bxVqykB{6+0IZ9QPD-NF z>36ISo&D1{Q(=*}U4kGjDJcQcRPMgL&|G}Mm}b$n^gT>`uHZvS!>1}DAt9l6(1Wvp z;?mOYqHI(I0F?XJs&^sO3l8<*)YMb}y40+Jm+pdAZ4B${>jtycrh>T9(SCSUd#F~j zFbB{G8{jAG0nTu^`;S4|{QP{!(mNpOh1YmifmdFhUS3_Ujp~+MFMyiIWo0RrSB=jQ z&6)^Z5pBVnz=K=LClJ7c4U_qanqu!{K2sJzmNcW5_&$7EWwgJXf@~3@Na_f@$pN~ON@tE ziPEH%o+eNOeWhezK>7Al)k|7h+8#vljbFZ-kzYF#UiUXrIs^V0_&ZNsfkJ;h&j*|L zxtuTCl|?~({;Du}%&tl0@HvC=*kgKnTE=^mp;kzY^^_`9yWNIthM^?X3U<1_fV#A< zBq7;v|9z}++B8q9p3TUX^+$aq=OivIEkaf`A>_|X&gnE-NL`e{Jnoom- z9%UBR)KCJ=h8r0P8F5e!41|2nhQzSQd4KHaUvovI(6139~>_)0`L*jXTQ~w zrmI$oG#{0|lNYY4;b~#TpJlL=You2fF{=S+u|jkSAUi&G2tArbI^{485igQ@MLZyo zHDCthg*8Ae^+Yz6UU?9IlX2_IA(5JrDgu1c8&YSuo!Ql`G$_Y~xavv&9~@j?Pvr*MUH_dWzhN@6XEJY+(2*cfW zYCvpt%}<*td=LvsxAWoR>xo?d!fG^pjJ0F#luwHWRE(+QWQY()q$g7jTTSu5%m^#F z8dxXJuvRNLbar-@H{&J4Tsyg**p1(8V72`jj4ivpDi51~nI3DK9U{Ht)TPcAsJP}a zzzezFR+HXt8IQz2%i<8X&SmUxL?qNKkGzm+<272?_!N3}zvp<>4+c`Ryd`>JPg1jZ&Nd4+`pvUJ~HN|R>}_JG69dWc{Q zG2q4f($0SryT_?Vd=Fw?j*lxG*1I~lkPj6$yAN@bUypquk6ANRz*K!HKkerVvj0mO zP!
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- -#define AUDIO_SAMPLE_FREQ (48000) -#define AUDIO_SAMPLES_PER_CH_PER_FRAME (64) -#define AUDIO_NUM_CHANNELS (2) -#define AUDIO_SAMPLES_PER_FRAME \ - (AUDIO_SAMPLES_PER_CH_PER_FRAME * AUDIO_NUM_CHANNELS) -#define AUDIO_SAMPLE_BYTES (4) -#define AUDIO_SAMPLE_BIT_WIDTH (32) - -#define AUDIO_FRAME_BUF_BYTES \ - (AUDIO_SAMPLES_PER_FRAME * AUDIO_SAMPLE_BYTES) - -#define I2S_PLAYBACK_DEV "I2S_1" -#define I2S_HOST_DEV "I2S_2" - -#define I2S_PLAY_BUF_COUNT (6) -#define I2S_TX_PRELOAD_BUF_COUNT (2) - -#define BASE_TONE_FREQ_HZ 1046.502f /* Hz */ -#define FLOAT_VALUE_OF_2PI (2 * 3.1415926535897932384626433832795f) -#define BASE_TONE_FREQ_RAD (BASE_TONE_FREQ_HZ * FLOAT_VALUE_OF_2PI) -#define BASE_TONE_PHASE_DELTA (BASE_TONE_FREQ_RAD / AUDIO_SAMPLE_FREQ) - -#define SECONDS_PER_TONE (1) /* second(s) */ -#define TONES_TO_PLAY \ - {0, 2, 4, 5, 7, 9, 10, 12, 12, 10, 9, 7, 5, 4, 2, 0} - -#define AUDIO_FRAMES_PER_SECOND \ - (AUDIO_SAMPLE_FREQ / AUDIO_SAMPLES_PER_CH_PER_FRAME) -#define AUDIO_FRAMES_PER_TONE_DURATION \ - (SECONDS_PER_TONE * AUDIO_FRAMES_PER_SECOND) - -#define SIGNAL_AMPLITUDE_DBFS (-36) -#define SIGNAL_AMPLITUDE_BITS (31 + (SIGNAL_AMPLITUDE_DBFS / 6)) -#define SIGNAL_AMPLITUDE_SCALE (1 << SIGNAL_AMPLITUDE_BITS) - -#ifdef AUDIO_PLAY_FROM_HOST -#define APP_MODE_STRING "host playback" -#else -#define APP_MODE_STRING "tone playback" -#endif - -static struct k_mem_slab i2s_mem_slab; -__attribute__((section(".dma_buffers"))) -static char audio_buffers[AUDIO_FRAME_BUF_BYTES][I2S_PLAY_BUF_COUNT]; -static const struct device *spk_i2s_dev; -static const struct device *host_i2s_dev; -static const struct device *codec_device; - -#ifndef AUDIO_PLAY_FROM_HOST -static inline int audio_playback_buffer_fill(float phase_delta, int32_t *buffer, - int channels, int samples) -{ - int channel; - int32_t sample; - int32_t *wr_ptr; - int sample_index; - static float phase; - - wr_ptr = buffer; - sample_index = 0; - while ((sample_index < samples) && (phase_delta != 0.0f)) { - /* get sine(phase) and scale it */ - sample = (int32_t)(SIGNAL_AMPLITUDE_SCALE * sinf(phase)); - /* update phase for next sample */ - phase = fmodf(phase + phase_delta, FLOAT_VALUE_OF_2PI); - /* write same sample value to all channels */ - for (channel = 0; channel < channels; channel++) { - *wr_ptr++ = sample; - } - sample_index++; - } - - return sample_index; -} - -static float audio_playback_tone_get_next(void) -{ - static int index; - static int frame; - char tones[] = TONES_TO_PLAY; - - if (frame == 0) { - LOG_INF("Tone %u Hz", (unsigned int)(BASE_TONE_FREQ_HZ * - powf(2.0f, (float)tones[index]/12.0f))); - } - - if (++frame == AUDIO_FRAMES_PER_TONE_DURATION) { - frame = 0; - index++; - } - - if (index == ARRAY_SIZE(tones)) { - index = 0; - - /* all tones returned */ - return 0.0f; - } - - return (BASE_TONE_PHASE_DELTA * powf(2.0f, (float)tones[index]/12.0f)); -} -#endif - -static void i2s_audio_init(void) -{ - int ret; - struct i2s_config i2s_cfg; - struct audio_codec_cfg codec_cfg; - - k_mem_slab_init(&i2s_mem_slab, audio_buffers, AUDIO_FRAME_BUF_BYTES, - I2S_PLAY_BUF_COUNT); - - spk_i2s_dev = device_get_binding(I2S_PLAYBACK_DEV); - - if (!spk_i2s_dev) { - LOG_ERR("unable to find " I2S_PLAYBACK_DEV " device"); - return; - } - - host_i2s_dev = device_get_binding(I2S_HOST_DEV); - - if (!host_i2s_dev) { - LOG_ERR("unable to find " I2S_HOST_DEV " device"); - return; - } - - codec_device = device_get_binding(DT_LABEL(DT_INST(0, ti_tlv320dac))); - if (!codec_device) { - LOG_ERR("unable to find " DT_LABEL(DT_INST(0, ti_tlv320dac)) " device"); - return; - } - - /* configure i2s for audio playback */ - i2s_cfg.word_size = AUDIO_SAMPLE_BIT_WIDTH; - i2s_cfg.channels = AUDIO_NUM_CHANNELS; - i2s_cfg.format = I2S_FMT_DATA_FORMAT_I2S | I2S_FMT_CLK_NF_NB; - i2s_cfg.options = I2S_OPT_FRAME_CLK_MASTER | - I2S_OPT_BIT_CLK_MASTER; - i2s_cfg.frame_clk_freq = AUDIO_SAMPLE_FREQ; - i2s_cfg.block_size = AUDIO_FRAME_BUF_BYTES; - i2s_cfg.mem_slab = &i2s_mem_slab; - - /* make the transmit interface non-blocking */ - i2s_cfg.timeout = 0; - ret = i2s_configure(spk_i2s_dev, I2S_DIR_TX, &i2s_cfg); - if (ret != 0) { - LOG_ERR("dmic_configure failed with %d error", ret); - return; - } - - /* make the receive interface blocking */ - i2s_cfg.timeout = SYS_FOREVER_MS; - ret = i2s_configure(host_i2s_dev, I2S_DIR_RX, &i2s_cfg); - if (ret != 0) { - LOG_ERR("dmic_configure failed with %d error", ret); - return; - } - - /* configure codec */ - codec_cfg.dai_type = AUDIO_DAI_TYPE_I2S, - codec_cfg.dai_cfg.i2s = i2s_cfg; - codec_cfg.dai_cfg.i2s.options = I2S_OPT_FRAME_CLK_SLAVE | - I2S_OPT_BIT_CLK_SLAVE; - codec_cfg.dai_cfg.i2s.mem_slab = NULL; - codec_cfg.mclk_freq = soc_get_ref_clk_freq(); - - audio_codec_configure(codec_device, &codec_cfg); -} - -static void i2s_start_audio(void) -{ - int ret; - - LOG_DBG("Starting audio playback..."); - /* start codec output */ - audio_codec_start_output(codec_device); - - /* start i2s */ - ret = i2s_trigger(spk_i2s_dev, I2S_DIR_TX, I2S_TRIGGER_START); - if (ret) { - LOG_ERR("spk_i2s_dev TX start failed. code %d", ret); - } - - ret = i2s_trigger(host_i2s_dev, I2S_DIR_TX, I2S_TRIGGER_START); - if (ret) { - LOG_ERR("host_i2s_dev TX start failed. code %d", ret); - } - - ret = i2s_trigger(host_i2s_dev, I2S_DIR_RX, I2S_TRIGGER_START); - if (ret) { - LOG_ERR("host_i2s_dev RX start failed. code %d", ret); - } -} - -static void i2s_prepare_audio(const struct device *dev) -{ - int frame_counter = 0; - void *buffer; - int ret; - - LOG_DBG("Preloading silence..."); - while (frame_counter++ < I2S_TX_PRELOAD_BUF_COUNT) { - ret = k_mem_slab_alloc(&i2s_mem_slab, &buffer, K_NO_WAIT); - if (ret) { - LOG_ERR("buffer alloc failed %d", ret); - return; - } - - LOG_DBG("allocated buffer %p frame %d", - buffer, frame_counter); - - /* fill the buffer with zeros (silence) */ - memset(buffer, 0, AUDIO_FRAME_BUF_BYTES); - - ret = i2s_write(dev, buffer, AUDIO_FRAME_BUF_BYTES); - if (ret) { - LOG_ERR("i2s_write failed %d", ret); - k_mem_slab_free(&i2s_mem_slab, &buffer); - } - } -} - -static void i2s_play_audio(void) -{ - void *in_buf; - void *copy_buf; - size_t size; - int ret; - - while (true) { - /* read from host I2S interface */ - ret = i2s_read(host_i2s_dev, &in_buf, &size); - if (ret) { - LOG_ERR("host_i2s_dev i2s_read failed %d", ret); - return; - } - - /* make a copy of the audio to send back to the host */ - ret = k_mem_slab_alloc(&i2s_mem_slab, ©_buf, K_NO_WAIT); - if (ret) { - LOG_ERR("buffer alloc failed %d", ret); - k_mem_slab_free(&i2s_mem_slab, &in_buf); - return; - } - - memcpy(copy_buf, in_buf, AUDIO_FRAME_BUF_BYTES); - - /* loop the audio back to the host */ - ret = i2s_write(host_i2s_dev, copy_buf, AUDIO_FRAME_BUF_BYTES); - if (ret) { - k_mem_slab_free(&i2s_mem_slab, ©_buf); - LOG_ERR("host_i2s_dev i2s_write failed %d", ret); - return; - } - -#ifndef AUDIO_PLAY_FROM_HOST - /* fill buffer with audio samples */ - if (audio_playback_buffer_fill(audio_playback_tone_get_next(), - (int32_t *)in_buf, AUDIO_NUM_CHANNELS, - size) < size) { - /* break if all tones are exhausted */ - k_mem_slab_free(&i2s_mem_slab, &in_buf); - break; - } -#endif - ret = i2s_write(spk_i2s_dev, in_buf, AUDIO_FRAME_BUF_BYTES); - if (ret) { - k_mem_slab_free(&i2s_mem_slab, &in_buf); - LOG_ERR("spk_i2s_dev i2s_write failed %d", ret); - } - } -} - -#ifndef AUDIO_PLAY_FROM_HOST -static void i2s_stop_audio(void) -{ - int ret; - - ret = i2s_trigger(spk_i2s_dev, I2S_DIR_TX, I2S_TRIGGER_STOP); - if (ret) { - LOG_ERR("spk_i2s_dev stop failed with code %d", ret); - } - - ret = i2s_trigger(host_i2s_dev, I2S_DIR_RX, I2S_TRIGGER_STOP); - if (ret) { - LOG_ERR("host_i2s_dev stop failed with code %d", ret); - } - - LOG_DBG("Stopping audio playback..."); -} -#endif - -static void i2s_audio_sample_app(void *p1, void *p2, void *p3) -{ - i2s_audio_init(); - - LOG_INF("Starting I2S audio sample app in " APP_MODE_STRING " mode..."); - i2s_prepare_audio(spk_i2s_dev); - i2s_prepare_audio(host_i2s_dev); - i2s_start_audio(); -#ifdef AUDIO_PLAY_FROM_HOST - LOG_WRN("Play audio from the host over I2S using"); - LOG_WRN("aplay -f S32_LE -r 48000 -c 2 -D "); -#endif - i2s_play_audio(); -#ifndef AUDIO_PLAY_FROM_HOST - i2s_stop_audio(); - LOG_INF("Exiting I2S audio sample app ..."); - k_thread_suspend(k_current_get()); -#endif -} - -K_THREAD_DEFINE(i2s_sample, 1024, i2s_audio_sample_app, NULL, NULL, NULL, - 10, 0, 0); diff --git a/samples/boards/intel_s1000_crb/intel_s1000_crb.rst b/samples/boards/intel_s1000_crb/intel_s1000_crb.rst deleted file mode 100644 index da50ed621ac73..0000000000000 --- a/samples/boards/intel_s1000_crb/intel_s1000_crb.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _intel_s1000_crb-samples: - -Intel® S1000 Customer Reference Board Samples -############################################# - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* From 426b6fc247d3195a977b3505f68440d62b7b63f5 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 13 Jun 2022 14:25:25 -0400 Subject: [PATCH 2/8] tests: remove intel_s1000_crb tests Remove all tests specific to the intel_s1000_crb board. The board is no longer supported. Signed-off-by: Anas Nashif --- .../intel_s1000_crb/cache/CMakeLists.txt | 8 - tests/boards/intel_s1000_crb/cache/prj.conf | 2 - .../intel_s1000_crb/cache/src/cache_test.c | 101 ------- .../intel_s1000_crb/cache/testcase.yaml | 4 - .../intel_s1000_crb/main/CMakeLists.txt | 27 -- tests/boards/intel_s1000_crb/main/README.txt | 65 ----- tests/boards/intel_s1000_crb/main/prj.conf | 10 - .../intel_s1000_crb/main/src/dma_test.c | 276 ------------------ .../intel_s1000_crb/main/src/gpio_test.c | 140 --------- .../intel_s1000_crb/main/src/i2c_test.c | 176 ----------- .../intel_s1000_crb/main/src/i2s_test.c | 185 ------------ tests/boards/intel_s1000_crb/main/src/main.c | 27 -- .../intel_s1000_crb/main/src/spi_flash.c | 108 ------- .../intel_s1000_crb/main/src/test_hid.c | 93 ------ .../boards/intel_s1000_crb/main/testcase.yaml | 4 - 15 files changed, 1226 deletions(-) delete mode 100644 tests/boards/intel_s1000_crb/cache/CMakeLists.txt delete mode 100644 tests/boards/intel_s1000_crb/cache/prj.conf delete mode 100644 tests/boards/intel_s1000_crb/cache/src/cache_test.c delete mode 100644 tests/boards/intel_s1000_crb/cache/testcase.yaml delete mode 100644 tests/boards/intel_s1000_crb/main/CMakeLists.txt delete mode 100644 tests/boards/intel_s1000_crb/main/README.txt delete mode 100644 tests/boards/intel_s1000_crb/main/prj.conf delete mode 100644 tests/boards/intel_s1000_crb/main/src/dma_test.c delete mode 100644 tests/boards/intel_s1000_crb/main/src/gpio_test.c delete mode 100644 tests/boards/intel_s1000_crb/main/src/i2c_test.c delete mode 100644 tests/boards/intel_s1000_crb/main/src/i2s_test.c delete mode 100644 tests/boards/intel_s1000_crb/main/src/main.c delete mode 100644 tests/boards/intel_s1000_crb/main/src/spi_flash.c delete mode 100644 tests/boards/intel_s1000_crb/main/src/test_hid.c delete mode 100644 tests/boards/intel_s1000_crb/main/testcase.yaml diff --git a/tests/boards/intel_s1000_crb/cache/CMakeLists.txt b/tests/boards/intel_s1000_crb/cache/CMakeLists.txt deleted file mode 100644 index e14b80b09a6c7..0000000000000 --- a/tests/boards/intel_s1000_crb/cache/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(BOARD intel_s1000_crb) -cmake_minimum_required(VERSION 3.20.0) -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(intel_s1000_crb) - -target_sources(app PRIVATE src/cache_test.c) diff --git a/tests/boards/intel_s1000_crb/cache/prj.conf b/tests/boards/intel_s1000_crb/cache/prj.conf deleted file mode 100644 index 0bd88af20d791..0000000000000 --- a/tests/boards/intel_s1000_crb/cache/prj.conf +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_LOG=y -CONFIG_USB_DEVICE_STACK=n diff --git a/tests/boards/intel_s1000_crb/cache/src/cache_test.c b/tests/boards/intel_s1000_crb/cache/src/cache_test.c deleted file mode 100644 index e139560828f1e..0000000000000 --- a/tests/boards/intel_s1000_crb/cache/src/cache_test.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2019 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#define LOG_LEVEL CONFIG_LOG_DEFAULT_LEVEL -#include -LOG_MODULE_REGISTER(cache_test); - -#define LP_SRAM_BASE 0xBE800000 -#define LP_SRAM_BASE_UNCACHED 0x9E800000 - -#define CACHE_TEST_BUFFER_SIZE 256 - -struct test_buffer { - uint8_t flush[CACHE_TEST_BUFFER_SIZE]; - uint8_t invalidate[CACHE_TEST_BUFFER_SIZE]; -}; - -static struct test_buffer *cached_buffer = (struct test_buffer *)LP_SRAM_BASE; - -static struct test_buffer *mem_buffer = - (struct test_buffer *)LP_SRAM_BASE_UNCACHED; - -static void buffer_fill_sequence(uint8_t *buffer, bool inv_seq) -{ - int byte; - - for (byte = 0; byte < CACHE_TEST_BUFFER_SIZE; byte++) { - buffer[byte] = inv_seq ? ~byte : byte; - } -} - -static void cache_flush_test(void) -{ - LOG_INF("Filling main memory with an inverted byte sequence ..."); - buffer_fill_sequence(mem_buffer->flush, true); - - LOG_INF("Filling cacheable memory with a normal byte sequence ..."); - buffer_fill_sequence(cached_buffer->flush, false); - - LOG_INF("Comparing contents of cached memory vs main memory ..."); - if (memcmp(mem_buffer->flush, cached_buffer->flush, - CACHE_TEST_BUFFER_SIZE)) { - LOG_INF("Contents mismatch. This is expected"); - } else { - LOG_ERR("Contents match. Is Cache configured write-through?"); - } - - LOG_INF("Flushing cache to commit contents to main memory ..."); - z_xtensa_cache_flush(cached_buffer->flush, - CACHE_TEST_BUFFER_SIZE); - - LOG_INF("Comparing contents of cached memory vs main memory ..."); - if (memcmp(mem_buffer->flush, cached_buffer->flush, - CACHE_TEST_BUFFER_SIZE)) { - LOG_ERR("Contents mismatch. Cache flush test Failed"); - } else { - LOG_INF("Contents match. Cache flush test Passed"); - } -} - -static void cache_invalidation_test(void) -{ - LOG_INF("Filling main memory with an inverted byte sequence ..."); - buffer_fill_sequence(mem_buffer->invalidate, true); - - LOG_INF("Filling cacheable memory with a normal byte sequence ..."); - buffer_fill_sequence(cached_buffer->invalidate, false); - - LOG_INF("Comparing contents of cached memory vs main memory ..."); - if (memcmp(mem_buffer->invalidate, cached_buffer->invalidate, - CACHE_TEST_BUFFER_SIZE)) { - LOG_INF("Contents mismatch. This is expected"); - } else { - LOG_ERR("Contents match. This is unexpected"); - } - - LOG_INF("Invalidating cache to read contents from main memory ..."); - z_xtensa_cache_inv(cached_buffer->invalidate, - CACHE_TEST_BUFFER_SIZE); - - LOG_INF("Comparing contents of cached memory vs main memory ..."); - if (memcmp(mem_buffer->invalidate, cached_buffer->invalidate, - CACHE_TEST_BUFFER_SIZE)) { - LOG_ERR("Contents mismatch. Cache invalidation test Failed"); - } else { - LOG_INF("Contents match. Cache invalidation test Passed"); - } -} - -void main(void) -{ - LOG_INF("Data Cache write-back test for Intel S1000"); - cache_flush_test(); - LOG_INF("Data Cache invalidation test for Intel S1000"); - cache_invalidation_test(); -} diff --git a/tests/boards/intel_s1000_crb/cache/testcase.yaml b/tests/boards/intel_s1000_crb/cache/testcase.yaml deleted file mode 100644 index 99e827a09edaa..0000000000000 --- a/tests/boards/intel_s1000_crb/cache/testcase.yaml +++ /dev/null @@ -1,4 +0,0 @@ -tests: - boards.s1000_crb.cache: - platform_allow: intel_s1000_crb - tags: boards diff --git a/tests/boards/intel_s1000_crb/main/CMakeLists.txt b/tests/boards/intel_s1000_crb/main/CMakeLists.txt deleted file mode 100644 index 23d8f948a43fc..0000000000000 --- a/tests/boards/intel_s1000_crb/main/CMakeLists.txt +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(intel_s1000_crb) - -if(CONFIG_I2C) -target_sources(app PRIVATE src/i2c_test.c) -target_compile_definitions(app PRIVATE -DLED_LIGHT_PAT=1) -endif() -if(CONFIG_GPIO) -target_sources(app PRIVATE src/gpio_test.c) -endif() -if(CONFIG_DMA) -target_sources(app PRIVATE src/dma_test.c) -endif() -if(CONFIG_I2S) -target_sources(app PRIVATE src/i2s_test.c) -endif() -if(CONFIG_USB_DEVICE_STACK) -target_sources(app PRIVATE src/test_hid.c) -endif() -if(CONFIG_SPI) -target_sources(app PRIVATE src/spi_flash.c) -endif() - -target_sources(app PRIVATE src/main.c) diff --git a/tests/boards/intel_s1000_crb/main/README.txt b/tests/boards/intel_s1000_crb/main/README.txt deleted file mode 100644 index fb7b810d89b80..0000000000000 --- a/tests/boards/intel_s1000_crb/main/README.txt +++ /dev/null @@ -1,65 +0,0 @@ -Title: Intel S1000 CRB tests - -Description: - -This test illustrates the various features enabled on Intel S1000 CRB. - -Features exhibited in this test set -============================ - -GPIO toggling - - GPIO_23 configured as input - - GPIO_24 configured as output and interrupt capable - - GPIO_23 and GPIO_24 are shorted - - Upon toggling GPIO_23, GPIO_24 also changes state appropriately and - also calls its callback function if interrupt is configured - -I2C slave communication - - Intel S1000 CRB I2C configured as master, 7 bit mode, standard speed - - 2 LED matrices are configured as slaves - - The LED matrices are written over I2C to emit blue light and red - light alternately - - Read functionality verified by reading LED0 after every write and - dumping the result on to the console - -Interrupt handling - - All peripheral interrupts are enabled by default - - Each peripheral interrupt can be disabled by calling irq_disable(). - For e.g. GPIO IRQ can be disabled by calling "irq_disable(GPIO_DW_0_IRQ);" - -UART prints - - Displays the various prints dumped to the console by the above modules - ---------------------------------------------------------------------------- - -Building and Running Project: - -This project outputs to the console. It can be built and executed -on Intel S1000 CRB using the flyswatter2 as follows: - - make flash - ---------------------------------------------------------------------------- - -Troubleshooting: - -Problems caused by out-dated project information can be addressed by -issuing one of the following commands then rebuilding the project: - - make clean # discard results of previous builds - # but keep existing configuration info -or - make pristine # discard results of previous builds - # and restore pre-defined configuration info - ---------------------------------------------------------------------------- - -Sample Output: - -***** BOOTING ZEPHYR OS v1.9.99-intel_internal - BUILD: Oct 31 2017 14:48:57 ***** -Sample app running on: xtensa Intel S1000 CRB -Reading GPIO_24 = 0 -LED0 = 10 -GPIO_24 triggered -Reading GPIO_24 = 1 -LED0 = 41 diff --git a/tests/boards/intel_s1000_crb/main/prj.conf b/tests/boards/intel_s1000_crb/main/prj.conf deleted file mode 100644 index afbff4fcd37fb..0000000000000 --- a/tests/boards/intel_s1000_crb/main/prj.conf +++ /dev/null @@ -1,10 +0,0 @@ -CONFIG_LOG=y -CONFIG_USB_DRIVER_LOG_LEVEL_ERR=y -CONFIG_USB_DEVICE_LOG_LEVEL_ERR=y - -CONFIG_I2S=y -CONFIG_I2C=y -CONFIG_DMA=y -CONFIG_SPI=y -CONFIG_FLASH=y -CONFIG_FLASH_MAP=y diff --git a/tests/boards/intel_s1000_crb/main/src/dma_test.c b/tests/boards/intel_s1000_crb/main/src/dma_test.c deleted file mode 100644 index ae16cd08cdbe7..0000000000000 --- a/tests/boards/intel_s1000_crb/main/src/dma_test.c +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (c) 2019 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * - * @brief Sample app to illustrate dma transfer on Intel S1000 CRB. - * - * Intel S1000 CRB - Xtensa - * -------------------- - * - * The dma_cavs driver is being used. - * - * In this sample app, multi-block dma is tested in the following manner - * - Define 2 strings which will serve as 2 blocks of source data. - * - Define 2 empty buffers to receive the data from the DMA operation. - * - Set dma channel configuration including source/dest addr, burstlen etc. - * - Set direction memory-to-memory - * - Start transfer - * - * Expected Results - * - Data is transferred correctly from src to dest. The DMAed string should - * be printed on to the console. No error should be seen. - */ - -#include -#include - -#include -#include - -#include -#include - -/* size of stack area used by each thread */ -#define STACKSIZE 1024 - -/* scheduling priority used by each thread */ -#define PRIORITY 7 - -/* delay between greetings (in ms) */ -#define SLEEPTIME K_MSEC(500) - -/* max time to be waited for dma to complete (in ms) */ -#define WAITTIME K_MSEC(1000) - -#define MAX_TRANSFERS 4 - -/* This semaphore is used as a signal from the dma isr to the app - * to let it know the DMA is complete. The app should wait till - * this event comes indicating the completion of DMA. - */ -K_SEM_DEFINE(dma_sem, 0, 1); - -extern struct k_sem thread_sem; - -#define RX_BUFF_SIZE (48) - -struct transfers { - const char *source; - char *destination; - size_t size; -}; - -static const char tx_data[] = "It is harder to be kind than to be wise"; -static const char tx_data2[] = "India have a good cricket team"; -static const char tx_data3[] = "Virat: the best ever?"; -static const char tx_data4[] = "Phenomenon"; -static char rx_data[RX_BUFF_SIZE] = { 0 }; -static char rx_data2[RX_BUFF_SIZE] = { 0 }; -static char rx_data3[RX_BUFF_SIZE] = { 0 }; -static char rx_data4[RX_BUFF_SIZE] = { 0 }; - -static struct transfers transfer_blocks[MAX_TRANSFERS] = { - { - .source = tx_data, - .destination = rx_data, - .size = sizeof(tx_data), - }, - { - .source = tx_data2, - .destination = rx_data2, - .size = sizeof(tx_data2), - }, - { - .source = tx_data3, - .destination = rx_data3, - .size = sizeof(tx_data3), - }, - { - .source = tx_data4, - .destination = rx_data4, - .size = sizeof(tx_data4), - }, -}; -static const struct device *dma_device; -static uint32_t current_block_count, total_block_count; - -static void test_done(const struct device *dma_dev, void *arg, - uint32_t channel, int error_code) -{ - uint32_t src, dst; - size_t size; - - current_block_count++; - - if (error_code != 0) { - printk("DMA transfer met an error = 0x%x\n", error_code); - k_sem_give(&dma_sem); - } else if (current_block_count < total_block_count) { - src = (uint32_t)transfer_blocks[current_block_count].source; - dst = (uint32_t)transfer_blocks[current_block_count].destination; - size = transfer_blocks[current_block_count].size; - dma_reload(dma_dev, channel, src, dst, size); - dma_start(dma_dev, channel); - } else { - printk("DMA transfer done\n"); - k_sem_give(&dma_sem); - } -} - -static int test_task(uint32_t chan_id, uint32_t blen, uint32_t block_count) -{ - struct dma_config dma_cfg = {0}; - - struct dma_block_config dma_block_cfg = { - .block_size = sizeof(tx_data), - .source_address = (uint32_t)tx_data, - .dest_address = (uint32_t)rx_data, - }; - - if (block_count > ARRAY_SIZE(transfer_blocks)) { - printk("block_count %u is greater than %zu\n", block_count, - ARRAY_SIZE(transfer_blocks)); - return -1; - } - - dma_device = DEVICE_DT_GET(DT_NODELABEL(dma0)); - - if (!device_is_ready(dma_device)) { - printk("dma controller is not ready\n"); - return -1; - } - - dma_cfg.channel_direction = MEMORY_TO_MEMORY; - dma_cfg.source_data_size = 1U; - dma_cfg.dest_data_size = 1U; - dma_cfg.source_burst_length = blen; - dma_cfg.dest_burst_length = blen; - dma_cfg.dma_callback = test_done; - dma_cfg.complete_callback_en = 0U; - dma_cfg.error_callback_en = 1U; - dma_cfg.block_count = 1U; - dma_cfg.head_block = &dma_block_cfg; - - printk("Preparing DMA Controller: Chan_ID=%u, BURST_LEN=%u\n", - chan_id, blen); - - (void)memset(rx_data, 0, sizeof(rx_data)); - (void)memset(rx_data2, 0, sizeof(rx_data2)); - (void)memset(rx_data3, 0, sizeof(rx_data3)); - (void)memset(rx_data4, 0, sizeof(rx_data4)); - - /* - * dma_block_cfg4 is assigned to 0 by default. Hence if user_data is - * not assigned, it will be NULL implying there are no more blocks to - * transfer - */ - - if (dma_config(dma_device, chan_id, &dma_cfg)) { - printk("ERROR: configuring\n"); - return -1; - } - - printk("Starting the transfer\n"); - - current_block_count = 0U; - total_block_count = block_count; - - if (dma_start(dma_device, chan_id)) { - printk("ERROR: transfer\n"); - return -1; - } - - /* Wait a while for the dma to complete */ - if (k_sem_take(&dma_sem, WAITTIME)) { - printk("*** timed out waiting for dma to complete ***\n"); - } - - z_xtensa_cache_inv(rx_data, RX_BUFF_SIZE); - z_xtensa_cache_inv(rx_data2, RX_BUFF_SIZE); - z_xtensa_cache_inv(rx_data3, RX_BUFF_SIZE); - z_xtensa_cache_inv(rx_data4, RX_BUFF_SIZE); - - /* Intentionally break has been omitted (fall-through) */ - switch (block_count) { - case 4: - if (strcmp(tx_data4, rx_data4) != 0) { - return -1; - } - printk("%s\n", rx_data4); - - case 3: - if (strcmp(tx_data3, rx_data3) != 0) { - return -1; - } - printk("%s\n", rx_data3); - - case 2: - if (strcmp(tx_data2, rx_data2) != 0) { - return -1; - } - printk("%s\n", rx_data2); - - case 1: - if (strcmp(tx_data, rx_data) != 0) { - return -1; - } - printk("%s\n", rx_data); - break; - - default: - printk("Invalid block count %d\n", block_count); - return -1; - } - - return 0; -} - -/* export test cases */ -void dma_thread(void) -{ - while (1) { - k_sem_take(&thread_sem, K_FOREVER); - if (test_task(0, 8, 2) == 0) { - printk("DMA Passed\n"); - } else { - printk("DMA Failed\n"); - } - k_sem_give(&thread_sem); - k_sleep(SLEEPTIME); - - k_sem_take(&thread_sem, K_FOREVER); - if (test_task(1, 8, 3) == 0) { - printk("DMA Passed\n"); - } else { - printk("DMA Failed\n"); - } - k_sem_give(&thread_sem); - k_sleep(SLEEPTIME); - - k_sem_take(&thread_sem, K_FOREVER); - if (test_task(0, 16, 4) == 0) { - printk("DMA Passed\n"); - } else { - printk("DMA Failed\n"); - } - k_sem_give(&thread_sem); - k_sleep(SLEEPTIME); - - k_sem_take(&thread_sem, K_FOREVER); - if (test_task(1, 16, 1) == 0) { - printk("DMA Passed\n"); - } else { - printk("DMA Failed\n"); - } - k_sem_give(&thread_sem); - k_sleep(SLEEPTIME); - } -} - -K_THREAD_DEFINE(dma_thread_id, STACKSIZE, dma_thread, NULL, NULL, NULL, - PRIORITY, 0, 0); diff --git a/tests/boards/intel_s1000_crb/main/src/gpio_test.c b/tests/boards/intel_s1000_crb/main/src/gpio_test.c deleted file mode 100644 index 065671447e3cb..0000000000000 --- a/tests/boards/intel_s1000_crb/main/src/gpio_test.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2017 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * - * @brief Sample app to utilize GPIO on Intel S1000 CRB. - * - * Intel S1000 CRB - * --------------- - * - * The gpio_dw driver is being used. - * - * This sample app toggles GPIO_23. It also waits for - * GPIO_24 to go high and display a message. - * - * If GPIOs 23 and 24 are connected together, the GPIO should - * triggers every 1 second. And you should see this repeatedly - * on console: - * " - * Reading GPIO_24 = 0 - * GPIO_24 triggered - * Reading GPIO_24 = 1 - * " - */ - -#include -#include - -#include -#include - -#define GPIO_OUT_PIN 23 -#define GPIO_INT_PIN 24 -#define GPIO_NAME "GPIO_" -#define GPIO_DRV_NAME DT_LABEL(DT_INST(0, snps_designware_gpio)) - -/* size of stack area used by each thread */ -#define STACKSIZE 1024 - -/* scheduling priority used by each thread */ -#define PRIORITY 7 - -/* delay between greetings (in ms) */ -#define SLEEPTIME K_MSEC(500) - -extern struct k_sem thread_sem; - -void gpio_test_callback(const struct device *port, - struct gpio_callback *cb, uint32_t pins) -{ - printk(GPIO_NAME "%d triggered\n", GPIO_INT_PIN); -} - -static struct gpio_callback gpio_cb; - -void setup_gpio(const struct device *gpio_dev) -{ - int ret; - - /* Setup GPIO output */ - ret = gpio_pin_configure(gpio_dev, GPIO_OUT_PIN, GPIO_OUTPUT_LOW); - if (ret) { - printk("Error configuring " GPIO_NAME "%d!\n", GPIO_OUT_PIN); - } - - /* Setup GPIO input, and triggers on rising edge. */ - ret = gpio_pin_configure(gpio_dev, GPIO_INT_PIN, GPIO_INPUT); - if (ret) { - printk("Error configuring " GPIO_NAME "%d!\n", GPIO_INT_PIN); - } - - gpio_init_callback(&gpio_cb, gpio_test_callback, BIT(GPIO_INT_PIN)); - - ret = gpio_add_callback(gpio_dev, &gpio_cb); - if (ret) { - printk("Cannot setup callback!\n"); - } - - ret = gpio_pin_interrupt_configure(gpio_dev, GPIO_INT_PIN, - GPIO_INT_EDGE_RISING); - if (ret) { - printk("Error configuring interrupt on " GPIO_NAME "%d!\n", - GPIO_INT_PIN); - } - - /* Disable the GPIO interrupt. It is enabled by default */ - /* irq_disable(DT_GPIO_DW_0_IRQ); */ -} - -/* gpio_thread is a static thread that is spawned automatically */ -void gpio_thread(void *dummy1, void *dummy2, void *dummy3) -{ - const struct device *gpio_dev; - int ret; - - ARG_UNUSED(dummy1); - ARG_UNUSED(dummy2); - ARG_UNUSED(dummy3); - - gpio_dev = device_get_binding(GPIO_DRV_NAME); - if (!gpio_dev) { - printk("Cannot find %s!\n", GPIO_DRV_NAME); - return; - } - - setup_gpio(gpio_dev); - - while (1) { - /* take semaphore */ - k_sem_take(&thread_sem, K_FOREVER); - - ret = gpio_pin_toggle(gpio_dev, GPIO_OUT_PIN); - if (ret) { - printk("Cannot toggle " GPIO_NAME "%d!\n", - GPIO_OUT_PIN); - } - - ret = gpio_pin_get(gpio_dev, GPIO_INT_PIN); - if (ret < 0) { - printk("Error getting " GPIO_NAME "%d!\n", - GPIO_OUT_PIN); - } else { - printk("Reading "GPIO_NAME"%d = %d\n", GPIO_INT_PIN, - ret); - } - - /* let other threads have a turn */ - k_sem_give(&thread_sem); - - /* wait a while */ - k_sleep(SLEEPTIME); - } -} - -K_THREAD_DEFINE(gpio_thread_id, STACKSIZE, gpio_thread, NULL, NULL, NULL, - PRIORITY, 0, 0); diff --git a/tests/boards/intel_s1000_crb/main/src/i2c_test.c b/tests/boards/intel_s1000_crb/main/src/i2c_test.c deleted file mode 100644 index b45d6a1d3617f..0000000000000 --- a/tests/boards/intel_s1000_crb/main/src/i2c_test.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright (c) 2019 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * - * @brief Sample app to illustrate i2c master-slave communication on Intel S1000 CRB. - * - * Intel S1000 CRB - * --------------- - * - * The i2c_dw driver is being used. - * - * In this sample app, the Intel S1000 CRB master I2C communicates with 2 slave - * LED I2C matrices driving them to emit blue light and red light alternately. - * It can also be programmed to emit white and green light instead. - * While this validates the write functionality, the read functionality is - * verified by reading the LED0 values after each write. It would display - * the below message repeatedly on the console every 500ms. - * - * " - * Reading LED_0 = 41 - * Reading LED_0 = 10 - * " - */ - -#include -#include - -#include -#include - -#define I2C_DEV "I2C_0" -#define I2C_ADDR_LED_MAT0 0x65 -#define I2C_ADDR_LED_MAT1 0x69 -#define LED0 0x02 -#define LED1 0x03 -#define LED2 0x04 -#define LED3 0x05 -#define LED4 0x06 -#define LED5 0x07 - -/* size of stack area used by each thread */ -#define STACKSIZE 1024 - -/* scheduling priority used by each thread */ -#define PRIORITY 7 - -/* delay between greetings (in ms) */ -#define SLEEPTIME 500 - -extern struct k_sem thread_sem; - -void test_i2c_write_led(const struct device *i2c_dev, uint16_t i2c_slave_led, - uint8_t color) -{ - int ret; - int led_val[6]; - - switch (color) { - case 0: /* RED color LED */ - led_val[0] = 0x10; - led_val[1] = 0x04; - led_val[2] = 0x41; - led_val[3] = 0x10; - led_val[4] = 0x04; - led_val[5] = 0x41; - break; - - case 1: /* BLUE color LED */ - led_val[0] = 0x41; - led_val[1] = 0x10; - led_val[2] = 0x04; - led_val[3] = 0x41; - led_val[4] = 0x10; - led_val[5] = 0x04; - break; - - case 2: /* GREEN color LED */ - led_val[0] = 0x04; - led_val[1] = 0x41; - led_val[2] = 0x10; - led_val[3] = 0x04; - led_val[4] = 0x41; - led_val[5] = 0x10; - break; - - case 3: /* WHITE color LED */ - led_val[0] = 0x55; - led_val[1] = 0x55; - led_val[2] = 0x55; - led_val[3] = 0x55; - led_val[4] = 0x55; - led_val[5] = 0x55; - break; - - default: - /* Go dark */ - led_val[0] = 0x00; - led_val[1] = 0x00; - led_val[2] = 0x00; - led_val[3] = 0x00; - led_val[4] = 0x00; - led_val[5] = 0x00; - break; - } - - ret = i2c_reg_write_byte(i2c_dev, i2c_slave_led, 0x40, 0xFF); - ret |= i2c_reg_write_byte(i2c_dev, i2c_slave_led, LED0, led_val[0]); - ret |= i2c_reg_write_byte(i2c_dev, i2c_slave_led, LED1, led_val[1]); - ret |= i2c_reg_write_byte(i2c_dev, i2c_slave_led, LED2, led_val[2]); - ret |= i2c_reg_write_byte(i2c_dev, i2c_slave_led, LED3, led_val[3]); - ret |= i2c_reg_write_byte(i2c_dev, i2c_slave_led, LED4, led_val[4]); - ret |= i2c_reg_write_byte(i2c_dev, i2c_slave_led, LED5, led_val[5]); - if (ret) { - printk("Error writing to LED!\n"); - return; - } -} - -void test_i2c_read_led(const struct device *i2c_dev, uint16_t i2c_slave_led) -{ - int ret; - uint8_t data = 0U; - - ret = i2c_reg_read_byte(i2c_dev, i2c_slave_led, LED0, &data); - if (ret) { - printk("Error reading from LED! error code (%d)\n", ret); - return; - } - printk("LED0 = %x\n", data); -} - -/* i2c_thread is a static thread that is spawned automatically */ -void i2c_thread(void *dummy1, void *dummy2, void *dummy3) -{ - const struct device *i2c_dev; - int toggle = LED_LIGHT_PAT; - - ARG_UNUSED(dummy1); - ARG_UNUSED(dummy2); - ARG_UNUSED(dummy3); - - i2c_dev = device_get_binding(I2C_DEV); - if (!i2c_dev) { - printk("I2C: Device driver not found.\n"); - return; - } - - while (1) { - /* take semaphore */ - k_sem_take(&thread_sem, K_FOREVER); - - if (toggle == LED_LIGHT_PAT) { - toggle = LED_LIGHT_PAT - 1; - } else { - toggle = LED_LIGHT_PAT; - } - - test_i2c_write_led(i2c_dev, I2C_ADDR_LED_MAT0, toggle); - test_i2c_write_led(i2c_dev, I2C_ADDR_LED_MAT1, toggle); - test_i2c_read_led(i2c_dev, I2C_ADDR_LED_MAT0); - - /* let other threads have a turn */ - k_sem_give(&thread_sem); - - /* wait a while */ - k_msleep(SLEEPTIME); - } -} - -K_THREAD_DEFINE(i2c_thread_id, STACKSIZE, i2c_thread, NULL, NULL, NULL, - PRIORITY, 0, 0); diff --git a/tests/boards/intel_s1000_crb/main/src/i2s_test.c b/tests/boards/intel_s1000_crb/main/src/i2s_test.c deleted file mode 100644 index ef4ab8bd4ff9e..0000000000000 --- a/tests/boards/intel_s1000_crb/main/src/i2s_test.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2019 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * - * @brief Test app to illustrate I2S transmission/reception on Intel S1000 CRB - * - * The i2s_cavs driver is being used. - * - * In this test app, I2S transmission and reception are tested as follows: - * I2S port #3 of Intel S1000 is configured for bidirectional mode - * i.e., I2S_DIR_TX and I2S_DIR_RX - * After each frame is received, it is sent/looped back on the same I2S - * The transmit direction is started after 2 frames are queued. This is done to - * ensure that there is enough data for the DMA and I2S are available when the - * start operation is triggered - */ - -#include -#include - -#include -#include - -#define I2S_DEV_NAME "I2S_3" -#define NUM_I2S_BUFFERS 4 - -/* size of stack area used by each thread */ -#define STACKSIZE 2048 - -/* scheduling priority used by each thread */ -#define PRIORITY 7 - -/* delay between greetings (in ms) */ -#define SLEEPTIME K_MSEC(500) - -extern struct k_sem thread_sem; - -#define NUM_OF_CHANNELS 2 -#define FRAME_CLK_FREQ 48000 -#define I2S_WORDSIZE 32 -#define BLOCK_SIZE 192 -#define BLOCK_SIZE_BYTES (BLOCK_SIZE * sizeof(int32_t)) -#define FRAMES_PER_ITERATION 50 -#define TIMEOUT 2000 - -static char __aligned(4) audio_buffers[BLOCK_SIZE_BYTES * NUM_I2S_BUFFERS]; -static struct k_mem_slab i2s_mem_slab; - -/** Configure I2S bidirectional transfer. */ -void test_i2s_bidirectional_transfer_configure(void) -{ - int ret; - const struct device *dev_i2s; - struct i2s_config i2s_cfg; - - k_mem_slab_init(&i2s_mem_slab, audio_buffers, BLOCK_SIZE_BYTES, - NUM_I2S_BUFFERS); - - dev_i2s = device_get_binding(I2S_DEV_NAME); - if (!dev_i2s) { - printk("I2S: Device driver not found.\n"); - return; - } - - /* Configure */ - i2s_cfg.word_size = I2S_WORDSIZE; - i2s_cfg.channels = NUM_OF_CHANNELS; - i2s_cfg.format = I2S_FMT_DATA_FORMAT_I2S | I2S_FMT_CLK_NF_NB; - i2s_cfg.options = I2S_OPT_FRAME_CLK_MASTER | I2S_OPT_BIT_CLK_MASTER; - i2s_cfg.frame_clk_freq = FRAME_CLK_FREQ; - i2s_cfg.block_size = BLOCK_SIZE_BYTES; - i2s_cfg.mem_slab = &i2s_mem_slab; - i2s_cfg.timeout = TIMEOUT; - - ret = i2s_configure(dev_i2s, I2S_DIR_TX, &i2s_cfg); - if (ret != 0) { - printk("I2S_TX configuration failed with %d error\n", ret); - return; - } - ret = i2s_configure(dev_i2s, I2S_DIR_RX, &i2s_cfg); - if (ret != 0) { - printk("I2S_RX configuration failed with %d error\n", ret); - return; - } -} - -/** @brief Bi-Directional I2S transfer. - * - * - TX/RX stream START trigger starts transmission/reception. - * - TX/RX stream STOP trigger stops the transmission/reception. - */ -void test_i2s_bidirectional_transfer(void) -{ - const struct device *dev_i2s; - int frames = 0; - void *buffer; - size_t size; - int ret; - - printk("Testing I2S bidirectional transfer\n"); - dev_i2s = device_get_binding(I2S_DEV_NAME); - if (!dev_i2s) { - printk("I2S: Device driver not found.\n"); - return; - } - - /* Start reception */ - ret = i2s_trigger(dev_i2s, I2S_DIR_RX, I2S_TRIGGER_START); - if (ret != 0) { - printk("RX Start failed with %d error\n", ret); - return; - } - - /* iteratively receive a frame and send it back */ - while (frames++ < FRAMES_PER_ITERATION) { - ret = i2s_read(dev_i2s, &buffer, &size); - if (ret != 0) { - printk("i2s_read failed with %d error\n", ret); - return; - } - - /* send the buffer */ - ret = i2s_write(dev_i2s, buffer, size); - if (ret != 0) { - printk("i2s_write failed with %d error\n", ret); - return; - } - - /* Start transmission after 2 frames are queued */ - if (frames == 2) { - ret = i2s_trigger(dev_i2s, I2S_DIR_TX, - I2S_TRIGGER_START); - if (ret != 0) { - printk("TX Start failed with %d error\n", ret); - return; - } - } - } - - /* Stop transmission */ - ret = i2s_trigger(dev_i2s, I2S_DIR_TX, I2S_TRIGGER_STOP); - if (ret != 0) { - printk("TX Stop failed with %d error\n", ret); - return; - } - - /* Stop reception */ - ret = i2s_trigger(dev_i2s, I2S_DIR_RX, I2S_TRIGGER_STOP); - if (ret != 0) { - printk("RX Stop failed with %d error\n", ret); - return; - } - printk("Completed %d bidirectional frames on " I2S_DEV_NAME "\n", - FRAMES_PER_ITERATION); -} - -/* i2s_thread is a static thread that is spawned automatically */ -void i2s_thread(void *dummy1, void *dummy2, void *dummy3) -{ - ARG_UNUSED(dummy1); - ARG_UNUSED(dummy2); - ARG_UNUSED(dummy3); - - test_i2s_bidirectional_transfer_configure(); - - while (1) { - k_sem_take(&thread_sem, K_FOREVER); - - test_i2s_bidirectional_transfer(); - - /* let other threads have a turn */ - k_sem_give(&thread_sem); - - /* wait a while */ - k_sleep(SLEEPTIME); - } -} - -K_THREAD_DEFINE(i2s_thread_id, STACKSIZE, i2s_thread, NULL, NULL, NULL, - PRIORITY, 0, 0); diff --git a/tests/boards/intel_s1000_crb/main/src/main.c b/tests/boards/intel_s1000_crb/main/src/main.c deleted file mode 100644 index 358fffc8258ca..0000000000000 --- a/tests/boards/intel_s1000_crb/main/src/main.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2017 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#define LOG_LEVEL CONFIG_LOG_DEFAULT_LEVEL -#include - -void test_flash(void); - -LOG_MODULE_REGISTER(main); - -/* This semaphore is used to serialize the UART prints dumped by various - * modules. This prevents mixing of UART prints across modules. This - * semaphore starts off "available". - */ -K_SEM_DEFINE(thread_sem, 1, 1); - -void main(void) -{ - LOG_INF("Sample app running on: %s Intel S1000 CRB\n", CONFIG_ARCH); - - test_flash(); -} diff --git a/tests/boards/intel_s1000_crb/main/src/spi_flash.c b/tests/boards/intel_s1000_crb/main/src/spi_flash.c deleted file mode 100644 index 506eecffc3126..0000000000000 --- a/tests/boards/intel_s1000_crb/main/src/spi_flash.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include -LOG_MODULE_REGISTER(test_flash); - -#define FLASH_TEST_REGION_OFFSET 0x3F0000 -#define FLASH_SECTOR_SIZE 0x10000 -#define TEST_DATA_BYTE_0 0x4f -#define TEST_DATA_BYTE_1 0x4a -#define TEST_DATA_LEN 128 - -int flash_region_is_empty(uint32_t off, void *dst, uint32_t len) -{ - uint8_t i; - uint8_t *u8dst; - int rc; - const struct flash_area *fap; - - rc = flash_area_open(FLASH_AREA_ID(image_scratch), &fap); - if (rc != 0) { - LOG_ERR("SPI flash area open failed!\n"); - return -1; - } - - rc = flash_area_read(fap, off - fap->fa_off, dst, len); - if (rc) { - LOG_ERR("SPI flash efailed!\n"); - return -1; - } - - for (i = 0U, u8dst = (uint8_t *)dst; i < len; i++) { - if (u8dst[i] != 0xFF) { - flash_area_close(fap); - return 0; - } - } - - flash_area_close(fap); - - return 1; -} - -void test_flash(void) -{ - const struct device *flash_dev; - uint8_t buf[TEST_DATA_LEN]; - uint32_t magic[4]; - int i; - - flash_dev = device_get_binding(DT_LABEL(DT_INST(0, jedec_spi_nor))); - - if (!flash_dev) { - LOG_ERR("SPI flash driver was not found!\n"); - return; - } - - LOG_INF("SPI flash driver was found!\n"); - - if (flash_erase(flash_dev, - FLASH_TEST_REGION_OFFSET, - FLASH_SECTOR_SIZE) != 0) { - LOG_ERR(" Flash erase failed!\n"); - } else { - LOG_INF(" Flash erase succeeded!\n"); - } - - buf[0] = TEST_DATA_BYTE_0; - buf[1] = TEST_DATA_BYTE_1; - - for (i = 2 ; i < TEST_DATA_LEN; i++) { - buf[i] = 0x63; - } - - LOG_INF(" Attempted to write %x %x\n", buf[0], buf[1]); - if (flash_write(flash_dev, FLASH_TEST_REGION_OFFSET, buf, - TEST_DATA_LEN) != 0) { - LOG_ERR(" Flash write failed!\n"); - return; - } - - if (flash_read(flash_dev, FLASH_TEST_REGION_OFFSET, buf, - TEST_DATA_LEN) != 0) { - LOG_ERR(" Flash read failed!\n"); - return; - } - - if ((buf[0] == TEST_DATA_BYTE_0) && (buf[1] == TEST_DATA_BYTE_1)) { - LOG_INF(" Data read matches with data written. Good!!\n"); - } else { - LOG_ERR(" Data read does not match with data written!!\n"); - } - - if (flash_region_is_empty( - FLASH_TEST_REGION_OFFSET - 16, magic, 16) == 1) { - LOG_INF(" Flash region is empty. Good!!\n"); - } else { - LOG_ERR(" Flash region is not empty!!\n"); - } -} diff --git a/tests/boards/intel_s1000_crb/main/src/test_hid.c b/tests/boards/intel_s1000_crb/main/src/test_hid.c deleted file mode 100644 index a6294e0220bab..0000000000000 --- a/tests/boards/intel_s1000_crb/main/src/test_hid.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define LOG_LEVEL CONFIG_LOG_DEFAULT_LEVEL -#include -LOG_MODULE_DECLARE(main); - -#include - -#include -#include - -#define REPORT_ID_1 0x01 -#define REPORT_ID_2 0x02 - -/* size of stack area used by each thread */ -#define STACKSIZE 1024 - -/* scheduling priority used by each thread */ -#define PRIORITY 7 - -/* Some HID sample Report Descriptor */ -static const uint8_t hid_report_desc[] = { - /* 0x05, 0x01, USAGE_PAGE (Generic Desktop) */ - HID_GI_USAGE_PAGE, USAGE_GEN_DESKTOP, - /* 0x09, 0x00, USAGE (Undefined) */ - HID_LI_USAGE, USAGE_GEN_DESKTOP_UNDEFINED, - /* 0xa1, 0x01, COLLECTION (Application) */ - HID_MI_COLLECTION, COLLECTION_APPLICATION, - /* 0x15, 0x00, LOGICAL_MINIMUM one-byte (0) */ - HID_GI_LOGICAL_MIN(1), 0x00, - /* 0x26, 0xff, 0x00, LOGICAL_MAXIMUM two-bytes (255) */ - HID_GI_LOGICAL_MAX(2), 0xFF, 0x00, - /* 0x85, 0x01, REPORT_ID (1) */ - HID_GI_REPORT_ID, REPORT_ID_1, - /* 0x75, 0x08, REPORT_SIZE (8) in bits */ - HID_GI_REPORT_SIZE, 0x08, - /* 0x95, 0x01, REPORT_COUNT (1) */ - HID_GI_REPORT_COUNT, 0x01, - /* 0x09, 0x00, USAGE (Undefined) */ - HID_LI_USAGE, USAGE_GEN_DESKTOP_UNDEFINED, - /* v0x81, 0x82, INPUT (Data,Var,Abs,Vol) */ - HID_MI_INPUT, 0x82, - /* 0x85, 0x02, REPORT_ID (2) */ - HID_GI_REPORT_ID, REPORT_ID_2, - /* 0x75, 0x08, REPORT_SIZE (8) in bits */ - HID_GI_REPORT_SIZE, 0x08, - /* 0x95, 0x01, REPORT_COUNT (1) */ - HID_GI_REPORT_COUNT, 0x01, - /* 0x09, 0x00, USAGE (Undefined) */ - HID_LI_USAGE, USAGE_GEN_DESKTOP_UNDEFINED, - /* 0x91, 0x82, OUTPUT (Data,Var,Abs,Vol) */ - HID_MI_OUTPUT, 0x82, - /* 0xc0 END_COLLECTION */ - HID_MI_COLLECTION_END, -}; - -void hid_thread(void) -{ - uint8_t report_1[2] = { REPORT_ID_1, 0x00 }; - const struct device *hid_dev; - int ret, wrote; - - LOG_DBG("Starting application"); - - hid_dev = device_get_binding("HID_0"); - if (hid_dev == NULL) { - LOG_ERR("Cannot get USB HID Device"); - return; - } - - usb_hid_register_device(hid_dev, hid_report_desc, - sizeof(hid_report_desc), NULL); - - usb_hid_init(hid_dev); - - while (true) { - - k_sleep(K_SECONDS(1)); - - report_1[1]++; - - ret = hid_int_ep_write(hid_dev, report_1, sizeof(report_1), - &wrote); - LOG_DBG("Wrote %d bytes with ret %d", wrote, ret); - } -} - -K_THREAD_DEFINE(hid_thread_id, STACKSIZE, hid_thread, NULL, NULL, NULL, - PRIORITY, 0, 0); diff --git a/tests/boards/intel_s1000_crb/main/testcase.yaml b/tests/boards/intel_s1000_crb/main/testcase.yaml deleted file mode 100644 index d081e33053ca0..0000000000000 --- a/tests/boards/intel_s1000_crb/main/testcase.yaml +++ /dev/null @@ -1,4 +0,0 @@ -tests: - boards.s1000_crb.main: - platform_allow: intel_s1000_crb - tags: boards From e164f13022e212001fa1ab13e7c3eea86553e5e5 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 13 Jun 2022 14:26:23 -0400 Subject: [PATCH 3/8] boards: intel_s1000_crb: remove board/soc Remove the intel_s1000_crb board. it is no longer available or supported in the zephyr tree. Signed-off-by: Anas Nashif --- boards/xtensa/intel_s1000_crb/CMakeLists.txt | 14 - boards/xtensa/intel_s1000_crb/Kconfig.board | 8 - .../xtensa/intel_s1000_crb/Kconfig.defconfig | 160 ------ boards/xtensa/intel_s1000_crb/board.cmake | 20 - boards/xtensa/intel_s1000_crb/doc/index.rst | 293 ---------- .../intel_s1000_crb/doc/intel_s1000_crb.png | Bin 36329 -> 0 bytes .../intel_s1000_crb/intel_s1000_crb.dts | 116 ---- .../intel_s1000_crb/intel_s1000_crb.yaml | 14 - .../intel_s1000_crb/intel_s1000_crb_defconfig | 30 - boards/xtensa/intel_s1000_crb/pinmux.c | 55 -- .../xtensa/intel_s1000_crb/support/.gitignore | 1 - .../intel_s1000_crb/support/all_gdb.txt | 32 -- .../xtensa/intel_s1000_crb/support/config.yml | 17 - .../support/create_board_img.py | 223 -------- .../xtensa/intel_s1000_crb/support/device.py | 124 ---- .../intel_s1000_crb/support/download.py | 133 ----- .../intel_s1000_crb/support/dsp0_gdb.txt | 32 -- .../intel_s1000_crb/support/dsp1_gdb.txt | 32 -- .../intel_s1000_crb/support/load_elf.txt | 17 - .../intel_s1000_crb/support/messenger.py | 232 -------- .../support/topology_all_flyswatter2.xml | 24 - .../support/topology_dsp0_flyswatter2.xml | 21 - .../support/topology_dsp1_flyswatter2.xml | 21 - boards/xtensa/xt-sim/Kconfig.board | 3 - boards/xtensa/xt-sim/doc/index.rst | 1 - .../xt-sim/xt-sim_intel_s1000_defconfig | 8 - doc/_scripts/redirects.py | 1 - doc/develop/toolchains/cadence_xcc.rst | 2 +- dts/bindings/pinctrl/intel,s1000-pinmux.yaml | 14 - dts/xtensa/intel/intel_s1000.dtsi | 270 --------- soc/xtensa/intel_s1000/CMakeLists.txt | 13 - soc/xtensa/intel_s1000/Kconfig.defconfig | 48 -- soc/xtensa/intel_s1000/Kconfig.soc | 10 - .../intel_s1000/include/_soc_inthandlers.h | 256 --------- soc/xtensa/intel_s1000/include/cavs-idc.h | 148 ----- soc/xtensa/intel_s1000/include/cavs-shim.h | 144 ----- soc/xtensa/intel_s1000/iomux.h | 87 --- soc/xtensa/intel_s1000/linker.ld | 528 ------------------ soc/xtensa/intel_s1000/memory.h | 80 --- soc/xtensa/intel_s1000/soc.c | 331 ----------- soc/xtensa/intel_s1000/soc.h | 231 -------- soc/xtensa/intel_s1000/soc/shim.h | 268 --------- soc/xtensa/intel_s1000/soc_mp.c | 205 ------- soc/xtensa/intel_s1000/xcc/CMakeLists.txt | 4 - soc/xtensa/intel_s1000/xcc/cpp_fixes.c | 16 - soc/xtensa/intel_s1000/xcc/newlib_fixes.c | 22 - 46 files changed, 1 insertion(+), 4308 deletions(-) delete mode 100644 boards/xtensa/intel_s1000_crb/CMakeLists.txt delete mode 100644 boards/xtensa/intel_s1000_crb/Kconfig.board delete mode 100644 boards/xtensa/intel_s1000_crb/Kconfig.defconfig delete mode 100644 boards/xtensa/intel_s1000_crb/board.cmake delete mode 100644 boards/xtensa/intel_s1000_crb/doc/index.rst delete mode 100644 boards/xtensa/intel_s1000_crb/doc/intel_s1000_crb.png delete mode 100644 boards/xtensa/intel_s1000_crb/intel_s1000_crb.dts delete mode 100644 boards/xtensa/intel_s1000_crb/intel_s1000_crb.yaml delete mode 100644 boards/xtensa/intel_s1000_crb/intel_s1000_crb_defconfig delete mode 100644 boards/xtensa/intel_s1000_crb/pinmux.c delete mode 100644 boards/xtensa/intel_s1000_crb/support/.gitignore delete mode 100644 boards/xtensa/intel_s1000_crb/support/all_gdb.txt delete mode 100644 boards/xtensa/intel_s1000_crb/support/config.yml delete mode 100644 boards/xtensa/intel_s1000_crb/support/create_board_img.py delete mode 100644 boards/xtensa/intel_s1000_crb/support/device.py delete mode 100644 boards/xtensa/intel_s1000_crb/support/download.py delete mode 100644 boards/xtensa/intel_s1000_crb/support/dsp0_gdb.txt delete mode 100644 boards/xtensa/intel_s1000_crb/support/dsp1_gdb.txt delete mode 100644 boards/xtensa/intel_s1000_crb/support/load_elf.txt delete mode 100644 boards/xtensa/intel_s1000_crb/support/messenger.py delete mode 100644 boards/xtensa/intel_s1000_crb/support/topology_all_flyswatter2.xml delete mode 100644 boards/xtensa/intel_s1000_crb/support/topology_dsp0_flyswatter2.xml delete mode 100644 boards/xtensa/intel_s1000_crb/support/topology_dsp1_flyswatter2.xml delete mode 100644 boards/xtensa/xt-sim/xt-sim_intel_s1000_defconfig delete mode 100644 dts/bindings/pinctrl/intel,s1000-pinmux.yaml delete mode 100644 dts/xtensa/intel/intel_s1000.dtsi delete mode 100644 soc/xtensa/intel_s1000/CMakeLists.txt delete mode 100644 soc/xtensa/intel_s1000/Kconfig.defconfig delete mode 100644 soc/xtensa/intel_s1000/Kconfig.soc delete mode 100644 soc/xtensa/intel_s1000/include/_soc_inthandlers.h delete mode 100644 soc/xtensa/intel_s1000/include/cavs-idc.h delete mode 100644 soc/xtensa/intel_s1000/include/cavs-shim.h delete mode 100644 soc/xtensa/intel_s1000/iomux.h delete mode 100644 soc/xtensa/intel_s1000/linker.ld delete mode 100644 soc/xtensa/intel_s1000/memory.h delete mode 100644 soc/xtensa/intel_s1000/soc.c delete mode 100644 soc/xtensa/intel_s1000/soc.h delete mode 100644 soc/xtensa/intel_s1000/soc/shim.h delete mode 100644 soc/xtensa/intel_s1000/soc_mp.c delete mode 100644 soc/xtensa/intel_s1000/xcc/CMakeLists.txt delete mode 100644 soc/xtensa/intel_s1000/xcc/cpp_fixes.c delete mode 100644 soc/xtensa/intel_s1000/xcc/newlib_fixes.c diff --git a/boards/xtensa/intel_s1000_crb/CMakeLists.txt b/boards/xtensa/intel_s1000_crb/CMakeLists.txt deleted file mode 100644 index aa04cf71208c0..0000000000000 --- a/boards/xtensa/intel_s1000_crb/CMakeLists.txt +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_PINMUX_INTEL_S1000) - zephyr_library() - zephyr_library_sources(pinmux.c) -endif() - -set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${BOARD_DIR}/support/create_board_img.py - -i ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin - -o ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}_${BOARD}.bin - -l $ - -sk -) diff --git a/boards/xtensa/intel_s1000_crb/Kconfig.board b/boards/xtensa/intel_s1000_crb/Kconfig.board deleted file mode 100644 index ab0ba36d32ea0..0000000000000 --- a/boards/xtensa/intel_s1000_crb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# XTENSA board configuration - -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INTEL_S1000_CRB - bool "Xtensa on Intel_S1000" - depends on SOC_INTEL_S1000 diff --git a/boards/xtensa/intel_s1000_crb/Kconfig.defconfig b/boards/xtensa/intel_s1000_crb/Kconfig.defconfig deleted file mode 100644 index 4acc82999ea79..0000000000000 --- a/boards/xtensa/intel_s1000_crb/Kconfig.defconfig +++ /dev/null @@ -1,160 +0,0 @@ -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_INTEL_S1000_CRB - -config BOARD - default "intel_s1000_crb" - -config CAVS_ICTL_0_OFFSET - default 6 -config CAVS_ICTL_1_OFFSET - default 10 -config CAVS_ICTL_2_OFFSET - default 13 -config CAVS_ICTL_3_OFFSET - default 16 - -config 2ND_LVL_INTR_00_OFFSET - default CAVS_ICTL_0_OFFSET -config 2ND_LVL_INTR_01_OFFSET - default CAVS_ICTL_1_OFFSET -config 2ND_LVL_INTR_02_OFFSET - default CAVS_ICTL_2_OFFSET -config 2ND_LVL_INTR_03_OFFSET - default CAVS_ICTL_3_OFFSET -config 3RD_LVL_INTR_00_OFFSET - default 7 - -config MAX_IRQ_PER_AGGREGATOR - default 32 -config NUM_2ND_LEVEL_AGGREGATORS - default 4 -config NUM_3RD_LEVEL_AGGREGATORS - default 1 -config 2ND_LVL_ISR_TBL_OFFSET - default 21 -config 3RD_LVL_ISR_TBL_OFFSET - default 149 - -config CAVS_ISR_TBL_OFFSET - default 2ND_LVL_ISR_TBL_OFFSET -config DW_ISR_TBL_OFFSET - default 3RD_LVL_ISR_TBL_OFFSET - -config ROM_START_OFFSET - default 0x100 - depends on BOOTLOADER_MCUBOOT - -if USB_DEVICE_STACK - -config USB_DW - default y - -config USB_DW_USB_2_0 - default y - -config USB_REQUEST_BUFFER_SIZE - default 128 - depends on USB_DEVICE_HID - -config USB_REQUEST_BUFFER_SIZE - default 4096 - depends on USB_DFU_CLASS - -config USB_DEVICE_VID - default "0x8087" - -config USB_DEVICE_PID - default "0x0B1A" - -config USB_DEVICE_MANUFACTURER - default "Intel(R) Corporation" - -config USB_DEVICE_PRODUCT - default "Sue Creek (S1000) ASIC" - -endif # USB_DEVICE_STACK - -if SERIAL - -config UART_INTERRUPT_DRIVEN - default y - -endif # SERIAL - -if I2C - -config I2C_DW - default y - -endif - -config DMA_DW - default y - depends on DMA - -config I2S_CAVS - default y - depends on I2S - -if AUDIO -config AUDIO_CODEC - default y - -config AUDIO_TLV320DAC - default y - -config AUDIO_DMIC - default y - -config AUDIO_INTEL_DMIC - default y - -endif - -config INTEL_GNA - default y - depends on NEURAL_NET_ACCEL - -if GPIO - -config GPIO_INIT_PRIORITY - default 70 - -config GPIO_DW - default y - -config GPIO_DW_0 - default y - -endif - -if FLASH - -config SPI - default y - -config SPI_NOR - default y - -config FLASH_HAS_PAGE_LAYOUT - default y - -config FLASH_PAGE_LAYOUT - default y - -endif - -if SPI - -config SPI_DW - default y - -endif - -config PINMUX_INTEL_S1000 - default y - depends on PINMUX - -endif # BOARD_INTEL_S1000_CRB diff --git a/boards/xtensa/intel_s1000_crb/board.cmake b/boards/xtensa/intel_s1000_crb/board.cmake deleted file mode 100644 index 58c03a3e23a6f..0000000000000 --- a/boards/xtensa/intel_s1000_crb/board.cmake +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_set_flasher_ifnset(intel_s1000) -board_set_debugger_ifnset(intel_s1000) - -if(CONFIG_SMP) -board_finalize_runner_args(intel_s1000 - "--xt-ocd-dir=/opt/tensilica/xocd-12.0.4/xt-ocd" - "--ocd-topology=topology_all_flyswatter2.xml" - "--ocd-jtag-instr=all_gdb.txt" - "--gdb-flash-file=load_elf.txt" -) -else() -board_finalize_runner_args(intel_s1000 - "--xt-ocd-dir=/opt/tensilica/xocd-12.0.4/xt-ocd" - "--ocd-topology=topology_dsp0_flyswatter2.xml" - "--ocd-jtag-instr=dsp0_gdb.txt" - "--gdb-flash-file=load_elf.txt" -) -endif() diff --git a/boards/xtensa/intel_s1000_crb/doc/index.rst b/boards/xtensa/intel_s1000_crb/doc/index.rst deleted file mode 100644 index dcdf1b0535857..0000000000000 --- a/boards/xtensa/intel_s1000_crb/doc/index.rst +++ /dev/null @@ -1,293 +0,0 @@ -.. _Intel_S1000: - -Intel S1000 CRB -############### - -Overview -******** - -The Intel S1000 ASIC is designed for complex far-field signal processing -algorithms that use high dimensional microphone arrays to do beamforming, -cancel echoes, and reduce noise. It connects to a host processor chip via -simple SPI and I2S interfaces, to the microphone array via I2S or PDM -interfaces, and to speakers via I2S. In addition, it has an I2C interface -for controlling platform components such as ADCs, DACs, CODECs and PMICs. - -.. image:: ./intel_s1000_crb.png - :width: 442px - :align: center - :alt: Intel Speech Enabling Developer Kit - -The Intel S1000 contains the following: - -- Dual DSP - - - Dual 400 MHz Tensilica HiFi3 cores - - Single precision scalar floating-point - - 16KB 4-way I$; 48KB 4-way D$ - -- Inference Engine - - - On-chip Neural Network Accelerator - -- Internal Memory - - - 4MB shared embedded SRAM - - 64KB embedded SRAM for streaming samples in low power mode - -- External Memory Interfaces - - - Up to 8MB external 16-bit PSRAM - - Up to 128MB external SPI flash - -- I/O Interfaces - - - Host I/O: SPI or USB 2.0 High-speed device - - Microphone: I2S/TDM 9.6 MHz max. bit clock - - Digital Microphone: 4 stereo PDM ports up to 4.8 MHz clock - - Speaker: I2S/TDM 9.6 MHz max. bit clock - - Instrumentation: I2C master @ 100/400 KHz - - Debug: UART up to 2.4 Mbaud/s - - GPIO: 8 GPIOs with PWM output capability - - -.. note:: - - This board is not available for purchase anymore. - -System requirements -******************* - -Prerequisites -============= - -The Xtensa 'toolchain' i.e. XCC is required to build this port. This needs a -license and is available for Linux and Windows from Cadence. - -In order to download the installer and the core configuration, users need to -have a registered account at https://tensilicatools.com. - -The toolchain installer and the core configuration can be downloaded by following -the links at `Tensilica Tools for Sue Creek`_ - -Select version RI-2018.0 and download the archive. The archive contains two files: - -- Installer: :file:`Xplorer-8.0.8-linux-x64-installer.bin` and -- Core configuration - :file:`X6H3SUE_RI_2018_0_linux_redist.tgz` - -For JTAG based debugging, download the XOCD package as well. - -A node locked license key can also be generated from the `SDK portal`_. - -.. note:: - - Please upgrade to RI-2018.0 version of XCC if you have previously installed - the older RF-2016.4 version of XCC. The old toolchain does not support - the C/C++ standards required for building Zephyr applications. - -Set up build environment -======================== - -Run the installer using these commands: - -.. code-block:: console - - cd ~/Downloads - chmod +x Xplorer-8.0.8-linux-installer.bin - ./Xplorer-8.0.8-linux-installer.bin - -Please note a dialogue box should pop-up after running this command. In case the -graphical installation tool does not start, the tool will revert to console -based installation. The graphical tool is the preferred installation method. - -If the graphical tool does not start, it means your system is missing some -packages which is preventing successful installation, most probably -``gtk2-i686``. You can install any missing packages with:: - - sudo apt-get install gtk2-i686 - -On Fedora 29 you might need to install the following packages:: - - sudo dnf install libXtst.i686 libnsl.i686 gtk2.i686 - -.. note:: - - The SDK is a 32 bit binary, so you will need to install 32bit compatibility - packages for this work. - -Follow the instructions and install the toolchain and related tools in your -preferred path. - -After a successful installation of the tool, run the Xtensa Xplorer (it will run -automatically after installation is done) and follow the steps to install the -software keys you have downloaded from `Tensilica Tools for Sue Creek`_ - - -.. note:: - - The license key you have requested is tied to the Ethernet MAC address on the - host system. The license manager expects a network device named ``eth0`` or - ``eth1``. On many modern Linux distribution the naming scheme is different - and determined automatically. You will need to either force the naming to - follow what the license manager expects or create a dedicated ethernet device - for this to work. - - On Ubuntu 18.04 LTS, you can install the license key manually with - - .. code-block:: console - - cp sue-creek-SDK-license.dat /XtDevTools/install/tools/RI-2018.0-linux/XtensaTools/Tools/lic/license.dat" - -After the tool chain is successfully installed, the core build needs to be -installed as follows - -.. code-block:: console - - tar -xvzf X6H3SUE_RI_2018_0_linux_redist.tgz --directory /XtDevTools/install/builds - cd /XtDevTools/install/builds/RI-2018.0-linux/X6H3SUE_RI_2018_0 - ./install - -The :file:`install` script is the Xtensa Processor Configuration Installation -Tool which is required to update the installation path. When it prompts to -enter the path to the Xtensa Tools directory, enter -:file:`/XtDevTools/install/tools/RI-2018.0-linux/XtensaTools`. -You should use the default registry -:file:`/XtDevTools/install/tools/RI-2018.0-linux/XtensaTools/config`. - -With the XCC toolchain installed, the Zephyr build system must be instructed -to use this particular variant by setting the ``ZEPHYR_TOOLCHAIN_VARIANT`` -shell variable. Some more environment variables are also required (see below): - -.. code-block:: console - - export XTENSA_TOOLCHAIN_PATH= - export ZEPHYR_TOOLCHAIN_VARIANT=xcc - export TOOLCHAIN_VER=RI-2018.0-linux - export XTENSA_CORE=X6H3SUE_RI_2018_0 - export XTENSA_SYSTEM=${XTENSA_TOOLCHAIN_PATH}/XtDevTools/install/tools/RI-2018.0-linux/XtensaTools/config/ - export XTENSA_BUILD_PATHS=${XTENSA_TOOLCHAIN_PATH}/XtDevTools/install/builds/ - export XTENSA_OCD_PATH=/xocd-12.0.4 - -Programming and Debugging -************************* - -Flashing -======== - -The usual ``flash`` target will work with the ``intel_s1000_crb`` board -configuration using JTAG. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: intel_s1000_crb - :goals: flash - -Refer to :ref:`build_an_application` and :ref:`application_run` for -more details. - -Downloading binary image -======================== - -A Linux host connected to the SPI interface of the ``intel_s1000_crb`` board -can download a zephyr binary to RAM and execute the image. - -.. code-block:: console - - cd /build - sudo -E python3 \ - $ZEPHYR_BASE/boards/xtensa/intel_s1000_crb/support/download.py \ - zephyr/zephyr.bin - -The script depends on a few python modules. These dependencies can be installed -on the Linux host using the command below. - -.. code-block:: console - - pip3 install --user pyyaml python-periphery hashlib bitstruct - -Setting up UART -=============== - -We recommend using a "FT232RL FTDI USB To TTL Serial Converter Adapter Module" -to tap the UART data. The J8 Header on S1000 CRB is dedicated for UART. -Connect the J8 header and UART chip as shown below: - -+------------+-----------+ -| UART chip | J8 Header | -+============+===========+ -| DTR | | -+------------+-----------+ -| RX | 2 | -+------------+-----------+ -| TX | 4 | -+------------+-----------+ -| VCC | | -+------------+-----------+ -| CTS | | -+------------+-----------+ -| GND | 10 | -+------------+-----------+ - -Attach one end of the USB cable to the UART chip and the other end to the -Linux system. Use ``minicom`` or another terminal emulator to monitor the -UART data by following these steps: - -.. code-block:: console - - dmesg | grep USB - minicom -D /dev/ttyUSB0 - -Here, the first command will indicate the tty to which the USB is connected. -The second command assumes it was USB0 and opens up minicom. You can suitably -modify the second command based on the output of the first command. The serial -settings configured in zephyr is "115200 8N1". This is also the default -settings in minicom and can be verified by pressing Ctrl-A Z P. - -Using JTAG -========== - -For debugging and flashing, you can use a flyswatter2 to connect to the Intel -S1000 CRB. -The pinouts for flyswatter2 and the corresponding pinouts for CRB are -shown below. Note that pin 6 on CRB is left unconnected. - -The corresponding pin mapping is - -+-----------+-------------+-------------+-----------+ -| S1000 | Flyswatter2 | Flyswatter2 | S1000 | -+===========+=============+=============+===========+ -| 7 | 1 | 11 | NC | -+-----------+-------------+-------------+-----------+ -| NC | 2 | 12 | NC | -+-----------+-------------+-------------+-----------+ -| 4 | 3 | 13 | 5 | -+-----------+-------------+-------------+-----------+ -| NC | 4 | 14 | NC | -+-----------+-------------+-------------+-----------+ -| 3 | 5 | 15 | NC | -+-----------+-------------+-------------+-----------+ -| 8 | 6 | 16 | NC | -+-----------+-------------+-------------+-----------+ -| 2 | 7 | 17 | NC | -+-----------+-------------+-------------+-----------+ -| NC | 8 | 18 | NC | -+-----------+-------------+-------------+-----------+ -| 1 | 9 | 19 | NC | -+-----------+-------------+-------------+-----------+ -| NC | 10 | 20 | NC | -+-----------+-------------+-------------+-----------+ - -Ideally, these connections should have been enough to get the debug working. -However, we need to short 2 pins on Host Connector J3 via a 3.3k resistor -(simple shorting without the resistor will also do) for debugging to work. -Those 2 pins are Pin5 HOST_RST_N_LT_R) and Pin21 (+V_HOST_3P3_1P8). - -.. target-notes:: - -.. _`FT232 UART`: https://www.amazon.com/FT232RL-Serial-Converter-Adapter-Arduino/dp/B06XDH2VK9 - -.. _Tensilica Tools for Sue Creek: https://tensilicatools.com/platform/intel-sue-creek - -.. _SDK portal: https://tensilicatools.com diff --git a/boards/xtensa/intel_s1000_crb/doc/intel_s1000_crb.png b/boards/xtensa/intel_s1000_crb/doc/intel_s1000_crb.png deleted file mode 100644 index 5ce1fe2b193bbcb20fdf70196cc4df0c8db6a8d4..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 36329 zcmV)1K+V62P)00CYI0{{R3M2{UX00093P)t-s0002Y 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deleted file mode 100644 index 1924c28e18f42..0000000000000 --- a/boards/xtensa/intel_s1000_crb/intel_s1000_crb.dts +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -/dts-v1/; - -#include - -/ { - model = "intel_s1000_crb"; - compatible = "intel,s1000"; - - aliases { - uart-0 = &uart0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,flash-controller = &flash0; - }; - - dmic: dmic { - compatible = "intel,dmic"; - label = "PDM"; - - status = "okay"; - dmas = <&dma0 0 - &dma0 1>; - dma-names = "rx-a", "rx-b"; - }; -}; - -&cpu0 { - clock-frequency = <400000000>; -}; - -&cpu1 { - clock-frequency = <400000000>; -}; - -&gpio0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - - codec0: tlv320dac@18 { - compatible = "ti,tlv320dac"; - reg = <0x18>; - label = "TLV320DAC"; - reset-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; - }; -}; - -&spi0 { - status = "okay"; - - flash0: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <2000000>; - label = "MX25UM512"; - jedec-id = [c2 80 3a]; - size = <0x2000000>; - }; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* The flash is 64MB in size. Each sector is 4kB and - * 16 sectors make a block (64kB). The flash is partitioned - * in terms of blocks. - */ - - /* Reserve 192kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00030000>; - read-only; - }; - - /* Reserve 1856kB for the application in slot 0 */ - slot0_partition: partition@30000 { - label = "image-0"; - reg = <0x00030000 0x001D0000>; - }; - - /* Reserve 1856kB for the application in slot 1 */ - slot1_partition: partition@200000 { - label = "image-1"; - reg = <0x00200000 0x001D0000>; - }; - - /* Reserve 192kB for the scratch partition */ - scratch_partition: partition@3d0000 { - label = "image-scratch"; - reg = <0x003d0000 0x00030000>; - }; - }; -}; - -zephyr_udc0: &usb { - status = "okay"; -}; diff --git a/boards/xtensa/intel_s1000_crb/intel_s1000_crb.yaml b/boards/xtensa/intel_s1000_crb/intel_s1000_crb.yaml deleted file mode 100644 index 3a940a4e87750..0000000000000 --- a/boards/xtensa/intel_s1000_crb/intel_s1000_crb.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: intel_s1000_crb -name: Intel S1000 using cAVS (converged Audio Voice and Speech) -type: mcu -arch: xtensa -toolchain: - - xcc - - xtools - - zephyr -supported: - - i2s -testing: - ignore_tags: - - net - - bluetooth diff --git a/boards/xtensa/intel_s1000_crb/intel_s1000_crb_defconfig b/boards/xtensa/intel_s1000_crb/intel_s1000_crb_defconfig deleted file mode 100644 index 10db61c004998..0000000000000 --- a/boards/xtensa/intel_s1000_crb/intel_s1000_crb_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_SOC_INTEL_S1000=y -CONFIG_BOARD_INTEL_S1000_CRB=y - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - -CONFIG_XTENSA_RESET_VECTOR=y -CONFIG_XTENSA_USE_CORE_CRT1=y - -CONFIG_MULTI_LEVEL_INTERRUPTS=y -CONFIG_2ND_LEVEL_INTERRUPTS=y -CONFIG_3RD_LEVEL_INTERRUPTS=y -CONFIG_CAVS_ICTL=y -CONFIG_DW_ICTL=y - -CONFIG_BOOTLOADER_SRAM_SIZE=192 - - -CONFIG_GPIO=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_NS16550=y - -CONFIG_PINMUX=y -CONFIG_PINMUX_INTEL_S1000=y diff --git a/boards/xtensa/intel_s1000_crb/pinmux.c b/boards/xtensa/intel_s1000_crb/pinmux.c deleted file mode 100644 index 60cb92348c6d9..0000000000000 --- a/boards/xtensa/intel_s1000_crb/pinmux.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2018 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include "iomux.h" - -/* - * :::::::::::: NOTE :::::::::::: - * For a list of possible I/O MUX settings, - * See soc/xtensa/intel_s1000/iomux.h - */ - -/* - * Initializes the I/O MUX with the setting needed per Intel S1000 CRB - * For customizations, please refer to the table above for available settings - * Please note that a call to pinmux_pin_set is only needed when a setting - * that is not default is required - */ -static int intel_s1000_pinmux_init(const struct device *dev) -{ - const struct device *pinmux; - - pinmux = DEVICE_DT_GET(DT_INST(0, intel_s1000_pinmux)); - - __ASSERT_NO_MSG(device_is_ready(pinmux)); - - if (!device_is_ready(pinmux)) { - return -ENXIO; - } - - /* Select PDM instead of I2S0 since board has 8 microphones */ - pinmux_pin_set(pinmux, PIN_GROUP(I2S0), PINMUX_FUNC_B); - - /* - * I2S3 is wired to the host interface connector. - * Select GPIO to avoid any conflict with hosts that may be driving - * the signals. - */ - pinmux_pin_set(pinmux, PIN_GROUP(I2S3), PINMUX_FUNC_B); - - /* TI DAC is on I2C1. Usually, there is no device on I2C0 */ - pinmux_pin_set(pinmux, PIN_GROUP(I2C), PINMUX_FUNC_B); - - /* Intel S1000 CRB has an octal SPI flash. Select MST_DQ */ - pinmux_pin_set(pinmux, PIN_GROUP(EM_DQ), PINMUX_FUNC_B); - - return 0; -} - -SYS_INIT(intel_s1000_pinmux_init, PRE_KERNEL_2, CONFIG_PINMUX_INIT_PRIORITY); diff --git a/boards/xtensa/intel_s1000_crb/support/.gitignore b/boards/xtensa/intel_s1000_crb/support/.gitignore deleted file mode 100644 index 1d3ed4c17a4a5..0000000000000 --- a/boards/xtensa/intel_s1000_crb/support/.gitignore +++ /dev/null @@ -1 +0,0 @@ -config.yml diff --git a/boards/xtensa/intel_s1000_crb/support/all_gdb.txt b/boards/xtensa/intel_s1000_crb/support/all_gdb.txt deleted file mode 100644 index f182671d52043..0000000000000 --- a/boards/xtensa/intel_s1000_crb/support/all_gdb.txt +++ /dev/null @@ -1,32 +0,0 @@ -#Initialization script format -#COMMAND LENGTH DATA -# -#COMMAND: 1 - Scan DR branch -# 2 - Scan IR branch -# 3 - Send TRST -# -#LENGTH: Number of bits to send out (in decimal format). -# -#DATA: Data to send out. A sequence of bytes separated by space. -# The rightmost bit is scanned out first. E.g. (B4 B3 B2 B1 B0) -# -## Examples -# -# Perform TAP Reset: -3 -## all stap disable -2 8 12 -1 6 0 -# Scan out MTAP IDCODE command (0x2) a265013h -## all stap enable -2 8 12 -1 6 05 -# -# -# Scan out (2 cores): -# Send Trax Access IR command to 1st core and bypass to 2nd -#2 10 3 9F -# Write to DOSR register of 1st core (NAR part) -#1 9 1 07 -# Write 32 bits to DOSR register (NDR part) -#1 33 1 98 13 45 ab diff --git a/boards/xtensa/intel_s1000_crb/support/config.yml b/boards/xtensa/intel_s1000_crb/support/config.yml deleted file mode 100644 index b89a8a4b7d5ea..0000000000000 --- a/boards/xtensa/intel_s1000_crb/support/config.yml +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2019 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# -# Author: Sathish Kuttan - -general: - name: Sue Creek - -spi: - device: /dev/spidev0.0 - max_speed: 9.6 # Max SPI clock frequency 9.6 MHz - -gpio: - reset: 22 # GPIO 22 for resetting device - wake: 23 # GPIO 23 for wake notification to device - irq: 27 # GPIO 27 for interrupt notification from device diff --git a/boards/xtensa/intel_s1000_crb/support/create_board_img.py b/boards/xtensa/intel_s1000_crb/support/create_board_img.py deleted file mode 100644 index d9b73dc68d59b..0000000000000 --- a/boards/xtensa/intel_s1000_crb/support/create_board_img.py +++ /dev/null @@ -1,223 +0,0 @@ -#!/usr/bin/env python3 -# -# Copyright (c) 2019 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -# This script will add specific headers and FW load message to tell -# intel_s1000 ROM bootloader to load the firmware -# Usage python3 ${ZEPHYR_BASE}/scripts/create_board_img.py -# -i in_file.bin -o out_file.bin -l zephyr_prebuilt.elf -# [-m|--no_sram] [-c|--no_l1cache] [-t|--no_tlb] -# [-x|--no_exec] [-s|--no_sha] [-k|--clk_sel] - -import argparse -import os -import sys -import struct -from elftools.elf.elffile import ELFFile - -help_text=""" -The flash memory needs to have specific headers and fw load message to tell -the ROM bootloader to load firmware. - -To run script use command: - -create_board_img.py -i in_file.bin -o out_file.bin -l zephyr_prebuilt.elf - [-m|--no_sram] [-c|--no_l1cache] [-t|--no_tlb] - [-x|--no_exec] [-s|--no_sha] [-k|--clk_sel] -""" - -FLASH_PART_TABLE_OFFSET = (0x1000) -FLASH_SECTOR_SIZE = (4 * 1024) -FLASH_MAGIC_WORD = (0x30504353) - -SRAM_SIZE = (1024*1024*4) -MAX_FLASH_FILE_SIZE = (1024*1024*2) -SIZEOF_IPC64 = (64) -ROM_CONTROL_MEMWRITE = (0x11) -ROM_CONTROL_LOADFW = (0x2) -ROM_CONTROL_EXEC = (0x13) - -FW_LOAD_NO_L1_CACHE = (1 << 29) -FW_LOAD_NO_SRAM_FLAG = (1 << 28) -FW_LOAD_NO_TLB_FLAG = (1 << 27) -FW_LOAD_NO_EXEC_FLAG = (1 << 26) -FW_LOAD_NO_SHA_FLAG = (1 << 25) -FW_LOAD_CLK_SEL = (1 << 21) - -# File write buffer -flash_content = [] -write_buf = [] - -def debug(text): - sys.stdout.write(os.path.basename(sys.argv[0]) + ": " + text + "\n") - -def error(text): - sys.exit(os.path.basename(sys.argv[0]) + ": " + text) - -def set_magic_number(value): - flash_content.append(value) - -def set_partition_table_pointer(value): - flash_content.append(value) - -def ipc_load_fw(fw_size, fw_offset): - dword_count = 3 - load_flags = 0 - clock_sel = 0 - - dword_count = 0x3ff & dword_count - - debug("Creating flash image with following options:") - - if args.no_sram: - load_flags |= FW_LOAD_NO_SRAM_FLAG - debug("-m no_sram") - - if args.no_l1cache: - load_flags |= FW_LOAD_NO_L1_CACHE - debug("-c no_l1cache") - - if args.no_tlb: - load_flags |= FW_LOAD_NO_TLB_FLAG - debug("-t no_tlb") - - if args.no_exec: - load_flags |= FW_LOAD_NO_EXEC_FLAG - debug("-x no_exec") - - if args.no_sha: - load_flags |= FW_LOAD_NO_SHA_FLAG - debug("-s no_sha") - - if args.clk_sel: - clock_sel = FW_LOAD_CLK_SEL - debug("-k clk_sel") - - with open(args.kernel, "rb") as fp_kernel: - kernel = ELFFile(fp_kernel) - load_address = kernel.header['e_entry'] - debug("load address = 0x%X" % load_address) - - msg_header = 0x81000000 | ROM_CONTROL_LOADFW - ext_header = 0x80000000 | dword_count | load_flags | clock_sel - - flash_content.append(msg_header) - flash_content.append(ext_header) - flash_content.append(load_address) - flash_content.append(fw_offset) - flash_content.append(fw_size) - -def ipc_dbg_exec(address): - dword_count = 1 - dword_count = 0x3ff & dword_count - - msg_header = 0x81000000 | ROM_CONTROL_EXEC - ext_header = 0x0 | dword_count - - flash_content.append(msg_header) - flash_content.append(ext_header) - flash_content.append(address) - -def ipc_dbg_memwrite(address, value): - dword_count = 2 - dword_count = 0x3ff & dword_count - - msg_header = 0x81000000 | ROM_CONTROL_MEMWRITE - ext_header = 0x0 | dword_count - - flash_content.append(msg_header) - flash_content.append(ext_header) - flash_content.append(address) - flash_content.append(value) - -def parse_args(): - global args - parser = argparse.ArgumentParser( - description=help_text, - formatter_class=argparse.RawTextHelpFormatter) - - parser.add_argument("-i", "--in_file", required=True, - help="Input FW Bin File") - parser.add_argument("-o", "--out_file", required=True, - help="Output Flash Bin File") - parser.add_argument("-l", "--kernel", required=True, - help="Zephyr kernel image") - parser.add_argument("-m", "--no_sram", action="store_true", - help="No SRAM") - parser.add_argument("-c", "--no_l1cache", action="store_true", - help="No L1 Cache") - parser.add_argument("-t", "--no_tlb", action="store_true", - help="No TLB") - parser.add_argument("-x", "--no_exec", action="store_true", - help="No Exec") - parser.add_argument("-s", "--no_sha", action="store_true", - help="No SHA") - parser.add_argument("-k", "--clk_sel", action="store_true", - help="Clock Select") - - args = parser.parse_args() - -def main(): - global flash_content, write_buf - parse_args() - - in_file_size = os.path.getsize(args.in_file) - if in_file_size == 0: - error("%s file has no content\n" % args.in_file) - - out_file_size = FLASH_PART_TABLE_OFFSET + in_file_size - - # round up the flash size to sector boundary - zeropad_size = FLASH_SECTOR_SIZE - (out_file_size % FLASH_SECTOR_SIZE) - out_file_size += zeropad_size - if out_file_size > MAX_FLASH_FILE_SIZE: - error("%s exceeds %d bytes\n" % (args.out_file, MAX_FLASH_FILE_SIZE)) - - # pre-boot initialization commands - set_magic_number(FLASH_MAGIC_WORD) - set_partition_table_pointer(FLASH_PART_TABLE_OFFSET) - ipc_dbg_memwrite(0x71d14, 0x0) - ipc_dbg_memwrite(0x71d24, 0x0) - ipc_dbg_memwrite(0x304628, 0xd) - ipc_dbg_memwrite(0x71fd0, 0x3) - - # load the image at address FLASH_PART_TABLE_OFFSET in flash to SRAM - # at load_address (determined by the entrypoint in the supplied elf) - ipc_load_fw(SRAM_SIZE, FLASH_PART_TABLE_OFFSET) - - # pad zeros until FLASH_PART_TABLE_OFFSET - num_zero_pad = FLASH_PART_TABLE_OFFSET // 4 - len(flash_content) - flash_content += num_zero_pad * [0] - - # read contents of firmware input file and change the endianness - with open(args.in_file, "rb") as in_fp: - read_buf = in_fp.read() - in_fp.close() - for itr in range(int(in_file_size/4)): - write_buf.append(read_buf[itr*4 + 3]) - write_buf.append(read_buf[itr*4 + 2]) - write_buf.append(read_buf[itr*4 + 1]) - write_buf.append(read_buf[itr*4 + 0]) - - # pad zeros until the sector boundary - write_buf += zeropad_size*[0] - - # Generate the file which should be downloaded to Flash - with open(args.out_file, "wb") as out_fp: - # write as a uint (4 bytes) with byte order swapped (big-endian) - out_fp.write(struct.pack(">{}I".format(len(flash_content)), - *flash_content)) - - # write as a byte - out_fp.write(struct.pack("{}B".format(len(write_buf)), - *write_buf)) - - out_fp.close() - - debug("Input %s = %ld bytes" % (os.path.basename(args.in_file), in_file_size)) - debug("Output %s = %ld bytes" % (os.path.basename(args.out_file), out_file_size)) - -if __name__ == "__main__": - main() diff --git a/boards/xtensa/intel_s1000_crb/support/device.py b/boards/xtensa/intel_s1000_crb/support/device.py deleted file mode 100644 index f804164cf45fd..0000000000000 --- a/boards/xtensa/intel_s1000_crb/support/device.py +++ /dev/null @@ -1,124 +0,0 @@ -#!/usr/bin/env python3 -# -# Copyright (c) 2019 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# -# Author: Sathish Kuttan - -# This file defines device class that contains functions to -# setup/configure SPI master device and GPIO pins required -# to communicate with the target. -# Member functions are provided to send and receive messages -# over the SPI bus - -import yaml -import time -import periphery -import sys -import os - -class Device: - """ - Device class containing the interface methods for communicating - with the target using SPI bus and GPIOs - """ - def __init__(self): - """ - Read config file and determine the SPI device, speed, mode - GPIO pin assignments, etc. - Initialize data structures accordingly. - """ - config_file = os.path.dirname(__file__) - config_file += '/config.yml' - with open(config_file, 'r') as ymlfile: - config = yaml.safe_load(ymlfile) - self.name = config['general']['name'] - self.spi_device = config['spi']['device'] - self.spi_speed = config['spi']['max_speed'] - self.spi_mode = None - self.gpio_reset = config['gpio']['reset'] - self.gpio_wake = config['gpio']['wake'] - self.gpio_irq = config['gpio']['irq'] - self.spi = None - self.reset_pin = None - self.wake_pin = None - self.irq_pin = None - - def print_config(self): - """ - Print configuration information that was read from config file - """ - print('%s Device on %s' %(self.name, self.spi_device)) - print('Max SPI Frequency: %2.1f MHz' % self.spi_speed) - print('Reset GPIO: %d' % self.gpio_reset) - print('Wake GPIO : %d' % self.gpio_wake) - print('IRQ GPIO : %d' % self.gpio_irq) - - def configure_device(self, spi_mode, order, bits): - """ - Configure the SPI device and GPIOs for communication with target - """ - self.reset_pin = periphery.GPIO(self.gpio_reset, 'out') - self.wake_pin = periphery.GPIO(self.gpio_wake, 'out') - self.irq_pin = periphery.GPIO(self.gpio_irq, 'in') - self.spi = periphery.SPI(self.spi_device, spi_mode, - self.spi_speed * 1e6) - self.spi.bit_order = order - self.spi.bits_per_word = bits - print('Configured SPI %s for %s.' % (self.spi_device, self.name)) - print('Configured GPIO %d for %s Reset.' % (self.gpio_reset, self.name)) - print('Configured GPIO %d for %s Wake.' % (self.gpio_wake, self.name)) - print('Configured GPIO %d for %s IRQ.' % (self.gpio_irq, self.name)) - - def check_device_ready(self): - """ - Check whether the target is ready to accept a command as follows: - Wait a minimum time and check whether IRQ is asserted by the target - If IRQ is not asserted, wait maximum time and check again. - Device is ready if IRQ is asserted - """ - min_wait = 0.001 # 1 ms - max_wait = 0.1 # 100 ms - time.sleep(min_wait) - ready = self.irq_pin.read() - if not ready: - time.sleep(max_wait) - ready = self.irq_pin.read() - if not ready: - print('Error: Device not ready', file=sys.stderr) - return ready - - def reset_device(self): - """ - Assert the GPIO and deassert after a short duration to reset - the target. - """ - print('Resetting %s ...' % self.name) - self.reset_pin.write(False) - time.sleep(0.1) - self.reset_pin.write(True) - self.check_device_ready() - - def send_receive(self, data, wait=True): - """ - Transmit and receive full duplex data over SPI - If requested to wait, wait for device to become ready - before return. - """ - rx_data = self.spi.transfer(data) - if wait: - self.check_device_ready() - return rx_data - - def send_bulk(self, data): - """ - Send a byte stream of data without checking for device readiness. - """ - self.spi.transfer(data) - - def close(self): - """ - Close the device handle - """ - self.spi.close() diff --git a/boards/xtensa/intel_s1000_crb/support/download.py b/boards/xtensa/intel_s1000_crb/support/download.py deleted file mode 100644 index 71599b19198a8..0000000000000 --- a/boards/xtensa/intel_s1000_crb/support/download.py +++ /dev/null @@ -1,133 +0,0 @@ -#!/usr/bin/env python3 -# -# Copyright (c) 2019 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# -# Author: Sathish Kuttan - -# This script is the top level script that an user can invoke to -# download a Zephyr application binary from a Linux host connected -# over SPI to Intel Sue Creek S1000 target during development. - -import os -import sys -import hashlib -import device -import messenger - -sue_creek = device.Device() -msg = messenger.Message() - -def check_arguments(): - """ - Check whether file name is provided. - If not print usage instruction and exit. - """ - if len(sys.argv) != 2: - print('Usage: python3 %s ' % sys.argv[0]) - sys.exit() - return sys.argv[1] - -def calc_firmware_sha(file): - """ - Open firmware image file and calculate file size - Pad file size to a multiple of 64 bytes - Calculate SHA256 hash of the padded contents - """ - with open(file, 'rb') as firmware: - firmware.seek(0, 2) - size = firmware.tell() - - # pad firmware to round upto 64 byte boundary - padding = (size % 64) - if padding != 0: - padding = (64 - padding) - size += padding - - firmware.seek(0, 0) - sha256 = hashlib.sha256() - for block in iter(lambda: firmware.read(4096), b""): - sha256.update(block) - firmware.close() - - if padding != 0: - sha256.update(b'\0' * padding) - print('Firmware (%s): %d bytes, will be padded to %d bytes.' - % (os.path.basename(file), size - padding, size)) - else: - print('Firmware file size: %d bytes.' % size) - print('SHA: ' + sha256.hexdigest()) - return (size, padding, sha256.digest()) - -def setup_device(): - """ - Configure SPI master device - Reset target and send initialization commands - """ - sue_creek.configure_device(spi_mode=3, order='msb', bits=8) - sue_creek.reset_device() - - command = msg.create_memwrite_cmd((0x71d14, 0, 0x71d24, 0, - 0x304628, 0xd, 0x71fd0, 0x3)) - response = sue_creek.send_receive(command) - msg.print_response(response) - -def load_firmware(file, size, padding, sha): - """ - Send command to load firmware - Transfer binary file contents including padding - """ - command = msg.create_loadfw_cmd(size, sha) - response = sue_creek.send_receive(command) - msg.print_response(response) - - with open(file, 'rb') as firmware: - firmware.seek(0, 0) - block_size = msg.get_bulk_message_size() - transferred = 0 - for block in iter(lambda: firmware.read(block_size), b""): - if len(block) < block_size: - block += b'\0' * padding - bulk_msg = msg.create_bulk_message(block) - sue_creek.send_bulk(bulk_msg) - transferred += len(bulk_msg) - sys.stdout.write('\r%d of %d bytes transferred to %s.' - % (transferred, size, sue_creek.name)) - print('') - firmware.close() - - sue_creek.check_device_ready() - - command = msg.create_null_cmd() - response = sue_creek.send_receive(command) - msg.print_response(response) - -def execute_firmware(): - """ - Send command to start execution - """ - command = msg.create_memwrite_cmd((0x71d10, 0, 0x71d20, 0)) - response = sue_creek.send_receive(command) - msg.print_response(response) - - command = msg.create_execfw_cmd() - response = sue_creek.send_receive(command, wait=False) - msg.print_response(response) - -def main(): - """ - Check arguments to ensure binary file is provided. - Calculate SHA of the binary image - Setup the SPI master device and GPIOs on the host - Download Firmware - """ - file = check_arguments() - (size, padding, sha) = calc_firmware_sha(file) - setup_device() - load_firmware(file, size, padding, sha) - execute_firmware() - sue_creek.close() - -if __name__ == '__main__': - main() diff --git a/boards/xtensa/intel_s1000_crb/support/dsp0_gdb.txt b/boards/xtensa/intel_s1000_crb/support/dsp0_gdb.txt deleted file mode 100644 index bf2c4c927b2bc..0000000000000 --- a/boards/xtensa/intel_s1000_crb/support/dsp0_gdb.txt +++ /dev/null @@ -1,32 +0,0 @@ -#Initialization script format -#COMMAND LENGTH DATA -# -#COMMAND: 1 - Scan DR branch -# 2 - Scan IR branch -# 3 - Send TRST -# -#LENGTH: Number of bits to send out (in decimal format). -# -#DATA: Data to send out. A sequence of bytes separated by space. -# The rightmost bit is scanned out first. E.g. (B4 B3 B2 B1 B0) -# -## Examples -# -# Perform TAP Reset: -3 -## all stap disable -2 8 12 -1 6 0 -# Scan out MTAP IDCODE command (0x2) a265013h -## all stap enable -2 8 12 -1 6 01 -# -# -# Scan out (2 cores): -# Send Trax Access IR command to 1st core and bypass to 2nd -#2 10 3 9F -# Write to DOSR register of 1st core (NAR part) -#1 9 1 07 -# Write 32 bits to DOSR register (NDR part) -#1 33 1 98 13 45 ab diff --git a/boards/xtensa/intel_s1000_crb/support/dsp1_gdb.txt b/boards/xtensa/intel_s1000_crb/support/dsp1_gdb.txt deleted file mode 100644 index fccecac20c380..0000000000000 --- a/boards/xtensa/intel_s1000_crb/support/dsp1_gdb.txt +++ /dev/null @@ -1,32 +0,0 @@ -#Initialization script format -#COMMAND LENGTH DATA -# -#COMMAND: 1 - Scan DR branch -# 2 - Scan IR branch -# 3 - Send TRST -# -#LENGTH: Number of bits to send out (in decimal format). -# -#DATA: Data to send out. A sequence of bytes separated by space. -# The rightmost bit is scanned out first. E.g. (B4 B3 B2 B1 B0) -# -## Examples -# -# Perform TAP Reset: -3 -## all stap disable -2 8 12 -1 6 0 -# Scan out MTAP IDCODE command (0x2) a265013h -## all stap enable -2 8 12 -1 6 04 -# -# -# Scan out (2 cores): -# Send Trax Access IR command to 1st core and bypass to 2nd -#2 10 3 9F -# Write to DOSR register of 1st core (NAR part) -#1 9 1 07 -# Write 32 bits to DOSR register (NDR part) -#1 33 1 98 13 45 ab diff --git a/boards/xtensa/intel_s1000_crb/support/load_elf.txt b/boards/xtensa/intel_s1000_crb/support/load_elf.txt deleted file mode 100644 index d1457acd3c56a..0000000000000 --- a/boards/xtensa/intel_s1000_crb/support/load_elf.txt +++ /dev/null @@ -1,17 +0,0 @@ -target remote localhost:20000 - -# make SRAM writable -set *(0x71d10) = 0 -set *(0x71d20) = 0 - -# disable xtensa core power saving -set *(0x71F90) = 0x71 - -# stall/reset second core -set *(0x81C14) = 0x0202 - -set pagination off -set confirm off -file zephyr/zephyr.elf -load zephyr/zephyr.elf -c diff --git a/boards/xtensa/intel_s1000_crb/support/messenger.py b/boards/xtensa/intel_s1000_crb/support/messenger.py deleted file mode 100644 index 9a7033a850f06..0000000000000 --- a/boards/xtensa/intel_s1000_crb/support/messenger.py +++ /dev/null @@ -1,232 +0,0 @@ -#!/usr/bin/env python3 -# -# Copyright (c) 2019 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# -# Author: Sathish Kuttan - -# This file defines a message class that contains functions to create -# commands to the target and to parse responses from the target. - -import bitstruct - -class Message: - """ - Message class containing the methods to create command messages and - parse response messages. - """ - message_id = {1: 'Control'} - cmd_rsp = {2: 'Load Firmware', - 4: 'Mode Select', - 0x10: 'Memory Read', - 0x11: 'Memory Write', - 0x12: 'Memory Block Write', - 0x13: 'Execute', - 0x14: 'Wait', - 0x20: 'Ready'} - tx_data = None - tx_bulk_data = None - tx_index = 0 - cmd_word_fmt = 'u1 u1 u1 u5 u16 u8' - cmd_keys = ['cmd', 'rsvd1', 'rsp', 'msg_id', 'rsvd2', 'cmd_rsp'] - - def __init__(self): - """ - Initialize a byte array of 64 bytes for command messages - Initialize another byte array of 4096 bytes for bulk messages - """ - self.tx_data = bytearray(64) - self.tx_bulk_data = bytearray(4096) - - def init_tx_data(self): - """ - Initialize transmit message buffers to zeros - """ - for index in range(len(self.tx_data)): - self.tx_data[index] = 0 - self.tx_index = 0 - - @staticmethod - def endian_swap(dst, dst_offset, src): - """ - Performs a byte swap of a 32-bit word to change it's endianness - """ - for index in range(0, len(src), 4): - dst[dst_offset + index + 0] = src[index + 3] - dst[dst_offset + index + 1] = src[index + 2] - dst[dst_offset + index + 2] = src[index + 1] - dst[dst_offset + index + 3] = src[index + 0] - - def print_cmd_message(self): - """ - Prints the contents of the command message buffer - """ - for index in range(0, self.tx_index, 4): - offset = index * 8 - word = bitstruct.unpack_from('u32', self.tx_data, offset) - print('Index: %2d Content: 0x%08x' %(index, word[0])) - - def print_response(self, msg, verbose=False): - """ - Parses and prints the contents of the response message - """ - unpacked = bitstruct.unpack_from_dict(self.cmd_word_fmt, - self.cmd_keys, msg) - msg_id = unpacked['msg_id'] - rsp = unpacked['cmd_rsp'] - if msg_id == 0 and rsp == 0: - print('RSP <<< NULL.') - else: - print('RSP <<< %s.' % self.cmd_rsp[rsp]) - if verbose: - count = bitstruct.unpack_from('u32', msg, 4 * 8)[0] - count &= 0x1ff - for index in range(0, 8 + (count * 4), 4): - offset = index * 8 - word = bitstruct.unpack_from('u32', msg, offset) - print('Index: %2d Content: 0x%08x' %(index, word[0])) - - def get_cmd_code(self, cmd): - """ - Looks up the command and returns the numeric code - """ - index = list(self.cmd_rsp.values()).index(cmd) - return list(self.cmd_rsp.keys())[index] - - def print_cmd_code(self, cmd): - """ - Prints the numeric code for the given command - """ - key = self.get_cmd_code(cmd) - print('CMD >>> %s. Command Code: 0x%02x' % (cmd, key)) - - def create_null_cmd(self): - """ - Creates a NULL command - """ - print('CMD >>> NULL.') - for index in range(len(self.tx_data)): - self.tx_data[index] = 0 - self.tx_index = len(self.tx_data) - return self.tx_data - - def create_memwrite_cmd(self, tuple): - """ - Creates a memory write command with memory address and value pairs - """ - cmd = 'Memory Write' - print('CMD >>> %s.' % cmd) - code = self.get_cmd_code(cmd) - self.init_tx_data() - - index = list(self.message_id.values()).index('Control') - msg_id = list(self.message_id.keys())[index] - bitstruct.pack_into_dict(self.cmd_word_fmt, self.cmd_keys, - self.tx_data, 0, {'cmd': 1, 'rsvd1': 0, 'rsp': 0, - 'msg_id': msg_id, 'rsvd2': 0, 'cmd_rsp': code}) - self.tx_index += 4 - bitstruct.pack_into('u32', self.tx_data, self.tx_index * 8, - len(tuple)) - self.tx_index += 4 - for elm in tuple: - bitstruct.pack_into('u32', self.tx_data, self.tx_index * 8, elm) - self.tx_index += 4 - return self.tx_data - - def create_memread_cmd(self, tuple): - """ - Creates a memory read command with memory addresses - """ - cmd = 'Memory Read' - print('CMD >>> %s.' % cmd) - code = self.get_cmd_code(cmd) - self.init_tx_data() - - index = list(self.message_id.values()).index('Control') - msg_id = list(self.message_id.keys())[index] - bitstruct.pack_into_dict(self.cmd_word_fmt, self.cmd_keys, - self.tx_data, 0, {'cmd': 1, 'rsvd1': 0, 'rsp': 0, - 'msg_id': msg_id, 'rsvd2': 0, 'cmd_rsp': code}) - self.tx_index += 4 - bitstruct.pack_into('u32', self.tx_data, self.tx_index * 8, - len(tuple)) - self.tx_index += 4 - for elm in tuple: - bitstruct.pack_into('u32', self.tx_data, self.tx_index * 8, elm) - self.tx_index += 4 - return self.tx_data - - def create_loadfw_cmd(self, size, sha): - """ - Creates a command to load firmware with associated parameters - """ - cmd = 'Load Firmware' - print('CMD >>> %s.' % cmd) - code = self.get_cmd_code(cmd) - - FW_NO_EXEC_FLAG = (1 << 26) - SEL_HP_CLK = (1 << 21) - LD_FW_HEADER_LEN = 3 - - count_flags = FW_NO_EXEC_FLAG | SEL_HP_CLK - count_flags |= (LD_FW_HEADER_LEN + int(len(sha) / 4)) - - self.init_tx_data() - - index = list(self.message_id.values()).index('Control') - msg_id = list(self.message_id.keys())[index] - bitstruct.pack_into_dict(self.cmd_word_fmt, self.cmd_keys, - self.tx_data, 0, {'cmd': 1, 'rsvd1': 0, 'rsp': 0, - 'msg_id': msg_id, 'rsvd2': 0, 'cmd_rsp': code}) - self.tx_index += 4 - bitstruct.pack_into('u32', self.tx_data, self.tx_index * 8, count_flags) - self.tx_index += 4 - bitstruct.pack_into('u32', self.tx_data, self.tx_index * 8, 0xbe000000) - self.tx_index += 4 - bitstruct.pack_into('u32', self.tx_data, self.tx_index * 8, 0) - self.tx_index += 4 - bitstruct.pack_into('u32', self.tx_data, self.tx_index * 8, size) - self.tx_index += 4 - self.endian_swap(self.tx_data, self.tx_index, sha) - self.tx_index += len(sha) - return self.tx_data - - def create_execfw_cmd(self): - """ - Creates a command to execute firmware - """ - cmd = 'Execute' - print('CMD >>> %s.' % cmd) - code = self.get_cmd_code(cmd) - - EXE_FW_HEADER_LEN = 1 - - count = EXE_FW_HEADER_LEN - - self.init_tx_data() - - index = list(self.message_id.values()).index('Control') - msg_id = list(self.message_id.keys())[index] - bitstruct.pack_into_dict(self.cmd_word_fmt, self.cmd_keys, - self.tx_data, 0, {'cmd': 1, 'rsvd1': 0, 'rsp': 0, - 'msg_id': msg_id, 'rsvd2': 0, 'cmd_rsp': code}) - self.tx_index += 4 - bitstruct.pack_into('u32', self.tx_data, self.tx_index * 8, count) - self.tx_index += 4 - bitstruct.pack_into('u32', self.tx_data, self.tx_index * 8, 0xbe000000) - self.tx_index += 4 - return self.tx_data - - def create_bulk_message(self, data): - """ - Copies the input byte stream to the bulk message buffer - """ - self.endian_swap(self.tx_bulk_data, 0, data) - return self.tx_bulk_data[:len(data)] - - def get_bulk_message_size(self): - """ - Returns the size of the bulk message buffer - """ - return len(self.tx_bulk_data) diff --git a/boards/xtensa/intel_s1000_crb/support/topology_all_flyswatter2.xml b/boards/xtensa/intel_s1000_crb/support/topology_all_flyswatter2.xml deleted file mode 100644 index 3504ff9ae9e16..0000000000000 --- a/boards/xtensa/intel_s1000_crb/support/topology_all_flyswatter2.xml +++ /dev/null @@ -1,24 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/boards/xtensa/intel_s1000_crb/support/topology_dsp0_flyswatter2.xml b/boards/xtensa/intel_s1000_crb/support/topology_dsp0_flyswatter2.xml deleted file mode 100644 index 495b99b208733..0000000000000 --- a/boards/xtensa/intel_s1000_crb/support/topology_dsp0_flyswatter2.xml +++ /dev/null @@ -1,21 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - diff --git a/boards/xtensa/intel_s1000_crb/support/topology_dsp1_flyswatter2.xml b/boards/xtensa/intel_s1000_crb/support/topology_dsp1_flyswatter2.xml deleted file mode 100644 index 0dfc3f67bc88e..0000000000000 --- a/boards/xtensa/intel_s1000_crb/support/topology_dsp1_flyswatter2.xml +++ /dev/null @@ -1,21 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - diff --git a/boards/xtensa/xt-sim/Kconfig.board b/boards/xtensa/xt-sim/Kconfig.board index b5730e5cddbf8..d67c68417a92a 100644 --- a/boards/xtensa/xt-sim/Kconfig.board +++ b/boards/xtensa/xt-sim/Kconfig.board @@ -6,6 +6,3 @@ config BOARD_XT_SIM bool "Xtensa Development ISS" depends on SIMULATOR_XTENSA - -config BOARD_XT_SIM_INTEL_S1000 - bool "Xtensa Development ISS" diff --git a/boards/xtensa/xt-sim/doc/index.rst b/boards/xtensa/xt-sim/doc/index.rst index 81279110c178b..0e4a572a69b42 100644 --- a/boards/xtensa/xt-sim/doc/index.rst +++ b/boards/xtensa/xt-sim/doc/index.rst @@ -25,7 +25,6 @@ Hardware The following Xtensa cores are officially supported: -- Intel S1000 - sample_controller System Clock diff --git a/boards/xtensa/xt-sim/xt-sim_intel_s1000_defconfig b/boards/xtensa/xt-sim/xt-sim_intel_s1000_defconfig deleted file mode 100644 index 4079872489cbd..0000000000000 --- a/boards/xtensa/xt-sim/xt-sim_intel_s1000_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_SOC_INTEL_S1000=y -CONFIG_BOARD_XT_SIM_INTEL_S1000=y -CONFIG_CONSOLE=y -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n diff --git a/doc/_scripts/redirects.py b/doc/_scripts/redirects.py index 6257704a12611..cad7605d16a78 100644 --- a/doc/_scripts/redirects.py +++ b/doc/_scripts/redirects.py @@ -137,7 +137,6 @@ ('boards/x86/tinytile/doc/board', 'boards/x86/tinytile/doc/index'), ('boards/x86/up_squared/doc/up_squared', 'boards/x86/up_squared/doc/index'), ('boards/xtensa/esp32/doc/esp32', 'boards/xtensa/esp32/doc/index'), - ('boards/xtensa/intel_s1000_crb/doc/intel_s1000', 'boards/xtensa/intel_s1000_crb/doc/index'), ('boards/xtensa/qemu_xtensa/doc/board', 'boards/xtensa/qemu_xtensa/doc/index'), ('boards/xtensa/xt-sim/doc/xt-sim', 'boards/xtensa/xt-sim/doc/index'), ('contribute/contribute_guidelines', 'contribute/index'), diff --git a/doc/develop/toolchains/cadence_xcc.rst b/doc/develop/toolchains/cadence_xcc.rst index 49661f78896ac..5a2e7cea8d014 100644 --- a/doc/develop/toolchains/cadence_xcc.rst +++ b/doc/develop/toolchains/cadence_xcc.rst @@ -36,7 +36,7 @@ Cadence Tensilica Xtensa C/C++ Compiler (XCC) * Set :envvar:`TOOLCHAIN_VER` to the Xtensa SDK version. #. For example, assuming the SDK is installed in ``/opt/xtensa``, and - using the SDK for application development on ``intel_s1000_crb``, + using the SDK for application development on ``intel_adsp_cavs15``, setup the environment using: .. code-block:: console diff --git a/dts/bindings/pinctrl/intel,s1000-pinmux.yaml b/dts/bindings/pinctrl/intel,s1000-pinmux.yaml deleted file mode 100644 index e3fbdd7a45940..0000000000000 --- a/dts/bindings/pinctrl/intel,s1000-pinmux.yaml +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -description: Intel S1000 pinmux - -compatible: "intel,s1000-pinmux" - -include: base.yaml - -properties: - reg: - required: true - -pinmux-cells: - - pin - - function diff --git a/dts/xtensa/intel/intel_s1000.dtsi b/dts/xtensa/intel/intel_s1000.dtsi deleted file mode 100644 index a9d2553bc942a..0000000000000 --- a/dts/xtensa/intel/intel_s1000.dtsi +++ /dev/null @@ -1,270 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -#include -#include -#include -#include -#include - - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "cdns,tensilica-xtensa-lx6"; - reg = <0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "cdns,tensilica-xtensa-lx6"; - reg = <1>; - }; - }; - - sram0: memory@be000000 { - compatible = "mmio-sram"; - reg = <0xbe000000 DT_SIZE_M(4)>; - }; - - sram1: memory@be800000 { - compatible = "mmio-sram"; - reg = <0xbe800000 DT_SIZE_K(64)>; - }; - - sysclk: system-clock { - compatible = "fixed-clock"; - clock-frequency = <400000000>; - #clock-cells = <0>; - }; - - soc { - core_intc: core_intc@0 { - compatible = "cdns,xtensa-core-intc"; - reg = <0x00 0x400>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - shim: shim@71f00 { - compatible = "intel,cavs-shim"; - reg = <0x71f00 0x100>; - }; - - cavs0: cavs@78800 { - compatible = "intel,cavs-intc"; - reg = <0x78800 0x10>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <6 0 0>; - interrupt-parent = <&core_intc>; - label = "CAVS_0"; - }; - - cavs1: cavs@78810 { - compatible = "intel,cavs-intc"; - reg = <0x78810 0x10>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <0xA 0 0>; - interrupt-parent = <&core_intc>; - label = "CAVS_1"; - }; - - cavs2: cavs@78820 { - compatible = "intel,cavs-intc"; - reg = <0x78820 0x10>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <0XD 0 0>; - interrupt-parent = <&core_intc>; - label = "CAVS_2"; - }; - - cavs3: cavs@78830 { - compatible = "intel,cavs-intc"; - reg = <0x78830 0x10>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <0x10 0 0>; - interrupt-parent = <&core_intc>; - label = "CAVS_3"; - }; - - idc: idc@1200 { - compatible = "intel,cavs-idc"; - label = "CAVS_IDC"; - reg = <0x1200 0x80>; - interrupts = <8 0 0>; - interrupt-parent = <&cavs0>; - }; - - dw_intc: intc@81800 { - compatible = "snps,designware-intc"; - reg = <0x00081800 0x400>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <6 0 0>; - num-irqs = <9>; - interrupt-parent = <&cavs0>; - label = "DW_INTC"; - }; - - gpio0: gpio@80c00 { - compatible = "snps,designware-gpio"; - reg = <0x00080c00 0x400>; - ngpios = <32>; - label = "GPIO"; - interrupts = <3 1 0>; - interrupt-parent = <&dw_intc>; - - gpio-controller; - #gpio-cells = <2>; - }; - - pinmux: pinmux@81c30 { - compatible = "intel,s1000-pinmux"; - reg = <0x00081c30 0xC>; - }; - - uart0: uart@80800 { - compatible = "ns16550"; - reg = <0x80800 0x400>; - label = "UART_0"; - clock-frequency = <38400000>; - interrupts = <2 0 0>; - interrupt-parent = <&dw_intc>; - - - status = "disabled"; - }; - - i2c0: i2c@80400 { - compatible = "snps,designware-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80400 0x400>; - interrupts = <1 0 0>; - interrupt-parent = <&dw_intc>; - label = "I2C_0"; - - status = "disabled"; - }; - - spi0: spi@e000 { - compatible = "snps,designware-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0000E000 0x400>; - clocks = <&sysclk>; - interrupts = <6 0 0>; - interrupt-parent = <&dw_intc>; - label = "SPI_0"; - }; - - dma0: dma@7c000 { - compatible = "snps,designware-dma"; - #dma-cells = <1>; - reg = <0x0007C000 0x1000>; - interrupts = <0x10 0 0>; - interrupt-parent = <&cavs3>; - label = "DMA_0"; - - status = "okay"; - }; - - dma1: dma@7d000 { - compatible = "snps,designware-dma"; - #dma-cells = <1>; - reg = <0x0007D000 0x1000>; - interrupts = <0x00 0 0>; - interrupt-parent = <&cavs1>; - label = "DMA_1"; - - status = "disabled"; - }; - - dma2: dma@7e000 { - compatible = "snps,designware-dma"; - #dma-cells = <1>; - reg = <0x0007E000 0x1000>; - interrupts = <0x00 0 0>; - interrupt-parent = <&cavs2>; - label = "DMA_2"; - - status = "disabled"; - }; - - usb: usb@a0000 { - compatible = "snps,designware-usb"; - reg = <0x000A0000 0x1000>; - interrupts = <0x07 IRQ_TYPE_LOWEST_EDGE_RISING 3>; - interrupt-parent = <&cavs0>; - num-bidir-endpoints = <6>; - label = "USB_0"; - - status = "disabled"; - }; - - i2s1: i2s@77200 { - compatible = "intel,cavs-i2s"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x00077200 0x200 - 0x00078D08 0x008>; - interrupts = <0x01 0 0>; - interrupt-parent = <&cavs3>; - dmas = <&dma0 2 - &dma0 3>; - dma-names = "tx", "rx"; - label = "I2S_1"; - - status = "okay"; - }; - - i2s2: i2s@77400 { - compatible = "intel,cavs-i2s"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x00077400 0x200 - 0x00078D10 0x008>; - interrupts = <0x02 0 0>; - interrupt-parent = <&cavs3>; - dmas = <&dma0 4 - &dma0 5>; - dma-names = "tx", "rx"; - label = "I2S_2"; - - status = "okay"; - }; - - i2s3: i2s@77600 { - compatible = "intel,cavs-i2s"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x00077600 0x200 - 0x00078D18 0x008>; - interrupts = <0x03 0 0>; - interrupt-parent = <&cavs3>; - dmas = <&dma0 6 - &dma0 7>; - dma-names = "tx", "rx"; - label = "I2S_3"; - - status = "okay"; - }; - - gna: gna@e800 { - compatible = "intel,gna"; - reg = <0x0000E800 0x100>; - interrupt-controller; - interrupts = <5 0 0>; - interrupt-parent = <&cavs0>; - label = "GNA0"; - }; - }; -}; diff --git a/soc/xtensa/intel_s1000/CMakeLists.txt b/soc/xtensa/intel_s1000/CMakeLists.txt deleted file mode 100644 index 252f85f618885..0000000000000 --- a/soc/xtensa/intel_s1000/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_library_sources(soc.c) - -if("${ZEPHYR_TOOLCHAIN_VARIANT}" STREQUAL "xcc") -add_subdirectory(xcc) -endif() - -if(CONFIG_SMP) -zephyr_library_sources(soc_mp.c) -endif() diff --git a/soc/xtensa/intel_s1000/Kconfig.defconfig b/soc/xtensa/intel_s1000/Kconfig.defconfig deleted file mode 100644 index 67eeebaf98680..0000000000000 --- a/soc/xtensa/intel_s1000/Kconfig.defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# XTENSA board configuration - -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_INTEL_S1000 - -config SOC - default "intel_s1000" - -config SOC_SERIES - string - default "intel_s1000" - -config SOC_TOOLCHAIN_NAME - string - default "intel_s1000" - -config SPI_DW_FIFO_DEPTH - default 32 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 400000000 if XTENSA_TIMER - default 38400000 if CAVS_TIMER - -if SMP - -config MP_NUM_CPUS - default 2 - -config XTENSA_TIMER - default n - -config CAVS_TIMER - default y - -config IPM - default y - -config IPM_CAVS_IDC - default y if IPM - -config SCHED_IPI_SUPPORTED - default y if IPM_CAVS_IDC - -endif - -endif diff --git a/soc/xtensa/intel_s1000/Kconfig.soc b/soc/xtensa/intel_s1000/Kconfig.soc deleted file mode 100644 index 4fab35bcb003c..0000000000000 --- a/soc/xtensa/intel_s1000/Kconfig.soc +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_INTEL_S1000 - bool "intel_s1000" - select XTENSA - select XTENSA_HAL if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" - select HAS_I2C_DW if I2C - select HAS_SPI_DW if SPI - select ARCH_HAS_THREAD_LOCAL_STORAGE diff --git a/soc/xtensa/intel_s1000/include/_soc_inthandlers.h b/soc/xtensa/intel_s1000/include/_soc_inthandlers.h deleted file mode 100644 index d56db2bf4ca46..0000000000000 --- a/soc/xtensa/intel_s1000/include/_soc_inthandlers.h +++ /dev/null @@ -1,256 +0,0 @@ -/* - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - * - * Functions here are designed to produce efficient code to - * search an Xtensa bitmask of interrupts, inspecting only those bits - * declared to be associated with a given interrupt level. Each - * dispatcher will handle exactly one flagged interrupt, in numerical - * order (low bits first) and will return a mask of that bit that can - * then be cleared by the calling code. Unrecognized bits for the - * level will invoke an error handler. - */ - -#include -#include - -#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 2 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 2 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 2 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 3 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 3 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 3 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 4 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 4 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 4 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 5 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 5 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 5 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 5 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 5 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 7 -#error core-isa.h interrupt level does not match dispatcher! -#endif - -static inline int _xtensa_handle_one_int1(unsigned int mask) -{ - if (mask & 0x3) { - if (mask & (1 << 0)) { - struct _isr_table_entry *e = &_sw_isr_table[0]; - - e->isr(e->arg); - return 1 << 0; - } - if (mask & (1 << 1)) { - struct _isr_table_entry *e = &_sw_isr_table[1]; - - e->isr(e->arg); - return 1 << 1; - } - } else { - if (mask & (1 << 2)) { - struct _isr_table_entry *e = &_sw_isr_table[2]; - - e->isr(e->arg); - return 1 << 2; - } - if (mask & (1 << 3)) { - struct _isr_table_entry *e = &_sw_isr_table[3]; - - e->isr(e->arg); - return 1 << 3; - } - } - return 0; -} - -static inline int _xtensa_handle_one_int2(unsigned int mask) -{ - if (mask & 0x30) { - if (mask & (1 << 4)) { - struct _isr_table_entry *e = &_sw_isr_table[4]; - - e->isr(e->arg); - return 1 << 4; - } - if (mask & (1 << 5)) { - struct _isr_table_entry *e = &_sw_isr_table[5]; - - e->isr(e->arg); - return 1 << 5; - } - } else { - if (mask & (1 << 6)) { - struct _isr_table_entry *e = &_sw_isr_table[6]; - - e->isr(e->arg); - return 1 << 6; - } - if (mask & (1 << 7)) { - struct _isr_table_entry *e = &_sw_isr_table[7]; - - e->isr(e->arg); - return 1 << 7; - } - } - return 0; -} - -static inline int _xtensa_handle_one_int3(unsigned int mask) -{ - if (mask & 0x300) { - if (mask & (1 << 8)) { - struct _isr_table_entry *e = &_sw_isr_table[8]; - - e->isr(e->arg); - return 1 << 8; - } - if (mask & (1 << 9)) { - struct _isr_table_entry *e = &_sw_isr_table[9]; - - e->isr(e->arg); - return 1 << 9; - } - } else { - if (mask & (1 << 10)) { - struct _isr_table_entry *e = &_sw_isr_table[10]; - - e->isr(e->arg); - return 1 << 10; - } - if (mask & (1 << 11)) { - struct _isr_table_entry *e = &_sw_isr_table[11]; - - e->isr(e->arg); - return 1 << 11; - } - } - return 0; -} - -static inline int _xtensa_handle_one_int4(unsigned int mask) -{ - if (mask & (1 << 12)) { - struct _isr_table_entry *e = &_sw_isr_table[12]; - - e->isr(e->arg); - return 1 << 12; - } - if (mask & (1 << 13)) { - struct _isr_table_entry *e = &_sw_isr_table[13]; - - e->isr(e->arg); - return 1 << 13; - } - if (mask & (1 << 14)) { - struct _isr_table_entry *e = &_sw_isr_table[14]; - - e->isr(e->arg); - return 1 << 14; - } - return 0; -} - -static inline int _xtensa_handle_one_int5(unsigned int mask) -{ - if (mask & 0x18000) { - if (mask & (1 << 15)) { - struct _isr_table_entry *e = &_sw_isr_table[15]; - - e->isr(e->arg); - return 1 << 15; - } - if (mask & (1 << 16)) { - struct _isr_table_entry *e = &_sw_isr_table[16]; - - e->isr(e->arg); - return 1 << 16; - } - } else { - if (mask & (1 << 17)) { - struct _isr_table_entry *e = &_sw_isr_table[17]; - - e->isr(e->arg); - return 1 << 17; - } - if (mask & (1 << 18)) { - struct _isr_table_entry *e = &_sw_isr_table[18]; - - e->isr(e->arg); - return 1 << 18; - } - if (mask & (1 << 19)) { - struct _isr_table_entry *e = &_sw_isr_table[19]; - - e->isr(e->arg); - return 1 << 19; - } - } - return 0; -} - -static inline int _xtensa_handle_one_int7(unsigned int mask) -{ - if (mask & (1 << 20)) { - struct _isr_table_entry *e = &_sw_isr_table[20]; - - e->isr(e->arg); - return 1 << 20; - } - return 0; -} - -static inline int _xtensa_handle_one_int0(unsigned int mask) -{ - return 0; -} - -static inline int _xtensa_handle_one_int6(unsigned int mask) -{ - return 0; -} diff --git a/soc/xtensa/intel_s1000/include/cavs-idc.h b/soc/xtensa/intel_s1000/include/cavs-idc.h deleted file mode 100644 index d5abe233f3fb8..0000000000000 --- a/soc/xtensa/intel_s1000/include/cavs-idc.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (c) 2021 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef ZEPHYR_SOC_INTEL_ADSP_CAVS_IDC_H_ -#define ZEPHYR_SOC_INTEL_ADSP_CAVS_IDC_H_ - -/* - * (I)ntra (D)SP (C)ommunication is the facility for sending - * interrupts directly between DSP cores. The interface - * is... somewhat needlessly complicated. - * - * Each core has a set of registers its is supposed to use, but all - * registers seem to behave symmetrically regardless of which CPU does - * the access. - * - * Each core has a "ITC" register associated with each other core in - * the system (including itself). When the high bit becomes 1 in an - * ITC register, an IDC interrupt is latched for the target core. - * Data in other bits is stored but otherwise ignored, it's merely - * data to be transmitted along with the interrupt. - * - * On the target core, there is a "TFC" register for each core that - * reflects the same value written to ITC. In fact experimentally - * these seem to be the same register at different addresses. When - * the high bit of TFC is written with a 1, the value becomes ZERO, - * indicating an acknowledgment of the interrupt. This action can - * also latch an interrupt to send back to the originator if unmasked - * (see below). - * - * (There is also an IETC/TEFC register pair that stores 30 bits of - * data but otherwise has no hardware behavior. This is probably best - * ignored for new protocols, as experimentally it seems to provide no - * performance benefit vs. storing a message in RAM. The cAVS 1.5/1.8 - * ROM boot protocol uses it to store an entry point address, though.) - * - * So you can send a synchronous message from core "src" (where src is - * the PRID of the CPU, equal to arch_curr_cpu()->id in Zephyr) to - * core "dst" with: - * - * IDC[src].core[dst].itc = BIT(31) | message; - * while (IDC[src].core[dst].itc & BIT(31)) {} - * - * And the other side (on cpu "dst", generally in the IDC interrupt - * handler) will read and acknowledge those same values via: - * - * uint32_t my_msg = IDC[dst].core[src].tfc & 0x7fffffff; - * IDC[dst].core[src].tfc = BIT(31); // clear high bit to signal completion - * - * And for clarity, at all times and for all cores and all pairs of src/dst: - * - * IDC[src].core[dst].itc == IDC[dst].core[src].tfc - * - * Finally note the two control registers at the end of each core's - * register block, which store a bitmask of cores that are allowed to - * send that core an interrupt via either ITC (set high "BUSY" bit) or - * TFC (clear high "DONE" bit). This masking is in ADDITION to the - * level 2 bit for IDC in the per-core INTCTRL DSP register AND the - * Xtensa architectural INTENABLE SR. You must enable IDC interrupts - * form core "src" to core "dst" with: - * - * IDC[dst].busy_int |= BIT(src) // Or disable with "&= ~BIT(src)" of course - */ -struct cavs_idc { - struct { - uint32_t tfc; /* (T)arget (F)rom (C)ore */ - uint32_t tefc; /* ^^ + (E)xtension */ - uint32_t itc; /* (I)nitiator (T)o (C)ore */ - uint32_t ietc; /* ^^ + (E)xtension */ - } core[4]; - uint32_t unused0[4]; - uint8_t busy_int; /* bitmask of cores that can IDC via ITC */ - uint8_t done_int; /* bitmask of cores that can IDC via TFC */ - uint8_t unused1; - uint8_t unused2; - uint32_t unused3[11]; -}; - -#define IDC ((volatile struct cavs_idc *)DT_REG_ADDR(DT_NODELABEL(idc))) - -extern void soc_idc_init(void); - -/* cAVS interrupt mask bits. Each core has one of these structs - * indexed in the intctrl[] array. Each external interrupt source - * indexes one bit in one of the state substructs (one each for Xtensa - * level 2-5 interrupts). The "mask" field shows the current masking - * state, with a 1 representing "interrupt disabled". The "status" - * field indicates interrupts that are currently latched and awaiting - * delivery. Write bits to "set" to set the mask bit to 1 and disable - * interrupts. Write a 1 bit to "clear" to force the mask bit to 0 - * and enable them. For example, for core "c": - * - * INTCTRL[c].l2.clear = 0x10; // unmask IDC interrupt - * - * INTCTRL[c].l3.set = 0xffffffff; // Mask all L3 interrupts - * - * Note that this interrupt controller is separate from the Xtensa - * architectural interrupt hardware controlled by the - * INTENABLE/INTERRUPT/INTSET/INTCLEAR special registers on each core - * which much also be configured for interrupts to arrive. Note also - * that some hardware (like IDC, see above) implements a third (!) - * layer of interrupt masking. - */ -struct cavs_intctrl { - struct { - uint32_t set, clear, mask, status; - } l2, l3, l4, l5; -}; - -/* Named interrupt bits in the above registers */ -#define CAVS_L2_HPGPDMA BIT(24) /* HP General Purpose DMA */ -#define CAVS_L2_DWCT1 BIT(23) /* DSP Wall Clock Timer 1 */ -#define CAVS_L2_DWCT0 BIT(22) /* DSP Wall Clock Timer 0 */ -#define CAVS_L2_L2ME BIT(21) /* L2 Memory Error */ -#define CAVS_L2_DTS BIT(20) /* DSP Timestamping */ -#define CAVS_L2_SHA BIT(16) /* SHA-256 */ -#define CAVS_L2_DCLC BIT(15) /* Demand Cache Line Command */ -#define CAVS_L2_IDC BIT(8) /* IDC */ -#define CAVS_L2_HIPC BIT(7) /* Host IPC */ -#define CAVS_L2_MIPC BIT(6) /* CSME IPC */ -#define CAVS_L2_PIPC BIT(5) /* PMC IPC */ -#define CAVS_L2_SIPC BIT(4) /* Sensor Hub IPC */ - -#define CAVS_L3_DSPGCL BIT(31) /* DSP Gateway Code Loader */ -#define CAVS_L3_DSPGHOS(n) BIT(16 + n) /* DSP Gateway Host Output Stream */ -#define CAVS_L3_HPGPDMA BIT(15) /* HP General Purpose DMA */ -#define CAVS_L3_DSPGHIS(n) BIT(n) /* DSP Gateway Host Input Stream */ - -#define CAVS_L4_DSPGLOS(n) BIT(16 + n) /* DSP Gateway Link Output Stream */ -#define CAVS_L4_LPGPGMA BIT(15) /* LP General Purpose DMA */ -#define CAVS_L4_DSPGLIS(n) BIT(n) /* DSP Gateway Link Input Stream */ - -#define CAVS_L5_LPGPDMA BIT(16) /* LP General Purpose DMA */ -#define CAVS_L5_DWCT1 BIT(15) /* DSP Wall CLock Timer 1 */ -#define CAVS_L5_DWCT0 BIT(14) /* DSP Wall Clock Timer 0 */ -#define CAVS_L5_DMIX BIT(13) /* Digital Mixer */ -#define CAVS_L5_ANC BIT(12) /* Active Noise Cancellation */ -#define CAVS_L5_SNDW BIT(11) /* SoundWire */ -#define CAVS_L5_SLIM BIT(10) /* Slimbus */ -#define CAVS_L5_DSPK BIT(9) /* Digital Speaker */ -#define CAVS_L5_DMIC BIT(8) /* Digital Mic */ -#define CAVS_L5_I2S(n) BIT(n) /* I2S */ - -#define CAVS_INTCTRL \ - ((volatile struct cavs_intctrl *)DT_REG_ADDR(DT_NODELABEL(cavs0))) - -#endif /* ZEPHYR_SOC_INTEL_ADSP_CAVS_IDC_H_ */ diff --git a/soc/xtensa/intel_s1000/include/cavs-shim.h b/soc/xtensa/intel_s1000/include/cavs-shim.h deleted file mode 100644 index 982796633a6ad..0000000000000 --- a/soc/xtensa/intel_s1000/include/cavs-shim.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (c) 2021 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_ -#define ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_ - -/* The "shim" block contains most of the general system control - * registers on cAVS platforms. While the base address changes, it - * has remained largely, but not perfectly, compatible between - * versions. - */ - -#ifndef _ASMLANGUAGE -struct cavs_shim { - uint32_t skuid; - uint32_t _unused0[7]; - uint32_t dspwc_lo; - uint32_t dspwc_hi; - uint32_t dspwctcs; - uint32_t _unused1[1]; - uint32_t dspwct0c_lo; - uint32_t dspwct0c_hi; - uint32_t dspwct1c_lo; - uint32_t dspwct1c_hi; - uint32_t _unused2[14]; - uint32_t clkctl; - uint32_t clksts; - uint32_t hspgctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */ - uint32_t lspgctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */ - uint32_t hsrmctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */ - uint32_t lsrmctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */ - uint16_t pwrctl; - uint16_t pwrsts; - uint32_t lpsctl; - uint32_t lpsdmas0; - uint32_t lpsdmas1; - uint32_t spsreq; - uint32_t ldoctl; - uint32_t _unused3[2]; - union { - /* cAVS 1.5 */ - struct { - uint32_t hspgists; - uint32_t lspgists; - uint32_t _unused4[2]; - }; - /* cAVS 1.8+ */ - struct { - uint32_t lpsalhss0; - uint32_t lpsalhss1; - uint32_t lpsalhss2; - uint32_t lpsalhss3; - }; - }; - uint32_t _unused5[4]; - uint32_t l2mecs; - uint32_t l2mpat; - uint32_t _unused6[2]; - uint32_t ltrc; - uint32_t _unused8[3]; - uint32_t dbgo; - uint32_t svcfg; - uint32_t _unused9[2]; -}; - -/* L2 Local Memory control (cAVS 1.8+) */ -struct cavs_l2lm { - uint32_t l2lmcap; - uint32_t l2lmpat; - uint32_t _unused0[2]; - uint32_t hspgctl0; - uint32_t hsrmctl0; - uint32_t hspgists0; - uint32_t _unused1; - uint32_t hspgctl1; - uint32_t hsrmctl1; - uint32_t hspgists1; - uint32_t _unused2[9]; - uint32_t lspgctl; - uint32_t lsrmctl; - uint32_t lspgists; -}; - -#define CAVS_L2LM (*((volatile struct cavs_l2lm *)DT_REG_ADDR(DT_NODELABEL(l2lm)))) - -/* Host memory window control. Not strictly part of the shim block. */ -struct cavs_win { - uint32_t dmwba; - uint32_t dmwlo; -}; - -#define CAVS_WIN ((volatile struct cavs_win *)DT_REG_ADDR(DT_NODELABEL(win))) - -#endif /* _ASMLANGUAGE */ - -#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim)))) - -/* cAVS 1.8+ CLKCTL bits */ -#define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */ -#define CAVS_CLKCTL_RXOSCC BIT(30) /* Request XTAL oscillator */ -#define CAVS_CLKCTL_RLROSCC BIT(29) /* Request LP RING oscillator */ -#define CAVS_CLKCTL_SLIMFDCGB BIT(25) /* Slimbus force dynamic clock gating*/ -#define CAVS_CLKCTL_TCPLCG(x) BIT(16+x) /* Set bit: prevent clock gating on core x */ -#define CAVS_CLKCTL_SLIMCSS BIT(6) /* Slimbus clock (0: XTAL, 1: Audio) */ -#define CAVS_CLKCTL_OCS BIT(2) /* Oscillator clock (0: LP, 1: HP) */ -#define CAVS_CLKCTL_LMCS BIT(1) /* LP mem divisor (0: div/2, 1: div/4) */ -#define CAVS_CLKCTL_HMCS BIT(0) /* HP mem divisor (0: div/2, 1: div/4) */ - -/* cAVS 1.5 had a somewhat different CLKCTL (some fields were the same) */ -#define CAVS15_CLKCTL_RAPLLC BIT(31) -#define CAVS15_CLKCTL_RFROSCC BIT(29) -#define CAVS15_CLKCTL_HPGPDMAFDCGB BIT(28) -#define CAVS15_CLKCTL_LPGPDMAFDCGB(x) BIT(26+x) -#define CAVS15_CLKCTL_SLIMFDCGB BIT(25) -#define CAVS15_CLKCTL_DMICFDCGB BIT(24) -#define CAVS15_CLKCTL_I2SFDCGB(x) BIT(20+x) -#define CAVS15_CLKCTL_I2SEFDCGB(x) BIT(18+x) -#define CAVS15_CLKCTL_DPCS(div) ((((div)-1) & 3) << 8) /* DSP PLL divisor (1/2/4) */ -#define CAVS15_CLKCTL_TCPAPLLS BIT(7) -#define CAVS15_CLKCTL_LDCS BIT(5) -#define CAVS15_CLKCTL_HDCS BIT(4) -#define CAVS15_CLKCTL_LDOCS BIT(3) -#define CAVS15_CLKCTL_HDOCS BIT(2) -#define CAVS15_CLKCTL_LMPCS BIT(1) -#define CAVS15_CLKCTL_HMPCS BIT(0) - -#define SHIM_PWRCTL_TCPDSPPG(x) BIT(x) - -#ifdef SOC_SERIES_INTEL_CAVS_V25 -# define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0 | 3 << 16) -# define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(16) -#else -# define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0) -# define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0) -#endif -#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2) -#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2) - -#define CAVS_DMWBA_ENABLE BIT(0) -#define CAVS_DMWBA_READONLY BIT(1) - -#endif /* ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_ */ diff --git a/soc/xtensa/intel_s1000/iomux.h b/soc/xtensa/intel_s1000/iomux.h deleted file mode 100644 index 8264222a4b8c6..0000000000000 --- a/soc/xtensa/intel_s1000/iomux.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2018 Intel Corporation - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef __INTEL_S1000_IOMUX_H -#define __INTEL_S1000_IOMUX_H - -/* - * +----------------------+-------------------------------------------------+ - * | Table of Possible I/O MUX settings | - * +----------------------+-------------------------------------------------+ - * | Pin group | FUNC_A (Default) | FUNC_B (Available Alternate) | - * +----------------------+-------------------------------------------------+ - * | PIN_GROUP(EM_DQ) | EM_DQ | MST_DQ | - * | PIN_GROUP(GPIO_PWM0) | GPIO | PWM | - * | PIN_GROUP(GPIO_PWM1) | GPIO | PWM | - * | PIN_GROUP(GPIO_PWM2) | GPIO | PWM | - * | PIN_GROUP(GPIO_PWM3) | GPIO | PWM | - * | PIN_GROUP(GPIO_PWM4) | GPIO | PWM | - * | PIN_GROUP(GPIO_PWM5) | GPIO | PWM | - * | PIN_GROUP(GPIO_PWM6) | GPIO | PWM | - * | PIN_GROUP(GPIO_PWM7) | GPIO | PWM | - * | PIN_GROUP(HOST_IRQ) | HOST_IRQ | GPIO14 | - * | PIN_GROUP(HOST_WAKE) | HOST_WAKE | GPIO13 | - * | PIN_GROUP(I2S0) | I2S | PDM | - * | PIN_GROUP(I2S2) | I2S | GPIO | - * | PIN_GROUP(I2S3) | I2S | GPIO | - * | PIN_GROUP(MST_SS1) | MST_SS1 | GPIO25 | - * | PIN_GROUP(PDM_0_1) | PDM_0_1 | GPIO | - * | PIN_GROUP(UART) | UART | GPIO | - * | PIN_GROUP(I2C) | I2C0 | I2C1 | - * +----------------------+-------------------------------------------------+ - */ - -#define PIN_GROUP(group) IOMUX_PINGROUP_ ## group - -/* - * IO Selector is a bit encoding of the mux control register and the - * bits selecting the mux in the mux control register - */ -#define IO_SEL(iomux, lsb, msb) ((iomux) | ((lsb) << 8) | ((msb) << 16)) -#define IOMUX_INDEX(pingroup) ((pingroup) & BIT_MASK(8)) -#define IOMUX_LSB(pingroup) (((pingroup) >> 8) & BIT_MASK(8)) -#define IOMUX_MSB(pingroup) (((pingroup) >> 16) & BIT_MASK(8)) - -/* PSRAM DQ/WAIT or SPI Master DQ/DQS */ -#define IOMUX_PINGROUP_EM_DQ IO_SEL(0, 25, 25) - -/* GPIO or PWM */ -#define IOMUX_PINGROUP_GPIO_PWM0 IO_SEL(1, 0, 1) -#define IOMUX_PINGROUP_GPIO_PWM1 IO_SEL(1, 2, 3) -#define IOMUX_PINGROUP_GPIO_PWM2 IO_SEL(1, 4, 5) -#define IOMUX_PINGROUP_GPIO_PWM3 IO_SEL(1, 6, 7) -#define IOMUX_PINGROUP_GPIO_PWM4 IO_SEL(1, 8, 9) -#define IOMUX_PINGROUP_GPIO_PWM5 IO_SEL(1, 10, 11) -#define IOMUX_PINGROUP_GPIO_PWM6 IO_SEL(1, 12, 13) -#define IOMUX_PINGROUP_GPIO_PWM7 IO_SEL(1, 14, 15) - - -/* HOST_IRQ or GPIO14 */ -#define IOMUX_PINGROUP_HOST_IRQ IO_SEL(0, 1, 1) - -/* HOST_WAKE or GPIO13 */ -#define IOMUX_PINGROUP_HOST_WAKE IO_SEL(0, 0, 0) - -/* I2S0 or PDM2/3 */ -#define IOMUX_PINGROUP_I2S0 IO_SEL(0, 8, 8) - -/* I2S2 or GPIO */ -#define IOMUX_PINGROUP_I2S2 IO_SEL(0, 9, 9) -/* I2S3 or GPIO */ -#define IOMUX_PINGROUP_I2S3 IO_SEL(0, 10, 10) - -/* SPI Master SS #1 MST_SS1 or GPIO 25 */ -#define IOMUX_PINGROUP_MST_SS1 IO_SEL(0, 26, 26) - -/* PDM0/1 or GPIO */ -#define IOMUX_PINGROUP_PDM_0_1 IO_SEL(0, 11, 11) - -/* UART CTS/RTS or GPIO */ -#define IOMUX_PINGROUP_UART IO_SEL(0, 16, 16) - -/* I2C0 or I2C1 */ -#define IOMUX_PINGROUP_I2C IO_SEL(2, 0, 0) - -#endif /* __INTEL_S1000_IOMUX_H */ diff --git a/soc/xtensa/intel_s1000/linker.ld b/soc/xtensa/intel_s1000/linker.ld deleted file mode 100644 index 0868d9b109cc6..0000000000000 --- a/soc/xtensa/intel_s1000/linker.ld +++ /dev/null @@ -1,528 +0,0 @@ -/* - * Copyright (c) 2019 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - * Linker script for the intel_s1000_crb platform - */ - -OUTPUT_ARCH(xtensa) - -#include -#include "memory.h" -#include - -#include -#include - -#include - -#define RAMABLE_REGION ram :ram_phdr -#define ROMABLE_REGION ram :ram_phdr -#define LPRAM_REGION lpram - -MEMORY -{ - vector_reset_text : - org = XCHAL_RESET_VECTOR0_PADDR_SRAM, - len = MEM_RESET_TEXT_SIZE - vector_reset_lit : - org = XCHAL_RESET_VECTOR0_PADDR_SRAM + MEM_RESET_TEXT_SIZE, - len = MEM_RESET_LIT_SIZE - vector_memory_lit : - org = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE, - len = MEM_ERROR_LIT_SIZE - vector_memory_text : - org = XCHAL_MEMERROR_VECTOR_PADDR, - len = MEM_ERROR_TEXT_SIZE - vector_base_text : - org = XCHAL_VECBASE_RESET_PADDR_SRAM, - len = MEM_VECBASE_LIT_SIZE - vector_int2_lit : - org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, - len = MEM_VECT_LIT_SIZE - vector_int2_text : - org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM, - len = MEM_VECT_TEXT_SIZE - vector_int3_lit : - org = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, - len = MEM_VECT_LIT_SIZE - vector_int3_text : - org = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM, - len = MEM_VECT_TEXT_SIZE - vector_int4_lit : - org = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, - len = MEM_VECT_LIT_SIZE - vector_int4_text : - org = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM, - len = MEM_VECT_TEXT_SIZE - vector_int5_lit : - org = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, - len = MEM_VECT_LIT_SIZE - vector_int5_text : - org = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM, - len = MEM_VECT_TEXT_SIZE - vector_int6_lit : - org = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, - len = MEM_VECT_LIT_SIZE - vector_int6_text : - org = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM, - len = MEM_VECT_TEXT_SIZE - vector_int7_lit : - org = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, - len = MEM_VECT_LIT_SIZE - vector_int7_text : - org = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM, - len = MEM_VECT_TEXT_SIZE - vector_kernel_lit : - org = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, - len = MEM_VECT_LIT_SIZE - vector_kernel_text : - org = XCHAL_KERNEL_VECTOR_PADDR_SRAM, - len = MEM_VECT_TEXT_SIZE - vector_user_lit : - org = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, - len = MEM_VECT_LIT_SIZE - vector_user_text : - org = XCHAL_USER_VECTOR_PADDR_SRAM, - len = MEM_VECT_TEXT_SIZE - vector_double_lit : - org = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, - len = MEM_VECT_LIT_SIZE - vector_double_text : - org = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM, - len = MEM_VECT_TEXT_SIZE - ram : - org = RAM_BASE, - len = RAM_SIZE -#ifdef CONFIG_GEN_ISR_TABLES - IDT_LIST : - org = IDT_BASE, - len = IDT_SIZE -#endif - lpram : - org = LPRAM_BASE, - len = LPRAM_SIZE -} - -PHDRS -{ - vector_reset_text_phdr PT_LOAD; - vector_reset_lit_phdr PT_LOAD; - vector_memory_lit_phdr PT_LOAD; - vector_memory_text_phdr PT_LOAD; - vector_base_text_phdr PT_LOAD; - vector_int2_lit_phdr PT_LOAD; - vector_int2_text_phdr PT_LOAD; - vector_int3_lit_phdr PT_LOAD; - vector_int3_text_phdr PT_LOAD; - vector_int4_lit_phdr PT_LOAD; - vector_int4_text_phdr PT_LOAD; - vector_int5_lit_phdr PT_LOAD; - vector_int5_text_phdr PT_LOAD; - vector_int6_lit_phdr PT_LOAD; - vector_int6_text_phdr PT_LOAD; - vector_int7_lit_phdr PT_LOAD; - vector_int7_text_phdr PT_LOAD; - vector_kernel_lit_phdr PT_LOAD; - vector_kernel_text_phdr PT_LOAD; - vector_user_lit_phdr PT_LOAD; - vector_user_text_phdr PT_LOAD; - vector_double_lit_phdr PT_LOAD; - vector_double_text_phdr PT_LOAD; - ram_phdr PT_LOAD; -} -_rom_store_table = 0; -PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM); - -PROVIDE(__memctl_default = 0xFFFFFF00); -PROVIDE(_MemErrorHandler = 0xFFFFFF00); - -ENTRY(CONFIG_KERNEL_ENTRY) - -/* Various memory-map dependent cache attribute settings: */ -_memmap_cacheattr_wb_base = 0x44024000; -_memmap_cacheattr_wt_base = 0x11021000; -_memmap_cacheattr_bp_base = 0x22022000; -_memmap_cacheattr_unused_mask = 0x00F00FFF; -_memmap_cacheattr_wb_trapnull = 0x4422422F; -_memmap_cacheattr_wba_trapnull = 0x4422422F; -_memmap_cacheattr_wbna_trapnull = 0x25222222; -_memmap_cacheattr_wt_trapnull = 0x1122122F; -_memmap_cacheattr_bp_trapnull = 0x2222222F; -_memmap_cacheattr_wb_strict = 0x44F24FFF; -_memmap_cacheattr_wt_strict = 0x11F21FFF; -_memmap_cacheattr_bp_strict = 0x22F22FFF; -_memmap_cacheattr_wb_allvalid = 0x44224222; -_memmap_cacheattr_wt_allvalid = 0x11221222; -_memmap_cacheattr_bp_allvalid = 0x22222222; - -/* - * Cache attributes for memory addresses: - * (Each 4 bits correspond to 512MB of memory) - * - * 0x00000000 - 0x1FFFFFFF (bit 0 - 3) : Bypass cache - * (region for hardware registers) - * 0x20000000 - 0x3FFFFFFF (bit 4 - 7) : No access - * 0x40000000 - 0x5FFFFFFF (bit 8 - 11) : No access - * 0x60000000 - 0x7FFFFFFF (bit 12 - 15) : No access - * 0x80000000 - 0x9FFFFFFF (bit 16 - 19) : Bypass cache - * 0xA0000000 - 0xBFFFFFFF (bit 20 - 23) : Cached, write-through - * 0xC0000000 - 0xDFFFFFFF (bit 24 - 27) : Bypass cache - * 0xE0000000 - 0xFFFFFFFF (bit 28 - 31) : Cached, write-through - * - * Note that this is both for instruction and data caches, - * as cacheattr_set macro sets them both to the same set of - * attributes. - */ -#ifndef CONFIG_SMP -_memmap_cacheattr_intel_s1000 = 0x1212fff2; -#else -/* - * Since there is no cache coherence between cores, - * set the data section (0xA0000000 - 0xBFFFFFFF) to be - * non-cacheable, for now. Until we have proper support - * to manipulate cache lines. - */ -_memmap_cacheattr_intel_s1000 = 0x1222fff2; -#endif - -PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_s1000); -SECTIONS -{ - -#include - - .ResetVector.text : ALIGN(4) - { - . = CONFIG_ROM_START_OFFSET; - _ResetVector_text_start = ABSOLUTE(.); - KEEP (*(.ResetVector.text)) - _ResetVector_text_end = ABSOLUTE(.); - } >vector_reset_text :vector_reset_text_phdr - .ResetVector.literal : ALIGN(4) - { - _ResetVector_literal_start = ABSOLUTE(.); - *(.ResetVector.literal) - _ResetVector_literal_end = ABSOLUTE(.); - } >vector_reset_lit :vector_reset_lit_phdr - .MemoryExceptionVector.literal : ALIGN(4) - { - _MemoryExceptionVector_literal_start = ABSOLUTE(.); - KEEP (*(.MemoryExceptionVector.literal)) - _MemoryExceptionVector_literal_end = ABSOLUTE(.); - } >vector_memory_lit :vector_memory_lit_phdr - .MemoryExceptionVector.text : ALIGN(4) - { - _MemoryExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.MemoryExceptionVector.text)) - _MemoryExceptionVector_text_end = ABSOLUTE(.); - } >vector_memory_text :vector_memory_text_phdr - .WindowVectors.text : ALIGN(4) - { - _WindowVectors_text_start = ABSOLUTE(.); - KEEP (*(.WindowVectors.text)) - _WindowVectors_text_end = ABSOLUTE(.); - } >vector_base_text :vector_base_text_phdr - .Level2InterruptVector.literal : ALIGN(4) - { - _Level2InterruptVector_literal_start = ABSOLUTE(.); - *(.Level2InterruptVector.literal) - _Level2InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int2_lit :vector_int2_lit_phdr - .Level2InterruptVector.text : ALIGN(4) - { - _Level2InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level2InterruptVector.text)) - _Level2InterruptVector_text_end = ABSOLUTE(.); - } >vector_int2_text :vector_int2_text_phdr - .Level3InterruptVector.literal : ALIGN(4) - { - _Level3InterruptVector_literal_start = ABSOLUTE(.); - *(.Level3InterruptVector.literal) - _Level3InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int3_lit :vector_int3_lit_phdr - .Level3InterruptVector.text : ALIGN(4) - { - _Level3InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level3InterruptVector.text)) - _Level3InterruptVector_text_end = ABSOLUTE(.); - } >vector_int3_text :vector_int3_text_phdr - .Level4InterruptVector.literal : ALIGN(4) - { - _Level4InterruptVector_literal_start = ABSOLUTE(.); - *(.Level4InterruptVector.literal) - _Level4InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int4_lit :vector_int4_lit_phdr - .Level4InterruptVector.text : ALIGN(4) - { - _Level4InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level4InterruptVector.text)) - _Level4InterruptVector_text_end = ABSOLUTE(.); - } >vector_int4_text :vector_int4_text_phdr - .Level5InterruptVector.literal : ALIGN(4) - { - _Level5InterruptVector_literal_start = ABSOLUTE(.); - *(.Level5InterruptVector.literal) - _Level5InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int5_lit :vector_int5_lit_phdr - .Level5InterruptVector.text : ALIGN(4) - { - _Level5InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level5InterruptVector.text)) - _Level5InterruptVector_text_end = ABSOLUTE(.); - } >vector_int5_text :vector_int5_text_phdr - .DebugExceptionVector.literal : ALIGN(4) - { - _DebugExceptionVector_literal_start = ABSOLUTE(.); - *(.DebugExceptionVector.literal) - _DebugExceptionVector_literal_end = ABSOLUTE(.); - } >vector_int6_lit :vector_int6_lit_phdr - .DebugExceptionVector.text : ALIGN(4) - { - _DebugExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DebugExceptionVector.text)) - _DebugExceptionVector_text_end = ABSOLUTE(.); - } >vector_int6_text :vector_int6_text_phdr - .NMIExceptionVector.literal : ALIGN(4) - { - _NMIExceptionVector_literal_start = ABSOLUTE(.); - *(.NMIExceptionVector.literal) - _NMIExceptionVector_literal_end = ABSOLUTE(.); - } >vector_int7_lit :vector_int7_lit_phdr - .NMIExceptionVector.text : ALIGN(4) - { - _NMIExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.NMIExceptionVector.text)) - _NMIExceptionVector_text_end = ABSOLUTE(.); - } >vector_int7_text :vector_int7_text_phdr - .KernelExceptionVector.literal : ALIGN(4) - { - _KernelExceptionVector_literal_start = ABSOLUTE(.); - *(.KernelExceptionVector.literal) - _KernelExceptionVector_literal_end = ABSOLUTE(.); - } >vector_kernel_lit :vector_kernel_lit_phdr - .KernelExceptionVector.text : ALIGN(4) - { - _KernelExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.KernelExceptionVector.text)) - _KernelExceptionVector_text_end = ABSOLUTE(.); - } >vector_kernel_text :vector_kernel_text_phdr - .UserExceptionVector.literal : ALIGN(4) - { - _UserExceptionVector_literal_start = ABSOLUTE(.); - *(.UserExceptionVector.literal) - _UserExceptionVector_literal_end = ABSOLUTE(.); - } >vector_user_lit :vector_user_lit_phdr - .UserExceptionVector.text : ALIGN(4) - { - _UserExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.UserExceptionVector.text)) - _UserExceptionVector_text_end = ABSOLUTE(.); - } >vector_user_text :vector_user_text_phdr - .DoubleExceptionVector.literal : ALIGN(4) - { - _DoubleExceptionVector_literal_start = ABSOLUTE(.); - *(.DoubleExceptionVector.literal) - _DoubleExceptionVector_literal_end = ABSOLUTE(.); - } >vector_double_lit :vector_double_lit_phdr - .DoubleExceptionVector.text : ALIGN(4) - { - _DoubleExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DoubleExceptionVector.text)) - _DoubleExceptionVector_text_end = ABSOLUTE(.); - } >vector_double_text :vector_double_text_phdr - - .text : ALIGN(4) - { - _stext = .; - _text_start = ABSOLUTE(.); - *(.entry.text) - *(.init.literal) - *(.iram0.text) - KEEP(*(.init)) - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.fini.literal) - KEEP(*(.fini)) - *(.gnu.version) - _text_end = ABSOLUTE(.); - _etext = .; - } >ram :ram_phdr -#include -#include - - .noinit : ALIGN(4) - { - *(.noinit) - *(.noinit.*) - } >ram :ram_phdr - .rodata : ALIGN(4) - { - _rodata_start = ABSOLUTE(.); - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - *(.rodata1) - - . = ALIGN(4); - #include - - __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); - KEEP (*(.xt_except_table)) - KEEP (*(.gcc_except_table .gcc_except_table.*)) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - KEEP (*(.eh_frame)) - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); 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- _bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (8); - _bss_end = ABSOLUTE(.); - } >ram :ram_phdr - - /* stack */ - _end = ALIGN(8); - PROVIDE(end = ALIGN(8)); - __stack = L2_SRAM_BASE + L2_SRAM_SIZE; - /* dma buffers */ - .lpbuf (NOLOAD): ALIGN(4) - { - _dma_buf_start = ABSOLUTE(.); - *(.dma_buffers) - _dma_buf_end = ABSOLUTE(.); - } >LPRAM_REGION - _heap_sentry = L2_SRAM_BASE + L2_SRAM_SIZE; - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - .debug_ranges 0 : { *(.debug_ranges) } - .xtensa.info 0 : { *(.xtensa.info) } - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .xt.profile_range 0 : - { - KEEP (*(.xt.profile_range)) - KEEP (*(.gnu.linkonce.profile_range.*)) - } - .xt.profile_ranges 0 : - { - KEEP (*(.xt.profile_ranges)) - KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) - } - .xt.profile_files 0 : - { - KEEP (*(.xt.profile_files)) - KEEP (*(.gnu.linkonce.xt.profile_files.*)) - } -#ifdef CONFIG_GEN_ISR_TABLES -#include -#endif -} diff --git a/soc/xtensa/intel_s1000/memory.h b/soc/xtensa/intel_s1000/memory.h deleted file mode 100644 index 7ee294ce7e3e3..0000000000000 --- a/soc/xtensa/intel_s1000/memory.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2019 Intel Corporation - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef __INC_MEMORY_H -#define __INC_MEMORY_H - - -/* L2 HP SRAM */ -#define L2_VECTOR_SIZE 0x1000 - -#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0))) -#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0))) - -#ifdef CONFIG_BOOTLOADER_MCUBOOT -#define SRAM_BASE (L2_SRAM_BASE + CONFIG_BOOTLOADER_SRAM_SIZE * 1K) -#define SRAM_SIZE (L2_SRAM_SIZE - CONFIG_BOOTLOADER_SRAM_SIZE * 1K) -#else -#define SRAM_BASE (L2_SRAM_BASE) -#define SRAM_SIZE (L2_SRAM_SIZE) -#endif - -/* The reset vector address in SRAM and its size */ -#define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE -#define MEM_RESET_TEXT_SIZE 0x268 -#define MEM_RESET_LIT_SIZE 0x8 - -/* This is the base address of all the vectors defined in SRAM */ -#define XCHAL_VECBASE_RESET_PADDR_SRAM (SRAM_BASE + 0x400) -#define MEM_VECBASE_LIT_SIZE 0x178 - -/* The addresses of the vectors in SRAM. - * Only the memerror vector continues to point to its ROM address. - */ -#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM (SRAM_BASE + 0x580) -#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM (SRAM_BASE + 0x5C0) -#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM (SRAM_BASE + 0x600) -#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM (SRAM_BASE + 0x640) -#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM (SRAM_BASE + 0x680) -#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM (SRAM_BASE + 0x6C0) -#define XCHAL_KERNEL_VECTOR_PADDR_SRAM (SRAM_BASE + 0x700) -#define XCHAL_USER_VECTOR_PADDR_SRAM (SRAM_BASE + 0x740) -#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM (SRAM_BASE + 0x7C0) - -/* Vector and literal sizes */ -#define MEM_VECT_LIT_SIZE 0x8 -#define MEM_VECT_TEXT_SIZE 0x38 -#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\ - MEM_VECT_LIT_SIZE) - -#define MEM_ERROR_TEXT_SIZE 0x180 -#define MEM_ERROR_LIT_SIZE 0x8 - -/* text and data share the same L2 HP SRAM on Intel S1000. - * So, they lie next to each other. - */ -#define RAM_BASE (SRAM_BASE + L2_VECTOR_SIZE) -#define RAM_SIZE (SRAM_SIZE - L2_VECTOR_SIZE) - -/* Location for the intList section which is later used to construct the - * Interrupt Descriptor Table (IDT). This is a bogus address as this - * section will be stripped off in the final image. - */ -#define IDT_BASE (RAM_BASE + RAM_SIZE) - -/* size of the Interrupt Descriptor Table (IDT) */ -#define IDT_SIZE 0x2000 - -/* low power ram where DMA buffers are typically placed */ -#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) -#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) - -/* Boot vector residing in LP-SRAM for core #1 */ -#define LPSRAM_BOOT_VECTOR_ADDR (LPRAM_BASE + 0x08) - -#define IPC_DSP_SIZE 0x00000080 -#define IPC_DSP_BASE(x) (0x00001200 + x * IPC_DSP_SIZE) - -#endif /* __INC_MEMORY_H */ diff --git a/soc/xtensa/intel_s1000/soc.c b/soc/xtensa/intel_s1000/soc.c deleted file mode 100644 index b7dd8725326fd..0000000000000 --- a/soc/xtensa/intel_s1000/soc.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - * Copyright (c) 2019 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include - -#include "soc.h" - -#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL -#include -LOG_MODULE_REGISTER(soc); - -static uint32_t ref_clk_freq; - -#define CAVS_INTC_NODE(n) DT_INST(n, intel_cavs_intc) - -void z_soc_irq_enable(uint32_t irq) -{ - const struct device *dev_cavs, *dev_ictl; - - switch (XTENSA_IRQ_NUMBER(irq)) { - case DT_IRQN(CAVS_INTC_NODE(0)): - dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(0))); - break; - case DT_IRQN(CAVS_INTC_NODE(1)): - dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(1))); - break; - case DT_IRQN(CAVS_INTC_NODE(2)): - dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(2))); - break; - case DT_IRQN(CAVS_INTC_NODE(3)): - dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(3))); - break; - default: - /* regular interrupt */ - z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq)); - return; - } - - if (!dev_cavs) { - LOG_DBG("board: CAVS device binding failed"); - return; - } - - /* If the control comes here it means the specified interrupt - * is in either CAVS interrupt logic or DW interrupt controller - */ - z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq)); - - switch (CAVS_IRQ_NUMBER(irq)) { - case DW_ICTL_IRQ_CAVS_OFFSET: - dev_ictl = device_get_binding(DT_LABEL(DT_INST(0, snps_designware_intc))); - break; - default: - /* The source of the interrupt is in CAVS interrupt logic */ - irq_enable_next_level(dev_cavs, CAVS_IRQ_NUMBER(irq)); - return; - } - - if (!dev_ictl) { - LOG_DBG("board: DW intr_control device binding failed"); - return; - } - - /* If the control comes here it means the specified interrupt - * is in DW interrupt controller - */ - irq_enable_next_level(dev_cavs, CAVS_IRQ_NUMBER(irq)); - - /* Manipulate the relevant bit in the interrupt controller - * register as needed - */ - irq_enable_next_level(dev_ictl, INTR_CNTL_IRQ_NUM(irq)); -} - -void z_soc_irq_disable(uint32_t irq) -{ - const struct device *dev_cavs, *dev_ictl; - - switch (XTENSA_IRQ_NUMBER(irq)) { - case DT_IRQN(CAVS_INTC_NODE(0)): - dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(0))); - break; - case DT_IRQN(CAVS_INTC_NODE(1)): - dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(1))); - break; - case DT_IRQN(CAVS_INTC_NODE(2)): - dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(2))); - break; - case DT_IRQN(CAVS_INTC_NODE(3)): - dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(3))); - break; - default: - /* regular interrupt */ - z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq)); - return; - } - - if (!dev_cavs) { - LOG_DBG("board: CAVS device binding failed"); - return; - } - - /* If the control comes here it means the specified interrupt - * is in either CAVS interrupt logic or DW interrupt controller - */ - - switch (CAVS_IRQ_NUMBER(irq)) { - case DW_ICTL_IRQ_CAVS_OFFSET: - dev_ictl = device_get_binding(DT_LABEL(DT_INST(0, snps_designware_intc))); - break; - default: - /* The source of the interrupt is in CAVS interrupt logic */ - irq_disable_next_level(dev_cavs, CAVS_IRQ_NUMBER(irq)); - - /* Disable the parent IRQ if all children are disabled */ - if (!irq_is_enabled_next_level(dev_cavs)) { - z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq)); - } - return; - } - - if (!dev_ictl) { - LOG_DBG("board: DW intr_control device binding failed"); - return; - } - - /* If the control comes here it means the specified interrupt - * is in DW interrupt controller. - * Manipulate the relevant bit in the interrupt controller - * register as needed - */ - irq_disable_next_level(dev_ictl, INTR_CNTL_IRQ_NUM(irq)); - - /* Disable the parent IRQ if all children are disabled */ - if (!irq_is_enabled_next_level(dev_ictl)) { - irq_disable_next_level(dev_cavs, CAVS_IRQ_NUMBER(irq)); - - if (!irq_is_enabled_next_level(dev_cavs)) { - z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq)); - } - } -} - -int z_soc_irq_is_enabled(unsigned int irq) -{ - const struct device *dev_cavs, *dev_ictl; - int ret = -EINVAL; - - switch (XTENSA_IRQ_NUMBER(irq)) { - case DT_IRQN(CAVS_INTC_NODE(0)): - dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(0))); - break; - case DT_IRQN(CAVS_INTC_NODE(1)): - dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(1))); - break; - case DT_IRQN(CAVS_INTC_NODE(2)): - dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(2))); - break; - case DT_IRQN(CAVS_INTC_NODE(3)): - dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(3))); - break; - default: - /* regular interrupt */ - ret = z_xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq)); - goto out; - } - - if (!dev_cavs) { - LOG_DBG("board: CAVS device binding failed"); - ret = -ENODEV; - goto out; - } - - switch (CAVS_IRQ_NUMBER(irq)) { - case DW_ICTL_IRQ_CAVS_OFFSET: - dev_ictl = device_get_binding(DT_LABEL(DT_INST(0, snps_designware_intc))); - break; - default: - /* The source of the interrupt is in CAVS interrupt logic */ - ret = irq_line_is_enabled_next_level(dev_cavs, - CAVS_IRQ_NUMBER(irq)); - goto out; - } - - if (!dev_ictl) { - LOG_DBG("board: DW intr_control device binding failed"); - ret = -ENODEV; - goto out; - } - - ret = irq_line_is_enabled_next_level(dev_ictl, INTR_CNTL_IRQ_NUM(irq)); - -out: - return ret; -} - -static inline void soc_set_resource_ownership(void) -{ - volatile struct soc_resource_alloc_regs *regs = - (volatile struct soc_resource_alloc_regs *) - SOC_RESOURCE_ALLOC_REG_BASE; - int index; - - - /* set ownership of DMA controllers and channels */ - for (index = 0; index < SOC_NUM_LPGPDMAC; index++) { - regs->lpgpdmacxo[index] = SOC_LPGPDMAC_OWNER_DSP; - } - - /* set ownership of I2S and DMIC controllers */ - regs->dspiopo = SOC_DSPIOP_I2S_OWNSEL_DSP | - SOC_DSPIOP_DMIC_OWNSEL_DSP; - - /* set ownership of timestamp and M/N dividers */ - regs->geno = SOC_GENO_TIMESTAMP_OWNER_DSP | - SOC_GENO_MNDIV_OWNER_DSP; -} - -uint32_t soc_get_ref_clk_freq(void) -{ - return ref_clk_freq; -} - -static inline void soc_set_audio_mclk(void) -{ -#if (CONFIG_AUDIO) - int mclk; - volatile struct soc_mclk_control_regs *mclk_regs = - (volatile struct soc_mclk_control_regs *)SOC_MCLK_DIV_CTRL_BASE; - - for (mclk = 0; mclk < SOC_NUM_MCLK_OUTPUTS; mclk++) { - /* - * set divider to bypass mode which makes MCLK output frequency - * to be the same as referece clock frequency - */ - mclk_regs->mdivxr[mclk] = SOC_MDIVXR_SET_DIVIDER_BYPASS; - mclk_regs->mdivctrl |= SOC_MDIVCTRL_MCLK_OUT_EN(mclk); - } -#endif -} - -static inline void soc_set_dmic_power(void) -{ -#if (CONFIG_AUDIO_INTEL_DMIC) - volatile struct soc_dmic_shim_regs *dmic_shim_regs = - (volatile struct soc_dmic_shim_regs *)SOC_DMIC_SHIM_REG_BASE; - - /* enable power */ - dmic_shim_regs->dmiclctl |= SOC_DMIC_SHIM_DMICLCTL_SPA; - - while ((dmic_shim_regs->dmiclctl & SOC_DMIC_SHIM_DMICLCTL_CPA) == 0U) { - /* wait for power status */ - } -#endif -} - -static inline void soc_set_gna_power(void) -{ -#if (CONFIG_INTEL_GNA) - volatile struct soc_global_regs *regs = - (volatile struct soc_global_regs *)SOC_S1000_GLB_CTRL_BASE; - - /* power on GNA block */ - regs->gna_power_control |= SOC_GNA_POWER_CONTROL_SPA; - while ((regs->gna_power_control & SOC_GNA_POWER_CONTROL_CPA) == 0U) { - /* wait for power status */ - } - - /* enable clock for GNA block */ - regs->gna_power_control |= SOC_GNA_POWER_CONTROL_CLK_EN; -#endif -} - -static inline void soc_set_power_and_clock(void) -{ - volatile struct soc_dsp_shim_regs *dsp_shim_regs = - (volatile struct soc_dsp_shim_regs *)SOC_DSP_SHIM_REG_BASE; - - dsp_shim_regs->clkctl |= SOC_CLKCTL_REQ_FAST_CLK | - SOC_CLKCTL_OCS_FAST_CLK; - dsp_shim_regs->pwrctl |= SOC_PWRCTL_DISABLE_PWR_GATING_DSP0; - - soc_set_dmic_power(); - soc_set_gna_power(); - soc_set_audio_mclk(); -} - -static inline void soc_read_bootstraps(void) -{ - volatile struct soc_global_regs *regs = - (volatile struct soc_global_regs *)SOC_S1000_GLB_CTRL_BASE; - uint32_t bootstrap; - - bootstrap = regs->straps; - - bootstrap &= SOC_S1000_STRAP_REF_CLK; - - switch (bootstrap) { - case SOC_S1000_STRAP_REF_CLK_19P2: - ref_clk_freq = 19200000U; - break; - case SOC_S1000_STRAP_REF_CLK_24P576: - ref_clk_freq = 24576000U; - break; - case SOC_S1000_STRAP_REF_CLK_38P4: - default: - ref_clk_freq = 38400000U; - break; - } -} - -static int soc_init(const struct device *dev) -{ - soc_read_bootstraps(); - - LOG_INF("Reference clock frequency: %u Hz", ref_clk_freq); - - soc_set_resource_ownership(); - soc_set_power_and_clock(); - - return 0; -} - -SYS_INIT(soc_init, PRE_KERNEL_1, 99); diff --git a/soc/xtensa/intel_s1000/soc.h b/soc/xtensa/intel_s1000/soc.h deleted file mode 100644 index b928388d04e14..0000000000000 --- a/soc/xtensa/intel_s1000/soc.h +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright (c) 2019 Intel Corporation - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef __INC_SOC_H -#define __INC_SOC_H - -#include - -/* macros related to interrupt handling */ -#define XTENSA_IRQ_NUM_SHIFT 0 -#define CAVS_IRQ_NUM_SHIFT 8 -#define INTR_CNTL_IRQ_NUM_SHIFT 16 -#define XTENSA_IRQ_NUM_MASK 0xff -#define CAVS_IRQ_NUM_MASK 0xff -#define INTR_CNTL_IRQ_NUM_MASK 0xff - -/* - * IRQs are mapped on 3 levels. 4th level is left 0x00. - * - * 1. Peripheral Register bit offset. - * 2. CAVS logic bit offset. - * 3. Core interrupt number. - */ -#define XTENSA_IRQ_NUMBER(_irq) \ - ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK) -#define CAVS_IRQ_NUMBER(_irq) \ - (((_irq >> CAVS_IRQ_NUM_SHIFT) & CAVS_IRQ_NUM_MASK) - 1) -#define INTR_CNTL_IRQ_NUM(_irq) \ - (((_irq >> INTR_CNTL_IRQ_NUM_SHIFT) & INTR_CNTL_IRQ_NUM_MASK) - 1) - -/* Macro that aggregates the tri-level interrupt into an IRQ number */ -#define SOC_AGGREGATE_IRQ(ictl_irq, cavs_irq, core_irq) \ - (((core_irq & XTENSA_IRQ_NUM_MASK) << XTENSA_IRQ_NUM_SHIFT) | \ - (((cavs_irq) & CAVS_IRQ_NUM_MASK) << CAVS_IRQ_NUM_SHIFT) | \ - (((ictl_irq) & INTR_CNTL_IRQ_NUM_MASK) << INTR_CNTL_IRQ_NUM_SHIFT)) - -#define CAVS_L2_AGG_INT_LEVEL2 DT_IRQN(DT_INST(0, intel_cavs_intc)) -#define CAVS_L2_AGG_INT_LEVEL3 DT_IRQN(DT_INST(1, intel_cavs_intc)) -#define CAVS_L2_AGG_INT_LEVEL4 DT_IRQN(DT_INST(2, intel_cavs_intc)) -#define CAVS_L2_AGG_INT_LEVEL5 DT_IRQN(DT_INST(3, intel_cavs_intc)) - -#define CAVS_ICTL_INT_CPU_OFFSET(x) (0x40 * x) - -#define IOAPIC_EDGE 0 -#define IOAPIC_HIGH 0 - -/* DW interrupt controller */ -#define DW_ICTL_IRQ_CAVS_OFFSET CAVS_IRQ_NUMBER(DT_IRQN(DT_INST(0, snps_designware_intc))) -#define DW_ICTL_NUM_IRQS 9 - -/* GPIO */ -#define GPIO_DW_PORT_0_INT_MASK 0 - -#define DMA_HANDSHAKE_DMIC_RXA 0 -#define DMA_HANDSHAKE_DMIC_RXB 1 -#define DMA_HANDSHAKE_SSP0_TX 2 -#define DMA_HANDSHAKE_SSP0_RX 3 -#define DMA_HANDSHAKE_SSP1_TX 4 -#define DMA_HANDSHAKE_SSP1_RX 5 -#define DMA_HANDSHAKE_SSP2_TX 6 -#define DMA_HANDSHAKE_SSP2_RX 7 -#define DMA_HANDSHAKE_SSP3_TX 8 -#define DMA_HANDSHAKE_SSP3_RX 9 - -/* I2S */ -#define I2S_CAVS_IRQ(i2s_num) \ - SOC_AGGREGATE_IRQ(0, (i2s_num) + 1, CAVS_L2_AGG_INT_LEVEL5) - -#define I2S0_CAVS_IRQ I2S_CAVS_IRQ(0) -#define I2S1_CAVS_IRQ I2S_CAVS_IRQ(1) -#define I2S2_CAVS_IRQ I2S_CAVS_IRQ(2) -#define I2S3_CAVS_IRQ I2S_CAVS_IRQ(3) - -#define SSP_SIZE 0x0000200 -#define SSP_BASE(x) (0x00077000 + (x) * SSP_SIZE) -#define SSP_MN_DIV_SIZE (8) -#define SSP_MN_DIV_BASE(x) \ - (0x00078D00 + ((x) * SSP_MN_DIV_SIZE)) - -/* MCLK control */ -#define SOC_MCLK_DIV_CTRL_BASE 0x78C00 -#define SOC_NUM_MCLK_OUTPUTS 2 -#define SOC_MDIVCTRL_MCLK_OUT_EN(mclk) BIT(mclk) -#define SOC_MDIVXR_SET_DIVIDER_BYPASS BIT_MASK(12) - -struct soc_mclk_control_regs { - uint32_t mdivctrl; - uint32_t reserved[31]; - uint32_t mdivxr[SOC_NUM_MCLK_OUTPUTS]; -}; - -#define PDM_BASE 0x00010000 - -#define SOC_NUM_LPGPDMAC 3 -#define SOC_NUM_CHANNELS_IN_DMAC 8 - -/* DSP Wall Clock Timers (0 and 1) */ -#define DSP_WCT_IRQ(x) \ - SOC_AGGREGATE_IRQ(0, (23 + x), CAVS_L2_AGG_INT_LEVEL2) - -#define DSP_WCT_CS_TA(x) BIT(x) -#define DSP_WCT_CS_TT(x) BIT(4 + x) - -/* SOC Resource Allocation Registers */ -#define SOC_RESOURCE_ALLOC_REG_BASE 0x00071A60 -/* bit field definition for LP GPDMA ownership register */ -#define SOC_LPGPDMAC_OWNER_DSP \ - (BIT(15) | BIT_MASK(SOC_NUM_CHANNELS_IN_DMAC)) - -#define SOC_NUM_I2S_INSTANCES 4 -/* bit field definition for IO peripheral ownership register */ -#define SOC_DSPIOP_I2S_OWNSEL_DSP \ - (BIT_MASK(SOC_NUM_I2S_INSTANCES) << 8) -#define SOC_DSPIOP_DMIC_OWNSEL_DSP BIT(0) - -/* bit field definition for general ownership register */ -#define SOC_GENO_TIMESTAMP_OWNER_DSP BIT(2) -#define SOC_GENO_MNDIV_OWNER_DSP BIT(1) - -struct soc_resource_alloc_regs { - union { - uint16_t lpgpdmacxo[SOC_NUM_LPGPDMAC]; - uint16_t reserved[4]; - }; - uint32_t dspiopo; - uint32_t geno; -}; - -/* L2 Local Memory Registers */ -#define SOC_L2RAM_LOCAL_MEM_REG_BASE 0x00071D00 -#define SOC_L2RAM_LOCAL_MEM_REG_LSPGCTL \ - (SOC_L2RAM_LOCAL_MEM_REG_BASE + 0x50) - -/* DMIC SHIM Registers */ -#define SOC_DMIC_SHIM_REG_BASE 0x00071E80 -#define SOC_DMIC_SHIM_DMICLCTL_SPA BIT(0) -#define SOC_DMIC_SHIM_DMICLCTL_CPA BIT(8) - -struct soc_dmic_shim_regs { - uint32_t dmiclcap; - uint32_t dmiclctl; -}; - -/* SOC DSP SHIM Registers */ -#define SOC_DSP_SHIM_REG_BASE 0x00071F00 -/* SOC DSP SHIM Register - Clock Control */ -#define SOC_CLKCTL_REQ_FAST_CLK BIT(31) -#define SOC_CLKCTL_REQ_SLOW_CLK BIT(30) -#define SOC_CLKCTL_OCS_FAST_CLK BIT(2) -/* SOC DSP SHIM Register - Power Control */ -#define SOC_PWRCTL_DISABLE_PWR_GATING_DSP0 BIT(0) -#define SOC_PWRCTL_DISABLE_PWR_GATING_DSP1 BIT(1) - -struct soc_dsp_shim_regs { - uint32_t reserved[8]; - union { - struct { - uint32_t walclk32_lo; - uint32_t walclk32_hi; - }; - uint64_t walclk; - }; - uint32_t dspwctcs; - uint32_t reserved1[1]; - union { - struct { - uint32_t dspwct0c32_lo; - uint32_t dspwct0c32_hi; - }; - uint64_t dspwct0c; - }; - union { - struct { - uint32_t dspwct1c32_lo; - uint32_t dspwct1c32_hi; - }; - uint64_t dspwct1c; - }; - uint32_t reserved2[14]; - uint32_t clkctl; - uint32_t clksts; - uint32_t reserved3[4]; - uint16_t pwrctl; - uint16_t pwrsts; - uint32_t lpsctl; - uint32_t lpsdmas0; - uint32_t lpsdmas1; - uint32_t reserved4[22]; -}; - -/* Global Control registers */ -#define SOC_S1000_GLB_CTRL_BASE (0x00081C00) - -#define SOC_GNA_POWER_CONTROL_SPA (BIT(0)) -#define SOC_GNA_POWER_CONTROL_CPA (BIT(8)) -#define SOC_GNA_POWER_CONTROL_CLK_EN (BIT(16)) - -#define SOC_S1000_GLB_CTRL_DSP1_PWRCTL_CRST BIT(1) -#define SOC_S1000_GLB_CTRL_DSP1_PWRCTL_CSTALL BIT(9) -#define SOC_S1000_GLB_CTRL_DSP1_PWRCTL_SPA BIT(17) -#define SOC_S1000_GLB_CTRL_DSP1_PWRCTL_CPA BIT(25) - -#define SOC_S1000_STRAP_REF_CLK (BIT_MASK(2) << 3) -#define SOC_S1000_STRAP_REF_CLK_38P4 (0 << 3) -#define SOC_S1000_STRAP_REF_CLK_19P2 (1 << 3) -#define SOC_S1000_STRAP_REF_CLK_24P576 (2 << 3) - -struct soc_global_regs { - uint32_t reserved1[5]; - uint32_t cavs_dsp1power_control; - uint32_t reserved2[2]; - uint32_t gna_power_control; - uint32_t reserved3[7]; - uint32_t straps; -}; - -/* macros for data cache operations */ -#define SOC_DCACHE_FLUSH(addr, size) \ - z_xtensa_cache_flush((addr), (size)) -#define SOC_DCACHE_INVALIDATE(addr, size) \ - z_xtensa_cache_inv((addr), (size)) - -extern void z_soc_irq_enable(uint32_t irq); -extern void z_soc_irq_disable(uint32_t irq); -extern int z_soc_irq_is_enabled(unsigned int irq); - -extern uint32_t soc_get_ref_clk_freq(void); - -#endif /* __INC_SOC_H */ diff --git a/soc/xtensa/intel_s1000/soc/shim.h b/soc/xtensa/intel_s1000/soc/shim.h deleted file mode 100644 index caee6b175d853..0000000000000 --- a/soc/xtensa/intel_s1000/soc/shim.h +++ /dev/null @@ -1,268 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 - * - * Copyright(c) 2016 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - * Keyon Jie - */ - -#ifndef __PLATFORM_LIB_SHIM_H__ -#define __PLATFORM_LIB_SHIM_H__ - -#include -#include - -#ifndef ASSEMBLY -#include -#endif - -#if !defined(__ASSEMBLER__) && !defined(LINKER) -#include -#include -#endif - -#ifndef BIT -#define BIT(b) (1 << (b)) -#endif - -/* DSP IPC for Host Registers */ -#define IPC_DIPCT 0x00 -#define IPC_DIPCTE 0x04 -#define IPC_DIPCI 0x08 -#define IPC_DIPCIE 0x0c -#define IPC_DIPCCTL 0x10 - -/* DIPCT */ -#define IPC_DIPCT_BUSY BIT(31) -#define IPC_DIPCT_MSG_MASK 0x7FFFFFFF - -/* DIPCTE */ -#define IPC_DIPCTE_MSG_MASK 0x3FFFFFFF - -/* DIPCI */ -#define IPC_DIPCI_BUSY BIT(31) -#define IPC_DIPCI_MSG_MASK 0x7FFFFFFF - -/* DIPCIE */ -#define IPC_DIPCIE_DONE BIT(30) -#define IPC_DIPCIE_MSG_MASK 0x3FFFFFFF - -/* DIPCCTL */ -#define IPC_DIPCCTL_IPCIDIE BIT(1) -#define IPC_DIPCCTL_IPCTBIE BIT(0) - -#define IPC_DSP_OFFSET 0x10 - -/* DSP IPC for intra DSP communication */ -#define IPC_IDCTFC(x) (0x0 + x * IPC_DSP_OFFSET) -#define IPC_IDCTEFC(x) (0x4 + x * IPC_DSP_OFFSET) -#define IPC_IDCITC(x) (0x8 + x * IPC_DSP_OFFSET) -#define IPC_IDCIETC(x) (0xc + x * IPC_DSP_OFFSET) -#define IPC_IDCCTL 0x50 - -/* IDCTFC */ -#define IPC_IDCTFC_BUSY BIT(31) -#define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF - -/* IDCTEFC */ -#define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF - -/* IDCITC */ -#define IPC_IDCITC_BUSY BIT(31) -#define IPC_IDCITC_MSG_MASK 0x7FFFFFFF - -/* IDCIETC */ -#define IPC_IDCIETC_DONE BIT(30) -#define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF - -/* IDCCTL */ -#define IPC_IDCCTL_IDCIDIE(x) (0x100 << (x)) -#define IPC_IDCCTL_IDCTBIE(x) BIT(x) - -#define IRQ_CPU_OFFSET 0x40 - -#define REG_IRQ_IL2MSD(xcpu) (0x0 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2MCD(xcpu) (0x4 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2MD(xcpu) (0x8 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2SD(xcpu) (0xc + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL2MD_ALL 0x03F181F0 - -#define REG_IRQ_IL3MSD(xcpu) (0x10 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3MCD(xcpu) (0x14 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3MD(xcpu) (0x18 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3SD(xcpu) (0x1c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL3MD_ALL 0x807F81FF - -#define REG_IRQ_IL4MSD(xcpu) (0x20 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4MCD(xcpu) (0x24 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4MD(xcpu) (0x28 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4SD(xcpu) (0x2c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL4MD_ALL 0x807F81FF - -#define REG_IRQ_IL5MSD(xcpu) (0x30 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5MCD(xcpu) (0x34 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5MD(xcpu) (0x38 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5SD(xcpu) (0x3c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL5MD_ALL 0xFFFFC0CF - -#define REG_IRQ_IL2RSD 0x100 -#define REG_IRQ_IL3RSD 0x104 -#define REG_IRQ_IL4RSD 0x108 -#define REG_IRQ_IL5RSD 0x10c - -#define REG_IRQ_LVL5_LP_GPDMA0_MASK (0xff << 16) -#define REG_IRQ_LVL5_LP_GPDMA1_MASK (0xff << 24) - -/* DSP Shim Registers */ -#define SHIM_DSPWC 0x20 /* DSP Wall Clock */ -#define SHIM_DSPWCTCS 0x28 /* DSP Wall Clock Timer Control & Status */ -#define SHIM_DSPWCT0C 0x30 /* DSP Wall Clock Timer 0 Compare */ -#define SHIM_DSPWCT1C 0x38 /* DSP Wall Clock Timer 1 Compare */ - -#define SHIM_DSPWCTCS_T1T BIT(5) /* Timer 1 triggered */ -#define SHIM_DSPWCTCS_T0T BIT(4) /* Timer 0 triggered */ -#define SHIM_DSPWCTCS_T1A BIT(1) /* Timer 1 armed */ -#define SHIM_DSPWCTCS_T0A BIT(0) /* Timer 0 armed */ - -/** \brief Clock control */ -#define SHIM_CLKCTL 0x78 - -/** \brief Clock status */ -#define SHIM_CLKSTS 0x7C - -/** \brief Request Audio PLL Clock */ -#define SHIM_CLKCTL_RAPLLC BIT(31) - -/** \brief Request XTAL Oscillator Clock */ -#define SHIM_CLKCTL_RXOSCC BIT(30) - -/** \brief Request Fast RING Oscillator Clock */ -#define SHIM_CLKCTL_RFROSCC BIT(29) - -/** \brief LP GPDMA Force Dynamic Clock Gating bits, 0: enable */ -#define SHIM_CLKCTL_LPGPDMAFDCGB(x) BIT(26 + x) - -/** \brief DMIC Force Dynamic Clock Gating */ -#define SHIM_CLKCTL_DMICFDCGB BIT(24) - -/** \brief I2S Force Dynamic Clock Gating */ -#define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x) - -/** \brief I2S Extension Force Dynamic Clock Gating */ -#define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x) - -/** \brief Tensilica Core Prevent Local Clock Gating */ -#define SHIM_CLKCTL_TCPLCG_EN(x) BIT(16 + (x)) -#define SHIM_CLKCTL_TCPLCG_DIS(x) 0 - -/** \brief Core clock PLL divisor */ -#define SHIM_CLKCTL_DPCS_MASK(x) (0x3 << (8 + x * 2)) -#define SHIM_CLKCTL_DPCS_DIV1(x) (0x0 << (8 + x * 2)) -#define SHIM_CLKCTL_DPCS_DIV2(x) (0x1 << (8 + x * 2)) -#define SHIM_CLKCTL_DPCS_DIV4(x) (0x3 << (8 + x * 2)) - -/** \brief Tensilica Core Prevent Audio PLL Shutdown */ -#define SHIM_CLKCTL_TCPAPLLS_EN BIT(7) -#define SHIM_CLKCTL_TCPAPLLS_DIS 0 - -/** \brief LP domain clock select, 0: PLL, 1: oscillator */ -#define SHIM_CLKCTL_LDCS_XTAL BIT(5) -#define SHIM_CLKCTL_LDCS_PLL 0 - -/** \brief HP domain clock select */ -#define SHIM_CLKCTL_HDCS BIT(4) -#define SHIM_CLKCTL_HDCS_XTAL BIT(4) -#define SHIM_CLKCTL_HDCS_PLL 0 - -/** \brief LP domain oscillator clock select select, 0: XTAL, 1: Fast RING */ -#define SHIM_CLKCTL_LDOCS BIT(3) - -/** \brief HP domain oscillator clock select select, 0: XTAL, 1: Fast RING */ -#define SHIM_CLKCTL_HDOCS BIT(2) - -/** \brief LP memory clock PLL divisor, 0: div by 2, 1: div by 4 */ -#define SHIM_CLKCTL_LPMPCS_DIV4 BIT(1) -#define SHIM_CLKCTL_LPMPCS_DIV2 0 - -/** \brief HP memory clock PLL divisor, 0: div by 2, 1: div by 4 */ -#define SHIM_CLKCTL_HPMPCS_DIV4 BIT(0) -#define SHIM_CLKCTL_HPMPCS_DIV2 0 - -#define SHIM_PWRCTL 0x90 -#define SHIM_PWRSTS 0x92 -#define SHIM_LPSCTL 0x94 - -/* HP & LP SRAM Power Gating */ -#define SHIM_HSPGCTL 0x80 -#define SHIM_LSPGCTL 0x84 -#define SHIM_SPSREQ 0xa0 - -#define SHIM_SPSREQ_RVNNP BIT(0) - -/** \brief GPDMA shim registers Control */ -#define SHIM_GPDMA_BASE_OFFSET 0xC00 -#define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x80) - -/** \brief GPDMA Channel Linear Link Position Control */ -#define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + (y) * 0x10) -#define SHIM_GPDMA_CHLLPC_EN BIT(5) -#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(4, 0, x) - -/** \brief LDO Control */ -#define SHIM_LDOCTL 0xA4 -#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0) -#define SHIM_LDOCTL_LPSRAM_MASK (3 << 2) -#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0) -#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2) -#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0) -#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2) -#define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0) -#define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2) - -#define SHIM_HSPGISTS 0xb0 -#define SHIM_LSPGISTS 0xb4 -#define LSPGISTS (SHIM_BASE + SHIM_LSPGISTS) - - -#define SHIM_LPSCTL_FDSPRUN BIT(9) -#define SHIM_LPSCTL_FDMARUN BIT(8) - -#define SHIM_L2_MECS (SHIM_BASE + 0xd0) - -#define SHIM_LPGPDMAC(x) (0x1110 + (2 * x)) -#define SHIM_LPGPDMAC_CTLOSEL BIT(15) -#define SHIM_LPGPDMAC_CHOSEL 0xFF - -#define SHIM_DSPIOPO 0x1118 -#define SHIM_DSPIOPO_DMICOSEL BIT(0) -#define SHIM_DSPIOPO_I2SOSEL (0x3F << 8) - -#define SHIM_GENO 0x111C -#define SHIM_GENO_SHIMOSEL BIT(0) -#define SHIM_GENO_MDIVOSEL BIT(1) -#define SHIM_GENO_DIOPTOSEL BIT(2) - -#define SHIM_L2_CACHE_CTRL (SHIM_BASE + 0x500) -#define SHIM_L2_PREF_CFG (SHIM_BASE + 0x508) -#define SHIM_L2_CACHE_PREF (SHIM_BASE + 0x510) - -#define SHIM_SVCFG 0xF4 -#define SHIM_SVCFG_FORCE_L1_EXIT BIT(1) - -/* host windows */ -#define DMWBA(x) (HOST_WIN_BASE(x) + 0x0) -#define DMWLO(x) (HOST_WIN_BASE(x) + 0x4) - -#define DMWBA_ENABLE BIT(0) -#define DMWBA_READONLY BIT(1) - - -#endif /* __PLATFORM_LIB_SHIM_H__ */ diff --git a/soc/xtensa/intel_s1000/soc_mp.c b/soc/xtensa/intel_s1000/soc_mp.c deleted file mode 100644 index 9b837fec5b6a7..0000000000000 --- a/soc/xtensa/intel_s1000/soc_mp.c +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (c) 2018-2020 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -LOG_MODULE_REGISTER(soc_mp, CONFIG_SOC_LOG_LEVEL); - -#include "soc.h" -#include "memory.h" - -#ifdef CONFIG_SCHED_IPI_SUPPORTED -#include -#include - -static const struct device *idc; -#endif -extern void __start(void); - -struct cpustart_rec { - uint32_t cpu; - arch_cpustart_t fn; - char *stack_top; - void *arg; - uint32_t vecbase; - uint32_t alive; - /* padding to cache line */ - uint8_t padding[XCHAL_DCACHE_LINESIZE - 6 * 4]; -}; - -static __aligned(XCHAL_DCACHE_LINESIZE) -struct cpustart_rec start_rec; - -static void *mp_top; - -static void mp_entry2(void) -{ - volatile int ps, ie; - - /* Copy over VECBASE from the main CPU for an initial value - * (will need to revisit this if we ever allow a user API to - * change interrupt vectors at runtime). Make sure interrupts - * are locally disabled, then synthesize a PS value that will - * enable them for the user code to pass to irq_unlock() - * later. - */ - __asm__ volatile("rsr.PS %0" : "=r"(ps)); - ps &= ~(PS_EXCM_MASK | PS_INTLEVEL_MASK); - __asm__ volatile("wsr.PS %0" : : "r"(ps)); - - ie = 0; - __asm__ volatile("wsr.INTENABLE %0" : : "r"(ie)); - __asm__ volatile("wsr.VECBASE %0" : : "r"(start_rec.vecbase)); - __asm__ volatile("rsync"); - - /* Set up the CPU pointer. */ - _cpu_t *cpu = &_kernel.cpus[start_rec.cpu]; - - __asm__ volatile( - "wsr." ZSR_CPU_STR " %0" : : "r"(cpu)); - -#ifdef CONFIG_IPM_CAVS_IDC - /* Interrupt must be enabled while running on current core */ - irq_enable(XTENSA_IRQ_NUMBER(DT_IRQN(DT_INST(0, intel_cavs_idc)))); -#endif /* CONFIG_IPM_CAVS_IDC */ - - start_rec.alive = 1; - SOC_DCACHE_FLUSH(&start_rec, sizeof(start_rec)); - - start_rec.fn(start_rec.arg); - -#if CONFIG_MP_NUM_CPUS == 1 - /* CPU#1 can be under manual control running custom functions - * instead of participating in general thread execution. - * Put the CPU into idle after those functions return - * so this won't return. - */ - for (;;) { - k_cpu_idle(); - } -#endif -} - -/* Defines a locally callable "function" named mp_stack_switch(). The - * first argument (in register a2 post-ENTRY) is the new stack pointer - * to go into register a1. The second (a3) is the entry point. - * Because this never returns, a0 is used as a scratch register then - * set to zero for the called function (a null return value is the - * signal for "top of stack" to the debugger). - */ -void mp_stack_switch(void *stack, void *entry); -__asm__("\n" - ".align 4 \n" - "mp_stack_switch: \n\t" - - "entry a1, 16 \n\t" - - "movi a0, 0 \n\t" - - "jx a3 \n\t"); - -/* Carefully constructed to use no stack beyond compiler-generated ABI - * instructions. Stack pointer is pointing to __stack at this point. - */ -void z_mp_entry(void) -{ - mp_stack_switch(mp_top, mp_entry2); -} - -void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz, - arch_cpustart_t fn, void *arg) -{ - volatile struct soc_dsp_shim_regs *dsp_shim_regs = - (volatile struct soc_dsp_shim_regs *)SOC_DSP_SHIM_REG_BASE; - volatile struct soc_global_regs *soc_glb_regs = - (volatile struct soc_global_regs *)SOC_S1000_GLB_CTRL_BASE; - uint32_t vecbase; - - __ASSERT(cpu_num == 1, "Intel S1000 supports only two CPUs!"); - - /* Setup data to boot core #1 */ - __asm__ volatile("rsr.VECBASE %0\n\t" : "=r"(vecbase)); - - start_rec.cpu = cpu_num; - start_rec.fn = fn; - start_rec.stack_top = Z_THREAD_STACK_BUFFER(stack) + sz; - start_rec.arg = arg; - start_rec.vecbase = vecbase; - start_rec.alive = 0; - - mp_top = Z_THREAD_STACK_BUFFER(stack) + sz; - - SOC_DCACHE_FLUSH(&start_rec, sizeof(start_rec)); - -#ifdef CONFIG_SCHED_IPI_SUPPORTED - idc = device_get_binding(DT_LABEL(DT_INST(0, intel_cavs_idc))); -#endif - - /* - * SoC Boot ROM has hard-coded address for boot vector in LP-SRAM, - * and will jump unconditionally to it. So power up the LP-SRAM - * and set the vector. - */ - sys_write32(0x0, SOC_L2RAM_LOCAL_MEM_REG_LSPGCTL); - *((uint32_t *)LPSRAM_BOOT_VECTOR_ADDR) = (uint32_t)__start; - - /* Disable power gating for DSP core #cpu_num */ - dsp_shim_regs->pwrctl |= SOC_PWRCTL_DISABLE_PWR_GATING_DSP1; - - /* - * Since we do not know the status of the core, - * power it down and force it into reset and stall. - */ - soc_glb_regs->cavs_dsp1power_control |= - SOC_S1000_GLB_CTRL_DSP1_PWRCTL_CRST | - SOC_S1000_GLB_CTRL_DSP1_PWRCTL_CSTALL; - - soc_glb_regs->cavs_dsp1power_control &= - ~SOC_S1000_GLB_CTRL_DSP1_PWRCTL_SPA; - - /* Wait for core power down */ - while ((soc_glb_regs->cavs_dsp1power_control & - SOC_S1000_GLB_CTRL_DSP1_PWRCTL_CPA) != 0) { - } - - /* Now power up the core */ - soc_glb_regs->cavs_dsp1power_control |= - SOC_S1000_GLB_CTRL_DSP1_PWRCTL_SPA; - - /* Wait for core power up*/ - while ((soc_glb_regs->cavs_dsp1power_control & - SOC_S1000_GLB_CTRL_DSP1_PWRCTL_CPA) == 0) { - } - - /* Then step out of reset, and un-stall */ - soc_glb_regs->cavs_dsp1power_control &= - ~SOC_S1000_GLB_CTRL_DSP1_PWRCTL_CRST; - - soc_glb_regs->cavs_dsp1power_control &= - ~SOC_S1000_GLB_CTRL_DSP1_PWRCTL_CSTALL; - - do { - SOC_DCACHE_INVALIDATE(&start_rec, sizeof(start_rec)); - } while (start_rec.alive == 0); -} - -#ifdef CONFIG_SCHED_IPI_SUPPORTED -FUNC_ALIAS(soc_sched_ipi, arch_sched_ipi, void); -void soc_sched_ipi(void) -{ - if (likely(idc != NULL)) { - ipm_send(idc, 0, IPM_CAVS_IDC_MSG_SCHED_IPI_ID, - IPM_CAVS_IDC_MSG_SCHED_IPI_DATA, 0); - } -} -#endif diff --git a/soc/xtensa/intel_s1000/xcc/CMakeLists.txt b/soc/xtensa/intel_s1000/xcc/CMakeLists.txt deleted file mode 100644 index 13ba2bd79306f..0000000000000 --- a/soc/xtensa/intel_s1000/xcc/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources_ifdef(CONFIG_CPLUSPLUS cpp_fixes.c) -zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fixes.c) diff --git a/soc/xtensa/intel_s1000/xcc/cpp_fixes.c b/soc/xtensa/intel_s1000/xcc/cpp_fixes.c deleted file mode 100644 index 2e840c7d3e4d3..0000000000000 --- a/soc/xtensa/intel_s1000/xcc/cpp_fixes.c +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#ifdef __clang__ - -int atexit(void (*function)(void)) -{ - return 0; -} - -#endif /* __clang__ */ diff --git a/soc/xtensa/intel_s1000/xcc/newlib_fixes.c b/soc/xtensa/intel_s1000/xcc/newlib_fixes.c deleted file mode 100644 index f4e8fa7375649..0000000000000 --- a/soc/xtensa/intel_s1000/xcc/newlib_fixes.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include - -#include - -int _gettimeofday_r(struct _reent *r, struct timeval *__tp, void *__tzp) -{ - ARG_UNUSED(r); - ARG_UNUSED(__tp); - ARG_UNUSED(__tzp); - - return -1; -} From 3d32747a4a3a3c5696c4f3476bd32f9424846713 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 13 Jun 2022 14:26:59 -0400 Subject: [PATCH 4/8] west: remove intel_s1000_crb runners Remove runners specific to the intel_s1000_crb board. it is no longer available or supported in the zephyr tree. Signed-off-by: Anas Nashif --- scripts/west_commands/runners/__init__.py | 1 - scripts/west_commands/runners/intel_s1000.py | 172 ------------------- scripts/west_commands/tests/test_imports.py | 1 - 3 files changed, 174 deletions(-) delete mode 100644 scripts/west_commands/runners/intel_s1000.py diff --git a/scripts/west_commands/runners/__init__.py b/scripts/west_commands/runners/__init__.py index d02e8e24d9834..1259747792b4b 100644 --- a/scripts/west_commands/runners/__init__.py +++ b/scripts/west_commands/runners/__init__.py @@ -35,7 +35,6 @@ def _import_runner_module(runner_name): 'hifive1', 'intel_adsp', 'intel_cyclonev', - 'intel_s1000', 'jlink', 'mdb', 'misc', diff --git a/scripts/west_commands/runners/intel_s1000.py b/scripts/west_commands/runners/intel_s1000.py deleted file mode 100644 index 3c17c50abdcc0..0000000000000 --- a/scripts/west_commands/runners/intel_s1000.py +++ /dev/null @@ -1,172 +0,0 @@ -# Copyright (c) 2018 Intel Corporation. -# Copyright 2018 Open Source Foundries Limited. -# -# SPDX-License-Identifier: Apache-2.0 - -'''Runner for debugging and flashing Intel S1000 CRB''' -from os import path -import time -import signal - -from runners.core import ZephyrBinaryRunner - -DEFAULT_XT_GDB_PORT = 20000 - - -class IntelS1000BinaryRunner(ZephyrBinaryRunner): - '''Runner front-end for Intel S1000.''' - - def __init__(self, cfg, xt_ocd_dir, - ocd_topology, ocd_jtag_instr, gdb_flash_file, - gdb_port=DEFAULT_XT_GDB_PORT): - super().__init__(cfg) - self.board_dir = cfg.board_dir - self.elf_name = cfg.elf_file - self.gdb_cmd = cfg.gdb - self.xt_ocd_dir = xt_ocd_dir - self.ocd_topology = ocd_topology - self.ocd_jtag_instr = ocd_jtag_instr - self.gdb_flash_file = gdb_flash_file - self.gdb_port = gdb_port - - @classmethod - def name(cls): - return 'intel_s1000' - - @classmethod - def do_add_parser(cls, parser): - # Optional - parser.add_argument( - '--xt-ocd-dir', default='/opt/tensilica/xocd-12.0.4/xt-ocd', - help='ocd-dir, defaults to /opt/tensilica/xocd-12.0.4/xt-ocd') - parser.add_argument( - '--ocd-topology', default='topology_dsp0_flyswatter2.xml', - help='ocd-topology, defaults to topology_dsp0_flyswatter2.xml') - parser.add_argument( - '--ocd-jtag-instr', default='dsp0_gdb.txt', - help='ocd-jtag-instr, defaults to dsp0_gdb.txt') - parser.add_argument( - '--gdb-flash-file', default='load_elf.txt', - help='gdb-flash-file, defaults to load_elf.txt') - parser.add_argument( - '--gdb-port', default=DEFAULT_XT_GDB_PORT, - help='xt-gdb port, defaults to 20000') - - @classmethod - def do_create(cls, cfg, args): - return IntelS1000BinaryRunner( - cfg, args.xt_ocd_dir, - args.ocd_topology, args.ocd_jtag_instr, args.gdb_flash_file, - gdb_port=args.gdb_port) - - def do_run(self, command, **kwargs): - self.require(self.xt_ocd_dir) - kwargs['ocd-topology'] = path.join(self.board_dir, 'support', - self.ocd_topology) - kwargs['ocd-jtag-instr'] = path.join(self.board_dir, 'support', - self.ocd_jtag_instr) - kwargs['gdb-flash-file'] = path.join(self.board_dir, 'support', - self.gdb_flash_file) - - if command == 'flash': - self.flash(**kwargs) - elif command == 'debugserver': - self.debugserver(**kwargs) - else: - self.do_debug(**kwargs) - - def flash(self, **kwargs): - if self.gdb_cmd is None: - raise ValueError('Cannot debug; no gdb specified') - self.require(self.gdb_cmd) - topology_file = kwargs['ocd-topology'] - jtag_instr_file = kwargs['ocd-jtag-instr'] - gdb_flash_file = kwargs['gdb-flash-file'] - - self.log_gdbserver_message(self.gdb_port) - server_cmd = [self.xt_ocd_dir, - '-c', topology_file, - '-I', jtag_instr_file] - - # Start the server - # Note that XTOCD takes a few seconds to execute and always fails the - # first time. It has to be relaunched the second time to work. - server_proc = self.popen_ignore_int(server_cmd) - time.sleep(6) - server_proc.terminate() - server_proc = self.popen_ignore_int(server_cmd) - time.sleep(6) - - # Start the client - gdb_cmd = [self.gdb_cmd, '-x', gdb_flash_file] - client_proc = self.popen_ignore_int(gdb_cmd) - - # Wait for 3 seconds (waiting for XTGDB to finish loading the image) - time.sleep(3) - - # At this point, the ELF image is loaded and the program is in - # execution. Now we can quit the client (xt-gdb) and the server - # (xt-ocd) as they are not needed anymore. The loaded program - # (ELF) will continue to run though. - client_proc.terminate() - server_proc.terminate() - - def do_debug(self, **kwargs): - if self.elf_name is None: - raise ValueError('Cannot debug; elf is missing') - if self.gdb_cmd is None: - raise ValueError('Cannot debug; no gdb specified') - self.require(self.gdb_cmd) - - topology_file = kwargs['ocd-topology'] - jtag_instr_file = kwargs['ocd-jtag-instr'] - - self.log_gdbserver_message(self.gdb_port) - server_cmd = [self.xt_ocd_dir, - '-c', topology_file, - '-I', jtag_instr_file] - - # Start the server - # Note that XTOCD takes a few seconds to execute and always fails the - # first time. It has to be relaunched the second time to work. - server_proc = self.popen_ignore_int(server_cmd) - time.sleep(6) - server_proc.terminate() - server_proc = self.popen_ignore_int(server_cmd) - time.sleep(6) - - gdb_cmd = [self.gdb_cmd, - '-ex', 'target remote :{}'.format(self.gdb_port), - self.elf_name] - - # Start the client - # The below statement will consume the "^C" keypress ensuring - # the python main application doesn't exit. This is important - # since ^C in gdb means a "halt" operation. - previous = signal.signal(signal.SIGINT, signal.SIG_IGN) - try: - self.check_call(gdb_cmd) - finally: - signal.signal(signal.SIGINT, previous) - server_proc.terminate() - server_proc.wait() - - def debugserver(self, **kwargs): - topology_file = kwargs['ocd-topology'] - jtag_instr_file = kwargs['ocd-jtag-instr'] - - self.log_gdbserver_message(self.gdb_port) - server_cmd = [self.xt_ocd_dir, - '-c', topology_file, - '-I', jtag_instr_file] - - # Note that XTOCD takes a few seconds to execute and always fails the - # first time. It has to be relaunched the second time to work. - server_proc = self.popen_ignore_int(server_cmd) - time.sleep(6) - server_proc.terminate() - self.check_call(server_cmd) - - def log_gdbserver_message(self, gdb_port): - self.logger.info('Intel S1000 GDB server running on port {}'. - format(gdb_port)) diff --git a/scripts/west_commands/tests/test_imports.py b/scripts/west_commands/tests/test_imports.py index 4e2e48f68eaac..6c4a9f5bfeae4 100644 --- a/scripts/west_commands/tests/test_imports.py +++ b/scripts/west_commands/tests/test_imports.py @@ -25,7 +25,6 @@ def test_runner_imports(): 'hifive1', 'intel_adsp', 'intel_cyclonev', - 'intel_s1000', 'jlink', 'mdb-nsim', 'mdb-hw', From dd4ec0d290ea657c473107cb3ad084d61d16953a Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 13 Jun 2022 14:27:42 -0400 Subject: [PATCH 5/8] i2s: remove s1000 i2s driver Remove intel_s1000_crb drivers. The board is no longer available or supported in the zephyr tree. Signed-off-by: Anas Nashif --- drivers/i2s/CMakeLists.txt | 1 - drivers/i2s/Kconfig.cavs | 12 - drivers/i2s/i2s_cavs.c | 879 --------------------- drivers/i2s/i2s_cavs.h | 147 ---- soc/xtensa/intel_adsp/Kconfig.defconfig | 4 - soc/xtensa/intel_adsp/common/include/soc.h | 9 - 6 files changed, 1052 deletions(-) delete mode 100644 drivers/i2s/Kconfig.cavs delete mode 100644 drivers/i2s/i2s_cavs.c delete mode 100644 drivers/i2s/i2s_cavs.h diff --git a/drivers/i2s/CMakeLists.txt b/drivers/i2s/CMakeLists.txt index d97a16d58a0ca..4b3ce8eca379d 100644 --- a/drivers/i2s/CMakeLists.txt +++ b/drivers/i2s/CMakeLists.txt @@ -4,7 +4,6 @@ zephyr_library() zephyr_library_sources(i2s_common.c) zephyr_library_sources_ifdef(CONFIG_I2S_SAM_SSC i2s_sam_ssc.c) -zephyr_library_sources_ifdef(CONFIG_I2S_CAVS i2s_cavs.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE i2s_handlers.c) zephyr_library_sources_ifdef(CONFIG_I2S_STM32 i2s_ll_stm32.c) zephyr_library_sources_ifdef(CONFIG_I2S_LITEX i2s_litex.c) diff --git a/drivers/i2s/Kconfig.cavs b/drivers/i2s/Kconfig.cavs deleted file mode 100644 index ad33fc3f4660f..0000000000000 --- a/drivers/i2s/Kconfig.cavs +++ /dev/null @@ -1,12 +0,0 @@ -# Intel S1000 I2S configuration options - -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config I2S_CAVS - bool "Intel I2S (SSP) Bus Driver" - depends on BOARD_INTEL_S1000_CRB - select DMA - help - Enable Inter Sound (I2S) bus driver for Intel_S1000 based on - Synchronous Serial Port (SSP) module. diff --git a/drivers/i2s/i2s_cavs.c b/drivers/i2s/i2s_cavs.c deleted file mode 100644 index 1c75ba8c61355..0000000000000 --- a/drivers/i2s/i2s_cavs.c +++ /dev/null @@ -1,879 +0,0 @@ -/* - * Copyright (c) 2018 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief I2S bus (SSP) driver for Intel CAVS. - * - * Limitations: - * - DMA is used in simple single block transfer mode (with linked list - * enabled) and "interrupt on full transfer completion" mode. - */ - -#define DT_DRV_COMPAT intel_cavs_i2s - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "i2s_cavs.h" - -#define LOG_DOMAIN dev_i2s_cavs -#define LOG_LEVEL CONFIG_I2S_LOG_LEVEL -#include -LOG_MODULE_REGISTER(LOG_DOMAIN); - -/* length of the buffer queue */ -#define I2S_CAVS_BUF_Q_LEN 2 - -#define CAVS_SSP_WORD_SIZE_BITS_MIN 4 -#define CAVS_SSP_WORD_SIZE_BITS_MAX 32 -#define CAVS_SSP_WORD_PER_FRAME_MIN 1 -#define CAVS_SSP_WORD_PER_FRAME_MAX 8 - -#define CAVS_I2S_DMA_BURST_SIZE 8 - -/* - * This indicates the Tx/Rx stream. Most members of the stream are - * self-explanatory - * - * in_queue and out_queue are used as follows - * transmit stream: - * application provided buffer is queued to in_queue until loaded to DMA. - * when DMA channel is idle, buffer is retrieved from in_queue and loaded - * to DMA and queued to out_queue. - * when DMA completes, buffer is retrieved from out_queue and freed. - * - * receive stream: - * driver allocates buffer from slab and loads DMA - * buffer is queued to in_queue - * when DMA completes, buffer is retrieved from in_queue and queued to - * out_queue - * when application reads, buffer is read (may optionally block) from - * out_queue and presented to application. - */ -struct stream { - int32_t state; - uint32_t dma_channel; - struct dma_config dma_cfg; - struct dma_block_config dma_block; - struct k_msgq in_queue; - void *in_msgs[I2S_CAVS_BUF_Q_LEN]; - struct k_msgq out_queue; - void *out_msgs[I2S_CAVS_BUF_Q_LEN]; -}; - -struct i2s_cavs_config { - struct i2s_cavs_ssp *regs; - struct i2s_cavs_mn_div *mn_regs; - uint32_t irq_id; - void (*irq_connect)(void); - const struct device *dev_dma; -}; - -/* Device run time data */ -struct i2s_cavs_dev_data { - struct i2s_config cfg; - struct stream tx; - struct stream rx; -}; - -static void i2s_dma_tx_callback(const struct device *, void *, uint32_t, int); -static void i2s_tx_stream_disable(struct i2s_cavs_dev_data *, - volatile struct i2s_cavs_ssp *const, const struct device *); -static void i2s_rx_stream_disable(struct i2s_cavs_dev_data *, - volatile struct i2s_cavs_ssp *const, const struct device *); - -static inline void i2s_purge_stream_buffers(struct stream *strm, - struct k_mem_slab *mem_slab) -{ - void *buffer; - - while (k_msgq_get(&strm->in_queue, &buffer, K_NO_WAIT) == 0) { - k_mem_slab_free(mem_slab, &buffer); - } - while (k_msgq_get(&strm->out_queue, &buffer, K_NO_WAIT) == 0) { - k_mem_slab_free(mem_slab, &buffer); - } -} - -/* This function is executed in the interrupt context */ -static void i2s_dma_tx_callback(const struct device *dma_dev, void *arg, - uint32_t channel, int status) -{ - const struct device *dev = (const struct device *)arg; - const struct i2s_cavs_config *const dev_cfg = dev->config; - struct i2s_cavs_dev_data *const dev_data = dev->data; - - volatile struct i2s_cavs_ssp *const ssp = dev_cfg->regs; - struct stream *strm = &dev_data->tx; - void *buffer; - int ret; - - ret = k_msgq_get(&strm->out_queue, &buffer, K_NO_WAIT); - if (ret == 0) { - /* transmission complete. free the buffer */ - k_mem_slab_free(dev_data->cfg.mem_slab, &buffer); - } else { - LOG_ERR("no buffer in output queue for channel %u", - channel); - } - - switch (strm->state) { - - case I2S_STATE_RUNNING: - /* get the next buffer from queue */ - ret = k_msgq_get(&strm->in_queue, &buffer, K_NO_WAIT); - if (ret == 0) { - /* reload the DMA */ - dma_reload(dev_cfg->dev_dma, strm->dma_channel, - (uint32_t)buffer, (uint32_t)&ssp->ssd, - dev_data->cfg.block_size); - dma_start(dev_cfg->dev_dma, strm->dma_channel); - ssp->ssc1 |= SSCR1_TSRE; - k_msgq_put(&strm->out_queue, &buffer, K_NO_WAIT); - } - - if (ret || status) { - /* - * DMA encountered an error (status != 0) - * or - * No buffers in input queue - */ - LOG_ERR("DMA status %08x channel %u k_msgq_get ret %d", - status, channel, ret); - strm->state = I2S_STATE_STOPPING; - i2s_tx_stream_disable(dev_data, ssp, dev_cfg->dev_dma); - } - - break; - - case I2S_STATE_STOPPING: - i2s_tx_stream_disable(dev_data, ssp, dev_cfg->dev_dma); - break; - } -} - -static void i2s_dma_rx_callback(const struct device *dma_dev, void *arg, - uint32_t channel, int status) -{ - const struct device *dev = (const struct device *)arg; - const struct i2s_cavs_config *const dev_cfg = dev->config; - struct i2s_cavs_dev_data *const dev_data = dev->data; - volatile struct i2s_cavs_ssp *const ssp = dev_cfg->regs; - struct stream *strm = &dev_data->rx; - void *buffer; - int ret; - - switch (strm->state) { - - case I2S_STATE_RUNNING: - /* retrieve buffer from input queue */ - ret = k_msgq_get(&strm->in_queue, &buffer, K_NO_WAIT); - if (ret != 0) { - LOG_ERR("get buffer from in_queue %p failed (%d)", - &strm->in_queue, ret); - } - /* put buffer to output queue */ - ret = k_msgq_put(&strm->out_queue, &buffer, K_NO_WAIT); - if (ret != 0) { - LOG_ERR("buffer %p -> out_queue %p err %d", - buffer, &strm->out_queue, ret); - } - /* allocate new buffer for next audio frame */ - ret = k_mem_slab_alloc(dev_data->cfg.mem_slab, &buffer, - K_NO_WAIT); - if (ret != 0) { - LOG_ERR("buffer alloc from slab %p err %d", - dev_data->cfg.mem_slab, ret); - i2s_rx_stream_disable(dev_data, ssp, dev_cfg->dev_dma); - strm->state = I2S_STATE_READY; - } else { - /* put buffer in input queue */ - ret = k_msgq_put(&strm->in_queue, &buffer, K_NO_WAIT); - if (ret != 0) { - LOG_ERR("buffer %p -> in_queue %p err %d", - buffer, &strm->in_queue, ret); - } - - SOC_DCACHE_INVALIDATE(buffer, dev_data->cfg.block_size); - - /* reload the DMA */ - dma_reload(dev_cfg->dev_dma, strm->dma_channel, - (uint32_t)&ssp->ssd, (uint32_t)buffer, - dev_data->cfg.block_size); - dma_start(dev_cfg->dev_dma, strm->dma_channel); - ssp->ssc1 |= SSCR1_RSRE; - } - break; - case I2S_STATE_STOPPING: - i2s_rx_stream_disable(dev_data, ssp, dev_cfg->dev_dma); - strm->state = I2S_STATE_READY; - break; - } -} - -static int i2s_cavs_configure(const struct device *dev, enum i2s_dir dir, - const struct i2s_config *i2s_cfg) -{ - const struct i2s_cavs_config *const dev_cfg = dev->config; - struct i2s_cavs_dev_data *const dev_data = dev->data; - volatile struct i2s_cavs_ssp *const ssp = dev_cfg->regs; - volatile struct i2s_cavs_mn_div *const mn_div = dev_cfg->mn_regs; - struct dma_block_config *dma_block; - uint8_t num_words = i2s_cfg->channels; - uint8_t word_size_bits = i2s_cfg->word_size; - uint8_t word_size_bytes; - uint32_t bit_clk_freq, mclk; - int ret; - - uint32_t ssc0; - uint32_t ssc1; - uint32_t ssc2; - uint32_t ssc3; - uint32_t sspsp; - uint32_t sspsp2; - uint32_t sstsa; - uint32_t ssrsa; - uint32_t ssto; - uint32_t ssioc = 0U; - uint32_t mdiv; - uint32_t i2s_m = 0U; - uint32_t i2s_n = 0U; - uint32_t frame_len = 0U; - bool inverted_frame = false; - - if ((dev_data->tx.state != I2S_STATE_NOT_READY) && - (dev_data->tx.state != I2S_STATE_READY) && - (dev_data->rx.state != I2S_STATE_NOT_READY) && - (dev_data->rx.state != I2S_STATE_READY)) { - LOG_ERR("invalid state tx(%u) rx(%u)", dev_data->tx.state, - dev_data->rx.state); - return -EINVAL; - } - - if (i2s_cfg->frame_clk_freq == 0U) { - LOG_ERR("Invalid frame_clk_freq %u", - i2s_cfg->frame_clk_freq); - return -EINVAL; - } - - if (word_size_bits < CAVS_SSP_WORD_SIZE_BITS_MIN || - word_size_bits > CAVS_SSP_WORD_SIZE_BITS_MAX) { - LOG_ERR("Unsupported I2S word size %u", word_size_bits); - return -EINVAL; - } - - if (num_words < CAVS_SSP_WORD_PER_FRAME_MIN || - num_words > CAVS_SSP_WORD_PER_FRAME_MAX) { - LOG_ERR("Unsupported words per frame number %u", num_words); - return -EINVAL; - } - - if ((i2s_cfg->options & I2S_OPT_PINGPONG) == I2S_OPT_PINGPONG) { - LOG_ERR("Ping-pong mode not supported"); - return -ENOTSUP; - } - - memcpy(&dev_data->cfg, i2s_cfg, sizeof(struct i2s_config)); - - /* reset SSP settings */ - /* sscr0 dynamic settings are DSS, EDSS, SCR, FRDC, ECS */ - ssc0 = SSCR0_MOD | SSCR0_PSP | SSCR0_RIM; - - /* sscr1 dynamic settings are SFRMDIR, SCLKDIR, SCFR */ - ssc1 = SSCR1_TTE | SSCR1_TTELP | SSCR1_TRAIL; - - /* sscr2 dynamic setting is LJDFD */ - ssc2 = 0U; - - /* sscr3 dynamic settings are TFT, RFT */ - ssc3 = SSCR3_TX(CAVS_I2S_DMA_BURST_SIZE) | - SSCR3_RX(CAVS_I2S_DMA_BURST_SIZE); - - /* sspsp dynamic settings are SCMODE, SFRMP, DMYSTRT, SFRMWDTH */ - sspsp = 0U; - - /* sspsp2 no dynamic setting */ - sspsp2 = 0x0; - - /* ssto no dynamic setting */ - ssto = 0x0; - - /* sstsa dynamic setting is TTSA, set according to num_words */ - sstsa = BIT_MASK(num_words); - /* ssrsa dynamic setting is RTSA, set according to num_words */ - ssrsa = BIT_MASK(num_words); - - if (i2s_cfg->options & I2S_OPT_BIT_CLK_SLAVE) { - /* set BCLK mode as slave */ - ssc1 |= SSCR1_SCLKDIR; - } else { - /* enable BCLK output */ - ssioc = SSIOC_SCOE; - } - - if (i2s_cfg->options & I2S_OPT_FRAME_CLK_SLAVE) { - /* set WCLK mode as slave */ - ssc1 |= SSCR1_SFRMDIR; - } - - ssioc |= SSIOC_SFCR; - - /* clock signal polarity */ - switch (i2s_cfg->format & I2S_FMT_CLK_FORMAT_MASK) { - case I2S_FMT_CLK_NF_NB: - break; - - case I2S_FMT_CLK_NF_IB: - sspsp |= SSPSP_SCMODE(2); - break; - - case I2S_FMT_CLK_IF_NB: - inverted_frame = true; /* handled later with format */ - break; - - case I2S_FMT_CLK_IF_IB: - sspsp |= SSPSP_SCMODE(2); - inverted_frame = true; /* handled later with format */ - break; - - default: - LOG_ERR("Unsupported Clock format"); - return -EINVAL; - } - - mclk = soc_get_ref_clk_freq(); - bit_clk_freq = i2s_cfg->frame_clk_freq * word_size_bits * num_words; - - /* BCLK is generated from MCLK - must be divisible */ - if (mclk % bit_clk_freq) { - LOG_INF("MCLK/BCLK is not an integer, using M/N divider"); - - /* - * Simplification: Instead of calculating lowest values of - * M and N, just set M and N as BCLK and MCLK respectively - * in 0.1KHz units - * In addition, double M so that it can be later divided by 2 - * to get an approximately 50% duty cycle clock - */ - i2s_m = (bit_clk_freq << 1) / 100U; - i2s_n = mclk / 100U; - - /* set divider value of 1 which divides the clock by 2 */ - mdiv = 1U; - - /* Select M/N divider as the clock source */ - ssc0 |= SSCR0_ECS; - } else { - mdiv = (mclk / bit_clk_freq) - 1; - } - - /* divisor must be within SCR range */ - if (mdiv > (SSCR0_SCR_MASK >> 8)) { - LOG_ERR("Divisor is not within SCR range"); - return -EINVAL; - } - - /* set the SCR divisor */ - ssc0 |= SSCR0_SCR(mdiv); - - /* format */ - switch (i2s_cfg->format & I2S_FMT_DATA_FORMAT_MASK) { - - case I2S_FMT_DATA_FORMAT_I2S: - ssc0 |= SSCR0_FRDC(i2s_cfg->channels); - - /* set asserted frame length */ - frame_len = word_size_bits; - - /* handle frame polarity, I2S default is falling/active low */ - sspsp |= SSPSP_SFRMP(!inverted_frame) | SSPSP_FSRT; - break; - - case I2S_FMT_DATA_FORMAT_LEFT_JUSTIFIED: - ssc0 |= SSCR0_FRDC(i2s_cfg->channels); - - /* LJDFD enable */ - ssc2 &= ~SSCR2_LJDFD; - - /* set asserted frame length */ - frame_len = word_size_bits; - - /* LEFT_J default is rising/active high, opposite of I2S */ - sspsp |= SSPSP_SFRMP(inverted_frame); - break; - - case I2S_FMT_DATA_FORMAT_PCM_SHORT: - case I2S_FMT_DATA_FORMAT_PCM_LONG: - default: - LOG_ERR("Unsupported I2S data format"); - return -EINVAL; - } - - sspsp |= SSPSP_SFRMWDTH(frame_len); - - if (word_size_bits > 16) { - ssc0 |= (SSCR0_EDSS | SSCR0_DSIZE(word_size_bits - 16)); - } else { - ssc0 |= SSCR0_DSIZE(word_size_bits); - } - - ssp->ssc0 = ssc0; - ssp->ssc1 = ssc1; - ssp->ssc2 = ssc2; - ssp->ssc3 = ssc3; - ssp->sspsp2 = sspsp2; - ssp->sspsp = sspsp; - ssp->ssioc = ssioc; - ssp->ssto = ssto; - ssp->sstsa = sstsa; - ssp->ssrsa = ssrsa; - - mn_div->mval = I2S_MNVAL(i2s_m); - mn_div->nval = I2S_MNVAL(i2s_n); - - /* Set up DMA channel parameters */ - word_size_bytes = (word_size_bits + 7) / 8U; - dev_data->tx.dma_cfg.source_data_size = word_size_bytes; - dev_data->tx.dma_cfg.dest_data_size = word_size_bytes; - dev_data->rx.dma_cfg.source_data_size = word_size_bytes; - dev_data->rx.dma_cfg.dest_data_size = word_size_bytes; - - dma_block = dev_data->tx.dma_cfg.head_block; - dma_block->block_size = i2s_cfg->block_size; - dma_block->source_address = (uint32_t)NULL; - dma_block->dest_address = (uint32_t)&ssp->ssd; - - ret = dma_config(dev_cfg->dev_dma, dev_data->tx.dma_channel, - &dev_data->tx.dma_cfg); - if (ret < 0) { - LOG_ERR("dma_config failed: %d", ret); - return ret; - } - - dma_block = dev_data->rx.dma_cfg.head_block; - dma_block->block_size = i2s_cfg->block_size; - dma_block->source_address = (uint32_t)&ssp->ssd; - dma_block->dest_address = (uint32_t)NULL; - - ret = dma_config(dev_cfg->dev_dma, dev_data->rx.dma_channel, - &dev_data->rx.dma_cfg); - if (ret < 0) { - LOG_ERR("dma_config failed: %d", ret); - return ret; - } - - /* enable port */ - ssp->ssc0 |= SSCR0_SSE; - - /* enable interrupt */ - irq_enable(dev_cfg->irq_id); - - dev_data->tx.state = I2S_STATE_READY; - dev_data->rx.state = I2S_STATE_READY; - - return 0; -} - -static int i2s_tx_stream_start(struct i2s_cavs_dev_data *dev_data, - volatile struct i2s_cavs_ssp *const ssp, - const struct device *dev_dma) -{ - int ret = 0; - void *buffer; - unsigned int key; - struct stream *strm = &dev_data->tx; - - /* retrieve buffer from input queue */ - ret = k_msgq_get(&strm->in_queue, &buffer, K_NO_WAIT); - if (ret != 0) { - LOG_ERR("No buffer in input queue to start transmission"); - return ret; - } - - ret = dma_reload(dev_dma, strm->dma_channel, (uint32_t)buffer, - (uint32_t)&ssp->ssd, dev_data->cfg.block_size); - if (ret != 0) { - LOG_ERR("dma_reload failed (%d)", ret); - return ret; - } - - /* put buffer in output queue */ - ret = k_msgq_put(&strm->out_queue, &buffer, K_NO_WAIT); - if (ret != 0) { - LOG_ERR("failed to put buffer in output queue"); - return ret; - } - - ret = dma_start(dev_dma, strm->dma_channel); - - if (ret < 0) { - LOG_ERR("dma_start failed (%d)", ret); - return ret; - } - - /* Enable transmit operation */ - key = irq_lock(); - ssp->ssc1 |= SSCR1_TSRE; - ssp->sstsa |= SSTSA_TXEN; - irq_unlock(key); - - return 0; -} - -static int i2s_rx_stream_start(struct i2s_cavs_dev_data *dev_data, - volatile struct i2s_cavs_ssp *const ssp, - const struct device *dev_dma) -{ - int ret = 0; - void *buffer; - unsigned int key; - struct stream *strm = &dev_data->rx; - - /* allocate receive buffer from SLAB */ - ret = k_mem_slab_alloc(dev_data->cfg.mem_slab, &buffer, K_NO_WAIT); - if (ret != 0) { - LOG_ERR("buffer alloc from mem_slab failed (%d)", ret); - return ret; - } - - SOC_DCACHE_INVALIDATE(buffer, dev_data->cfg.block_size); - - ret = dma_reload(dev_dma, strm->dma_channel, (uint32_t)&ssp->ssd, - (uint32_t)buffer, dev_data->cfg.block_size); - if (ret != 0) { - LOG_ERR("dma_reload failed (%d)", ret); - return ret; - } - - /* put buffer in input queue */ - ret = k_msgq_put(&strm->in_queue, &buffer, K_NO_WAIT); - if (ret != 0) { - LOG_ERR("failed to put buffer in output queue"); - return ret; - } - - LOG_INF("Starting DMA Ch%u", strm->dma_channel); - ret = dma_start(dev_dma, strm->dma_channel); - if (ret < 0) { - LOG_ERR("Failed to start DMA Ch%d (%d)", strm->dma_channel, - ret); - return ret; - } - - /* Enable Receive operation */ - key = irq_lock(); - ssp->ssc1 |= SSCR1_RSRE; - ssp->ssrsa |= SSRSA_RXEN; - irq_unlock(key); - - return 0; -} - -static void i2s_tx_stream_disable(struct i2s_cavs_dev_data *dev_data, - volatile struct i2s_cavs_ssp *const ssp, - const struct device *dev_dma) -{ - struct stream *strm = &dev_data->tx; - unsigned int key; - - /* - * Enable transmit underrun interrupt to allow notification - * upon transmit FIFO being emptied. - * Defer disabling of TX to the underrun processing in ISR - */ - key = irq_lock(); - ssp->ssc0 &= ~SSCR0_TIM; - irq_unlock(key); - - LOG_INF("Stopping DMA channel %u for TX stream", strm->dma_channel); - dma_stop(dev_dma, strm->dma_channel); - - /* purge buffers queued in the stream */ - i2s_purge_stream_buffers(strm, dev_data->cfg.mem_slab); -} - -static void i2s_rx_stream_disable(struct i2s_cavs_dev_data *dev_data, - volatile struct i2s_cavs_ssp *const ssp, - const struct device *dev_dma) -{ - struct stream *strm = &dev_data->rx; - uint32_t data; - - /* Disable DMA service request handshake logic. Handshake is - * not required now since DMA is not in operation. - */ - ssp->ssrsa &= ~SSRSA_RXEN; - - LOG_INF("Stopping RX stream & DMA channel %u", strm->dma_channel); - dma_stop(dev_dma, strm->dma_channel); - - /* Empty the FIFO */ - while (ssp->sss & SSSR_RNE) { - /* read the RX FIFO */ - data = ssp->ssd; - } - - /* purge buffers queued in the stream */ - i2s_purge_stream_buffers(strm, dev_data->cfg.mem_slab); -} - -static int i2s_cavs_trigger(const struct device *dev, enum i2s_dir dir, - enum i2s_trigger_cmd cmd) -{ - const struct i2s_cavs_config *const dev_cfg = dev->config; - struct i2s_cavs_dev_data *const dev_data = dev->data; - volatile struct i2s_cavs_ssp *const ssp = dev_cfg->regs; - struct stream *strm; - unsigned int key; - int ret = 0; - - if (dir == I2S_DIR_BOTH) { - return -ENOSYS; - } - - strm = (dir == I2S_DIR_TX) ? &dev_data->tx : &dev_data->rx; - - key = irq_lock(); - switch (cmd) { - case I2S_TRIGGER_START: - if (strm->state != I2S_STATE_READY) { - LOG_ERR("START trigger: invalid state %u", strm->state); - ret = -EIO; - break; - } - - if (dir == I2S_DIR_TX) { - ret = i2s_tx_stream_start(dev_data, ssp, - dev_cfg->dev_dma); - } else { - ret = i2s_rx_stream_start(dev_data, ssp, - dev_cfg->dev_dma); - } - - if (ret < 0) { - LOG_DBG("START trigger failed %d", ret); - break; - } - - strm->state = I2S_STATE_RUNNING; - break; - - case I2S_TRIGGER_STOP: - case I2S_TRIGGER_DRAIN: - case I2S_TRIGGER_DROP: - if (strm->state != I2S_STATE_RUNNING) { - LOG_DBG("STOP/DRAIN/DROP trigger: invalid state"); - ret = -EIO; - break; - } - strm->state = I2S_STATE_STOPPING; - break; - - case I2S_TRIGGER_PREPARE: - break; - - default: - LOG_ERR("Unsupported trigger command"); - ret = -EINVAL; - } - - irq_unlock(key); - return ret; -} - -static int i2s_cavs_read(const struct device *dev, void **mem_block, - size_t *size) -{ - struct i2s_cavs_dev_data *const dev_data = dev->data; - struct stream *strm = &dev_data->rx; - void *buffer; - int ret = 0; - - if (strm->state == I2S_STATE_NOT_READY) { - LOG_ERR("invalid state %d", strm->state); - return -EIO; - } - - ret = k_msgq_get(&strm->out_queue, &buffer, - SYS_TIMEOUT_MS(dev_data->cfg.timeout)); - if (ret != 0) { - return -EAGAIN; - } - - *mem_block = buffer; - *size = dev_data->cfg.block_size; - return 0; -} - -static int i2s_cavs_write(const struct device *dev, void *mem_block, - size_t size) -{ - struct i2s_cavs_dev_data *const dev_data = dev->data; - struct stream *strm = &dev_data->tx; - int ret; - - if (strm->state != I2S_STATE_RUNNING && - strm->state != I2S_STATE_READY) { - LOG_ERR("invalid state (%d)", strm->state); - return -EIO; - } - - SOC_DCACHE_FLUSH(mem_block, size); - - ret = k_msgq_put(&strm->in_queue, &mem_block, - SYS_TIMEOUT_MS(dev_data->cfg.timeout)); - if (ret) { - LOG_ERR("k_msgq_put failed %d", ret); - return ret; - } - - return ret; -} - -/* clear IRQ sources atm */ -static void i2s_cavs_isr(const struct device *dev) -{ - const struct i2s_cavs_config *const dev_cfg = dev->config; - volatile struct i2s_cavs_ssp *const ssp = dev_cfg->regs; - struct i2s_cavs_dev_data *const dev_data = dev->data; - uint32_t status; - - /* clear interrupts */ - status = ssp->sss; - ssp->sss = status; - - if (status & SSSR_TUR) { - /* - * transmit underrun occurred. - * 1. disable transmission - * 2. disable underrun interrupt - */ - ssp->sstsa &= ~SSTSA_TXEN; - ssp->ssc0 |= SSCR0_TIM; - dev_data->tx.state = I2S_STATE_READY; - } -} - -static int i2s_cavs_initialize(const struct device *dev) -{ - const struct i2s_cavs_config *const dev_cfg = dev->config; - struct i2s_cavs_dev_data *const dev_data = dev->data; - - if (!device_is_ready(dev_cfg->dev_dma)) { - LOG_ERR("%s device not ready", dev_cfg->dev_dma->name); - return -ENODEV; - } - - /* Initialize the buffer queues */ - k_msgq_init(&dev_data->tx.in_queue, (char *)dev_data->tx.in_msgs, - sizeof(void *), I2S_CAVS_BUF_Q_LEN); - k_msgq_init(&dev_data->rx.in_queue, (char *)dev_data->rx.in_msgs, - sizeof(void *), I2S_CAVS_BUF_Q_LEN); - k_msgq_init(&dev_data->tx.out_queue, (char *)dev_data->tx.out_msgs, - sizeof(void *), I2S_CAVS_BUF_Q_LEN); - k_msgq_init(&dev_data->rx.out_queue, (char *)dev_data->rx.out_msgs, - sizeof(void *), I2S_CAVS_BUF_Q_LEN); - - /* register ISR */ - dev_cfg->irq_connect(); - - dev_data->tx.state = I2S_STATE_NOT_READY; - dev_data->rx.state = I2S_STATE_NOT_READY; - - LOG_INF("Device %s initialized", dev->name); - - return 0; -} - -static const struct i2s_driver_api i2s_cavs_driver_api = { - .configure = i2s_cavs_configure, - .read = i2s_cavs_read, - .write = i2s_cavs_write, - .trigger = i2s_cavs_trigger, -}; - -#define I2S_CAVS_DEVICE_INIT(n) \ - static void i2s_cavs_irq_connect_##n(void) \ - { \ - IRQ_CONNECT(DT_INST_IRQN(n), \ - DT_INST_IRQ(n, priority), \ - i2s_cavs_isr, \ - DEVICE_DT_INST_GET(n), 0); \ - \ - irq_enable(DT_INST_IRQN(n)); \ - } \ - \ - static const struct i2s_cavs_config i2s_cavs_config_##n = { \ - .regs = (struct i2s_cavs_ssp *) \ - DT_INST_REG_ADDR_BY_IDX(n, 0), \ - .mn_regs = (struct i2s_cavs_mn_div *) \ - DT_INST_REG_ADDR_BY_IDX(n, 1), \ - .irq_id = DT_INST_IRQN(n), \ - .irq_connect = i2s_cavs_irq_connect_##n, \ - .dev_dma = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, tx)),\ - }; \ - \ - static struct i2s_cavs_dev_data i2s_cavs_data_##n = { \ - .tx = { \ - .dma_channel = \ - DT_INST_DMAS_CELL_BY_NAME(n, tx, channel),\ - .dma_cfg = { \ - .source_burst_length = \ - CAVS_I2S_DMA_BURST_SIZE, \ - .dest_burst_length = \ - CAVS_I2S_DMA_BURST_SIZE, \ - .dma_callback = i2s_dma_tx_callback, \ - .user_data = \ - (void *)DEVICE_DT_INST_GET(n), \ - .complete_callback_en = 1, \ - .error_callback_en = 1, \ - .block_count = 1, \ - .head_block = \ - &i2s_cavs_data_##n.tx.dma_block,\ - .channel_direction = \ - MEMORY_TO_PERIPHERAL,\ - .dma_slot = \ - DT_INST_DMAS_CELL_BY_NAME(n, tx, channel),\ - }, \ - }, \ - .rx = { \ - .dma_channel = \ - DT_INST_DMAS_CELL_BY_NAME(n, rx, channel),\ - .dma_cfg = { \ - .source_burst_length = \ - CAVS_I2S_DMA_BURST_SIZE, \ - .dest_burst_length = \ - CAVS_I2S_DMA_BURST_SIZE, \ - .dma_callback = i2s_dma_rx_callback, \ - .user_data = \ - (void *)DEVICE_DT_INST_GET(n), \ - .complete_callback_en = 1, \ - .error_callback_en = 1, \ - .block_count = 1, \ - .head_block = \ - &i2s_cavs_data_##n.rx.dma_block,\ - .channel_direction = \ - PERIPHERAL_TO_MEMORY,\ - .dma_slot = \ - DT_INST_DMAS_CELL_BY_NAME(n, rx, channel),\ - }, \ - }, \ - }; \ - \ - DEVICE_DT_INST_DEFINE(n, \ - i2s_cavs_initialize, NULL, \ - &i2s_cavs_data_##n, \ - &i2s_cavs_config_##n, \ - POST_KERNEL, CONFIG_I2S_INIT_PRIORITY, \ - &i2s_cavs_driver_api); - -DT_INST_FOREACH_STATUS_OKAY(I2S_CAVS_DEVICE_INIT) diff --git a/drivers/i2s/i2s_cavs.h b/drivers/i2s/i2s_cavs.h deleted file mode 100644 index 2a234955c3588..0000000000000 --- a/drivers/i2s/i2s_cavs.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2018 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief I2S bus (SSP) driver for Intel CAVS. - * - * Limitations: - * - DMA is used in simple single block transfer mode (with linked list - * enabled) and "interrupt on full transfer completion" mode. - */ - -#ifndef ZEPHYR_DRIVERS_I2S_I2S_CAVS_H_ -#define ZEPHYR_DRIVERS_I2S_I2S_CAVS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -struct i2s_cavs_ssp { - uint32_t ssc0; /* 0x00 - Control0 */ - uint32_t ssc1; /* 0x04 - Control1 */ - uint32_t sss; /* 0x08 - Status */ - uint32_t ssit; /* 0x0C - Interrupt Test */ - uint32_t ssd; /* 0x10 - Data */ - uint32_t reserved0[5]; - uint32_t ssto; /* 0x28 - Time Out */ - uint32_t sspsp; /* 0x2C - Programmable Serial Protocol */ - uint32_t sstsa; /* 0x30 - TX Time Slot Active */ - uint32_t ssrsa; /* 0x34 - RX Time Slot Active */ - uint32_t sstss; /* 0x38 - Time Slot Status */ - uint32_t reserved1; - uint32_t ssc2; /* 0x40 - Command / Status 2 */ - uint32_t sspsp2; /* 0x44 - Programmable Serial Protocol 2 */ - uint32_t ssc3; /* 0x48 - Command / Status 3 */ - uint32_t ssioc; /* 0x4C - IO Control */ -}; - -/* SSCR0 bits */ -#define SSCR0_DSS_MASK (0x0000000f) -#define SSCR0_DSIZE(x) ((x) - 1) -#define SSCR0_FRF (0x00000030) -#define SSCR0_MOT (00 << 4) -#define SSCR0_TI (1 << 4) -#define SSCR0_NAT (2 << 4) -#define SSCR0_PSP (3 << 4) -#define SSCR0_ECS (1 << 6) -#define SSCR0_SSE (1 << 7) -#define SSCR0_SCR_MASK (0x000fff00) -#define SSCR0_SCR(x) ((x) << 8) -#define SSCR0_EDSS (1 << 20) -#define SSCR0_NCS (1 << 21) -#define SSCR0_RIM (1 << 22) -#define SSCR0_TIM (1 << 23) -#define SSCR0_FRDC(x) (((x) - 1) << 24) -#define SSCR0_ACS (1 << 30) -#define SSCR0_MOD (1 << 31) - -/* SSCR1 bits */ -#define SSCR1_RIE (1 << 0) -#define SSCR1_TIE (1 << 1) -#define SSCR1_LBM (1 << 2) -#define SSCR1_SPO (1 << 3) -#define SSCR1_SPH (1 << 4) -#define SSCR1_MWDS (1 << 5) -#define SSCR1_EFWR (1 << 14) -#define SSCR1_STRF (1 << 15) -#define SSCR1_IFS (1 << 16) -#define SSCR1_PINTE (1 << 18) -#define SSCR1_TINTE (1 << 19) -#define SSCR1_RSRE (1 << 20) -#define SSCR1_TSRE (1 << 21) -#define SSCR1_TRAIL (1 << 22) -#define SSCR1_RWOT (1 << 23) -#define SSCR1_SFRMDIR (1 << 24) -#define SSCR1_SCLKDIR (1 << 25) -#define SSCR1_ECRB (1 << 26) -#define SSCR1_ECRA (1 << 27) -#define SSCR1_SCFR (1 << 28) -#define SSCR1_EBCEI (1 << 29) -#define SSCR1_TTE (1 << 30) -#define SSCR1_TTELP (1 << 31) - -/* SSCR2 bits */ -#define SSCR2_TURM1 (1 << 1) -#define SSCR2_SDFD (1 << 14) -#define SSCR2_SDPM (1 << 16) -#define SSCR2_LJDFD (1 << 17) - -/* SSR bits */ -#define SSSR_TNF (1 << 2) -#define SSSR_RNE (1 << 3) -#define SSSR_BSY (1 << 4) -#define SSSR_TFS (1 << 5) -#define SSSR_RFS (1 << 6) -#define SSSR_ROR (1 << 7) -#define SSSR_TUR (1 << 21) - -/* SSPSP bits */ -#define SSPSP_SCMODE(x) ((x) << 0) -#define SSPSP_SFRMP(x) ((x) << 2) -#define SSPSP_ETDS (1 << 3) -#define SSPSP_STRTDLY(x) ((x) << 4) -#define SSPSP_DMYSTRT(x) ((x) << 7) -#define SSPSP_SFRMDLY(x) ((x) << 9) -#define SSPSP_SFRMWDTH(x) ((x) << 16) -#define SSPSP_DMYSTOP(x) ((x) << 23) -#define SSPSP_FSRT (1 << 25) -#define SSPSP_EDMYSTOP(x) ((x) << 26) - -/* SSTSA bits */ -#define SSTSA_TTSA(x) (1 << x) -#define SSTSA_TXEN (1 << 8) - -/* SSRSA bits */ -#define SSRSA_RTSA(x) (1 << x) -#define SSRSA_RXEN (1 << 8) - -/* SSCR3 bits */ -#define SSCR3_TFL_MASK (0x0000003f) -#define SSCR3_RFL_MASK (0x00003f00) -#define SSCR3_TFT_MASK (0x003f0000) -#define SSCR3_TX(x) (((x) - 1) << 16) -#define SSCR3_RFT_MASK (0x3f000000) -#define SSCR3_RX(x) (((x) - 1) << 24) - -/* SSIOC bits */ -#define SSIOC_TXDPDEB (1 << 1) -#define SSIOC_SFCR (1 << 4) -#define SSIOC_SCOE (1 << 5) - -struct i2s_cavs_mn_div { - uint32_t mval; /* 0x00 - M value */ - uint32_t nval; /* 0x04 - N value */ -}; - -/* MVAL & NVAL bits */ -#define I2S_MNVAL_MASK (BIT_MASK(24)) -#define I2S_MNVAL(x) ((x) & I2S_MNVAL_MASK) - -#ifdef __cplusplus -} -#endif - -#endif /* ZEPHYR_DRIVERS_I2S_I2S_CAVS_H_ */ diff --git a/soc/xtensa/intel_adsp/Kconfig.defconfig b/soc/xtensa/intel_adsp/Kconfig.defconfig index f697aa953af47..0911b38a21d2d 100644 --- a/soc/xtensa/intel_adsp/Kconfig.defconfig +++ b/soc/xtensa/intel_adsp/Kconfig.defconfig @@ -23,10 +23,6 @@ config DMA_CAVS_HDA default y depends on DMA -config I2S_CAVS - default y - depends on I2S - config XTENSA_CCOUNT_HZ default 400000000 if SOC_SERIES_INTEL_CAVS_V25 default 200000000 diff --git a/soc/xtensa/intel_adsp/common/include/soc.h b/soc/xtensa/intel_adsp/common/include/soc.h index 7583968ed1cc3..f86862c06871f 100644 --- a/soc/xtensa/intel_adsp/common/include/soc.h +++ b/soc/xtensa/intel_adsp/common/include/soc.h @@ -44,15 +44,6 @@ #define IOAPIC_EDGE 0 #define IOAPIC_HIGH 0 -/* I2S */ -#define I2S_CAVS_IRQ(i2s_num) \ - SOC_AGGREGATE_IRQ(0, (i2s_num), CAVS_L2_AGG_INT_LEVEL5) - -#define I2S0_CAVS_IRQ I2S_CAVS_IRQ(0) -#define I2S1_CAVS_IRQ I2S_CAVS_IRQ(1) -#define I2S2_CAVS_IRQ I2S_CAVS_IRQ(2) -#define I2S3_CAVS_IRQ I2S_CAVS_IRQ(3) - #define SSP_MN_DIV_SIZE (8) #define SSP_MN_DIV_BASE(x) \ (0x00078D00 + ((x) * SSP_MN_DIV_SIZE)) From f15993e150ab172387bf3b87f716edc9a3928ad7 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 13 Jun 2022 14:28:00 -0400 Subject: [PATCH 6/8] pinmux: remove s1000 i2s driver Remove intel_s1000_crb pinmux driver. The board is no longer available or supported in the zephyr tree. Signed-off-by: Anas Nashif --- drivers/pinmux/CMakeLists.txt | 1 - drivers/pinmux/Kconfig | 2 - drivers/pinmux/Kconfig.intel_s1000 | 8 --- drivers/pinmux/pinmux_intel_s1000.c | 98 ----------------------------- 4 files changed, 109 deletions(-) delete mode 100644 drivers/pinmux/Kconfig.intel_s1000 delete mode 100644 drivers/pinmux/pinmux_intel_s1000.c diff --git a/drivers/pinmux/CMakeLists.txt b/drivers/pinmux/CMakeLists.txt index 5f94a64566f10..ea933182b38d3 100644 --- a/drivers/pinmux/CMakeLists.txt +++ b/drivers/pinmux/CMakeLists.txt @@ -1,7 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 # Board initialization -zephyr_sources_ifdef(CONFIG_PINMUX_INTEL_S1000 pinmux_intel_s1000.c) zephyr_sources_ifdef(CONFIG_PINMUX_LPC11U6X pinmux_lpc11u6x.c) zephyr_sources_ifdef(CONFIG_PINMUX_MCUX pinmux_mcux.c) zephyr_sources_ifdef(CONFIG_PINMUX_MCUX_LPC pinmux_mcux_lpc.c) diff --git a/drivers/pinmux/Kconfig b/drivers/pinmux/Kconfig index dbe1693c068d8..d0537a9901b31 100644 --- a/drivers/pinmux/Kconfig +++ b/drivers/pinmux/Kconfig @@ -26,8 +26,6 @@ config PINMUX_INIT_PRIORITY source "drivers/pinmux/Kconfig.beetle" -source "drivers/pinmux/Kconfig.intel_s1000" - source "drivers/pinmux/Kconfig.lpc11u6x" source "drivers/pinmux/Kconfig.mcux" diff --git a/drivers/pinmux/Kconfig.intel_s1000 b/drivers/pinmux/Kconfig.intel_s1000 deleted file mode 100644 index e4ca26d73a6d4..0000000000000 --- a/drivers/pinmux/Kconfig.intel_s1000 +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2018 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config PINMUX_INTEL_S1000 - bool "Intel S1000 I/O multiplexer driver" - depends on SOC_INTEL_S1000 - help - Enable driver for Intel S1000 I/O multiplexer. diff --git a/drivers/pinmux/pinmux_intel_s1000.c b/drivers/pinmux/pinmux_intel_s1000.c deleted file mode 100644 index 5d7a0a7831d55..0000000000000 --- a/drivers/pinmux/pinmux_intel_s1000.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2018 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT intel_s1000_pinmux - -#include -#include -#include - -static volatile uint32_t *iomux_ctrl_regs = (volatile uint32_t *)DT_INST_REG_ADDR(0); - -#define PINMUX_CTRL_REG_COUNT (DT_INST_REG_SIZE(0) / 4) - -static int pinmux_set(const struct device *dev, uint32_t pin, uint32_t func) -{ - uint32_t lsb, msb; - uint32_t index; - uint32_t value; - uint32_t mask; - - /* retrieve control register index */ - index = IOMUX_INDEX(pin); - - /* - * retrieve the least and most significant bit positions for - * the pin group - */ - lsb = IOMUX_LSB(pin); - msb = IOMUX_MSB(pin); - - if ((index >= PINMUX_CTRL_REG_COUNT) || (msb > 31) || (lsb > msb)) { - return -EINVAL; - } - - mask = BIT_MASK(msb - lsb + 1) << lsb; - value = (func << lsb) & mask; - - iomux_ctrl_regs[index] = (iomux_ctrl_regs[index] & ~mask) | value; - - return 0; -} - -static int pinmux_get(const struct device *dev, uint32_t pin, uint32_t *func) -{ - uint32_t lsb, msb; - uint32_t index; - uint32_t mask; - - /* retrieve control register index */ - index = IOMUX_INDEX(pin); - - /* - * retrieve the least and most significant bit positions for - * the pin group - */ - lsb = IOMUX_LSB(pin); - msb = IOMUX_MSB(pin); - - if ((index >= PINMUX_CTRL_REG_COUNT) || (msb > 31) || (lsb > msb) || - (func == NULL)) { - return -EINVAL; - } - - mask = BIT_MASK(msb - lsb + 1); - - *func = (iomux_ctrl_regs[index] >> lsb) & mask; - - return 0; -} - -static int pinmux_pullup(const struct device *dev, uint32_t pin, uint8_t func) -{ - return -ENOTSUP; -} - -static int pinmux_input(const struct device *dev, uint32_t pin, uint8_t func) -{ - return -ENOTSUP; -} - -static struct pinmux_driver_api apis = { - .set = pinmux_set, - .get = pinmux_get, - .pullup = pinmux_pullup, - .input = pinmux_input -}; - -static int pinmux_init(const struct device *dev) -{ - ARG_UNUSED(dev); - return 0; -} - -DEVICE_DT_INST_DEFINE(0, &pinmux_init, NULL, NULL, NULL, - PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY, &apis); From e5fbeb84e855bcb21ed5f2fbd650031047e86dc7 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 13 Jun 2022 14:28:32 -0400 Subject: [PATCH 7/8] MAINTAINERS: remove s1000 references Remove intel_s1000_crb entries. The board is no longer available or supported in the zephyr tree. Signed-off-by: Anas Nashif --- CODEOWNERS | 4 ---- MAINTAINERS.yml | 1 - 2 files changed, 5 deletions(-) diff --git a/CODEOWNERS b/CODEOWNERS index f7a183e0c122b..1bb074964f7b8 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -59,7 +59,6 @@ /soc/arm/xilinx_zynq7000/ @ibirnbaum /soc/arm/xilinx_zynqmp/ @stephanosio /soc/arm/renesas_rcar/ @aaillet @pmarzin -/soc/xtensa/intel_s1000/ @sathishkuttan @dcpleung /soc/arm64/ @carlocaione /soc/arm64/qemu_cortex_a53/ @carlocaione /soc/arm64/bcm_vk/ @abhishek-brcm @@ -177,7 +176,6 @@ /boards/x86/ @dcpleung @nashif @jenmwms @aasthagr /boards/x86/acrn/ @enjiamai /boards/xtensa/ @nashif @dcpleung -/boards/xtensa/intel_s1000_crb/ @sathishkuttan @dcpleung /boards/xtensa/odroid_go/ @ydamigos /boards/xtensa/nxp_adsp_imx8/ @iuliana-prodan @dbaluta /boards/sparc/ @martin-aberg @@ -651,7 +649,6 @@ /samples/basic/minimal/ @carlescufi /samples/basic/servo_motor/boards/*microbit* @jhe /samples/bluetooth/ @jhedberg @Vudentz @alwa-nordic @sjanc -/samples/boards/intel_s1000_crb/ @sathishkuttan @dcpleung @nashif /samples/compression/ @Navin-Sankar /samples/drivers/can/ @alexanderwachter @henrikbrixandersen /samples/drivers/clock_control_litex/ @mateusz-holenko @kgugala @pgielda @@ -786,7 +783,6 @@ scripts/gen_image_info.py @tejlmand /tests/arch/arm/ @ioannisg @stephanosio /tests/benchmarks/cmsis_dsp/ @stephanosio /tests/boards/native_posix/ @aescolar @daor-oti -/tests/boards/intel_s1000_crb/ @dcpleung @sathishkuttan /tests/bluetooth/ @alwa-nordic @jhedberg @Vudentz @sjanc /tests/bluetooth/controller/ @cvinayak @thoh-ot @kruithofa @erbr-ot @sjanc @ppryga /tests/bluetooth/bsim_bt/ @alwa-nordic @jhedberg @Vudentz @wopu-ot diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index b341730654ccc..9eca5851a69c6 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -1642,7 +1642,6 @@ Intel Platforms (Xtensa): files: - boards/xtensa/intel_*/ - soc/xtensa/intel_*/ - - samples/boards/intel_s1000_crb/ labels: - "platform: Intel CAVS" From 9dcfa429f5cdb178dd64311c83e8d5ede8d09752 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 13 Jun 2022 14:29:20 -0400 Subject: [PATCH 8/8] drivers: ipm/spi/intc: remove Intel S1000 support Remove intel_s1000_crb support. The board is no longer available or supported in the zephyr tree. Signed-off-by: Anas Nashif --- drivers/interrupt_controller/intc_cavs.c | 4 +--- drivers/ipm/ipm_cavs_idc.c | 5 ----- drivers/ipm/ipm_cavs_idc.h | 2 -- drivers/spi/spi_dw.h | 6 +----- 4 files changed, 2 insertions(+), 15 deletions(-) diff --git a/drivers/interrupt_controller/intc_cavs.c b/drivers/interrupt_controller/intc_cavs.c index 3ebd676e9fd0c..8395dd13cc846 100644 --- a/drivers/interrupt_controller/intc_cavs.c +++ b/drivers/interrupt_controller/intc_cavs.c @@ -11,9 +11,7 @@ #include "intc_cavs.h" #if defined(CONFIG_SMP) && (CONFIG_MP_NUM_CPUS > 1) -#if defined(CONFIG_SOC_INTEL_S1000) -#define PER_CPU_OFFSET(x) (0x40 * x) -#elif defined(CONFIG_SOC_SERIES_INTEL_CAVS_V15) +#if defined(CONFIG_SOC_SERIES_INTEL_CAVS_V15) #define PER_CPU_OFFSET(x) (0x40 * x) #elif defined(CONFIG_SOC_SERIES_INTEL_CAVS_V18) #define PER_CPU_OFFSET(x) (0x40 * x) diff --git a/drivers/ipm/ipm_cavs_idc.c b/drivers/ipm/ipm_cavs_idc.c index dd402862f7900..922ad302c69ea 100644 --- a/drivers/ipm/ipm_cavs_idc.c +++ b/drivers/ipm/ipm_cavs_idc.c @@ -13,11 +13,6 @@ #include #include - -#ifdef CONFIG_SOC_INTEL_S1000 -#include -#endif - #include "ipm_cavs_idc.h" #ifdef CONFIG_SCHED_IPI_SUPPORTED diff --git a/drivers/ipm/ipm_cavs_idc.h b/drivers/ipm/ipm_cavs_idc.h index 620d93fcc2886..ce6d1de1ebf54 100644 --- a/drivers/ipm/ipm_cavs_idc.h +++ b/drivers/ipm/ipm_cavs_idc.h @@ -10,7 +10,6 @@ /* Redeclaration of the earlier IDC register API for platforms being * held back on this driver. */ -#ifndef CONFIG_SOC_INTEL_S1000 # ifndef IPC_DSP_BASE # define IPC_DSP_BASE(core) (DT_REG_ADDR(DT_NODELABEL(idc)) + 0x80 * (core)) # endif @@ -27,7 +26,6 @@ #define IPC_IDCIETC_DONE BIT(30) #define IPC_IDCCTL 0x50 #define IPC_IDCCTL_IDCTBIE(x) BIT(x) -#endif #define IPM_CAVS_IDC_ID_MASK \ (CAVS_IDC_TYPE(CAVS_IDC_TYPE_MASK) | \ diff --git a/drivers/spi/spi_dw.h b/drivers/spi/spi_dw.h index ad4b28a309eb9..f7b9e4fa86fcc 100644 --- a/drivers/spi/spi_dw.h +++ b/drivers/spi/spi_dw.h @@ -97,11 +97,7 @@ struct spi_dw_data { #define DW_SPI_CTRLR0_SLV_OE_BIT (10) #define DW_SPI_CTRLR0_SLV_OE BIT(DW_SPI_CTRLR0_SLV_OE_BIT) -#ifdef CONFIG_SOC_INTEL_S1000 -#define DW_SPI_CTRLR0_TMOD_SHIFT (10) -#else #define DW_SPI_CTRLR0_TMOD_SHIFT (8) -#endif #define DW_SPI_CTRLR0_TMOD_TX_RX (0) #define DW_SPI_CTRLR0_TMOD_TX (1 << DW_SPI_CTRLR0_TMOD_SHIFT) @@ -112,7 +108,7 @@ struct spi_dw_data { #define DW_SPI_CTRLR0_DFS_16(__bpw) ((__bpw) - 1) #define DW_SPI_CTRLR0_DFS_32(__bpw) (((__bpw) - 1) << 16) -#if defined(CONFIG_ARC) || defined(CONFIG_SOC_INTEL_S1000) +#if defined(CONFIG_ARC) #define DW_SPI_CTRLR0_DFS DW_SPI_CTRLR0_DFS_16 #else #define DW_SPI_CTRLR0_DFS DW_SPI_CTRLR0_DFS_32