diff --git a/boards/arm/gd32f403z_eval/Kconfig.board b/boards/arm/gd32f403z_eval/Kconfig.board
index 61733d3bf9714..97273a13f995a 100644
--- a/boards/arm/gd32f403z_eval/Kconfig.board
+++ b/boards/arm/gd32f403z_eval/Kconfig.board
@@ -3,4 +3,4 @@
 
 config BOARD_GD32F403Z_EVAL
 	bool "GigaDevice GD32F403Z Evaluation Kit"
-	depends on SOC_GD32F403Z
+	depends on SOC_GD32F403
diff --git a/boards/arm/gd32f403z_eval/gd32f403z_eval.dts b/boards/arm/gd32f403z_eval/gd32f403z_eval.dts
index 86393b16d60c1..6dda970076793 100644
--- a/boards/arm/gd32f403z_eval/gd32f403z_eval.dts
+++ b/boards/arm/gd32f403z_eval/gd32f403z_eval.dts
@@ -5,7 +5,7 @@
 
 /dts-v1/;
 
-#include <gigadevice/gd32f403zet6.dtsi>
+#include <gigadevice/gd32f403/gd32f403zet6.dtsi>
 
 / {
 	model = "GigaDevice GD32F403Z Evaluation Kit";
diff --git a/boards/arm/gd32f403z_eval/gd32f403z_eval_defconfig b/boards/arm/gd32f403z_eval/gd32f403z_eval_defconfig
index f5b70d6a48610..245a7e3307dbd 100644
--- a/boards/arm/gd32f403z_eval/gd32f403z_eval_defconfig
+++ b/boards/arm/gd32f403z_eval/gd32f403z_eval_defconfig
@@ -1,8 +1,8 @@
 # Copyright (c) 2021, ATL Electronics
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_SERIES_GD32F4=y
-CONFIG_SOC_GD32F403Z=y
+CONFIG_SOC_SERIES_GD32F403=y
+CONFIG_SOC_GD32F403=y
 CONFIG_BOARD_GD32F403Z_EVAL=y
 
 CONFIG_ARM_MPU=y
diff --git a/boards/arm/gd32f450i_eval/CMakeLists.txt b/boards/arm/gd32f450i_eval/CMakeLists.txt
new file mode 100644
index 0000000000000..abca855a4b82a
--- /dev/null
+++ b/boards/arm/gd32f450i_eval/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright (c) 2021, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+zephyr_library_sources(board.c)
diff --git a/boards/arm/gd32f450i_eval/Kconfig b/boards/arm/gd32f450i_eval/Kconfig
new file mode 100644
index 0000000000000..ec5800eae978d
--- /dev/null
+++ b/boards/arm/gd32f450i_eval/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_INIT_PRIORITY
+	int "Board initialization priority"
+	default 50
+	help
+	  Board initialization priority.
diff --git a/boards/arm/gd32f450i_eval/Kconfig.board b/boards/arm/gd32f450i_eval/Kconfig.board
new file mode 100644
index 0000000000000..257da26fd035c
--- /dev/null
+++ b/boards/arm/gd32f450i_eval/Kconfig.board
@@ -0,0 +1,6 @@
+# Copyright (c) 2021, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_GD32F450I_EVAL
+	bool "GigaDevice GD32F450I-EVAL"
+	depends on SOC_GD32F450
diff --git a/boards/arm/gd32f450i_eval/Kconfig.defconfig b/boards/arm/gd32f450i_eval/Kconfig.defconfig
new file mode 100644
index 0000000000000..3d7624c751e5d
--- /dev/null
+++ b/boards/arm/gd32f450i_eval/Kconfig.defconfig
@@ -0,0 +1,9 @@
+# Copyright (c) 2021 Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_GD32F450I_EVAL
+
+config BOARD
+	default "gd32f450i_eval"
+
+endif # BOARD_GD32F450I_EVAL
diff --git a/boards/arm/gd32f450i_eval/board.c b/boards/arm/gd32f450i_eval/board.c
new file mode 100644
index 0000000000000..28555ee344c73
--- /dev/null
+++ b/boards/arm/gd32f450i_eval/board.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2021, Teslabs Engineering S.L.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <init.h>
+
+static int board_init(const struct device *dev)
+{
+	rcu_periph_clock_enable(RCU_GPIOA);
+
+	/* PA9: USART0 TX */
+	gpio_af_set(GPIOA, GPIO_AF_7, GPIO_PIN_9);
+	gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_9);
+	gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, GPIO_PIN_9);
+
+	/* PA10: USART0 RX */
+	gpio_af_set(GPIOA, GPIO_AF_7, GPIO_PIN_10);
+	gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_10);
+	gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, GPIO_PIN_10);
+
+	rcu_periph_clock_disable(RCU_GPIOA);
+
+	return 0;
+}
+
+SYS_INIT(board_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);
diff --git a/boards/arm/gd32f450i_eval/board.cmake b/boards/arm/gd32f450i_eval/board.cmake
new file mode 100644
index 0000000000000..8460d86406bde
--- /dev/null
+++ b/boards/arm/gd32f450i_eval/board.cmake
@@ -0,0 +1,4 @@
+# Copyright (c) 2021, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/arm/gd32f450i_eval/doc/img/gd32f450i_eval.png b/boards/arm/gd32f450i_eval/doc/img/gd32f450i_eval.png
new file mode 100644
index 0000000000000..0fe5f3aed2c51
Binary files /dev/null and b/boards/arm/gd32f450i_eval/doc/img/gd32f450i_eval.png differ
diff --git a/boards/arm/gd32f450i_eval/doc/index.rst b/boards/arm/gd32f450i_eval/doc/index.rst
new file mode 100644
index 0000000000000..105ffca21f8f5
--- /dev/null
+++ b/boards/arm/gd32f450i_eval/doc/index.rst
@@ -0,0 +1,146 @@
+.. _gd32f450i_eval:
+
+GigaDevice GD32F450I-EVAL
+#########################
+
+Overview
+********
+
+The GD32F450I-EVAL board is a hardware platform that enables prototyping
+on GD32F450IK Cortex-M4F Stretch Performance MCU.
+
+The GD32F450IK features a single-core ARM Cortex-M4F MCU which can run up
+to 200 MHz with flash accesses zero wait states, 3072kiB of Flash, 256kiB of
+SRAM and 140 GPIOs.
+
+.. image:: img/gd32f450i_eval.png
+     :align: center
+     :alt: gd32f450i_eval
+
+
+Hardware
+********
+
+- GD32F450IKT6 MCU
+- AT24C02C 2Kb EEPROM
+- GD25Q32C 16Mbit SPI and QSPI NOR Flash
+- GD9FS1G8F2A 1Gbit NAND Flash
+- Micron MT48LC16M16A2P-6AIT 256Mbit SDRAM
+- 3 x User LEDs
+- 3 x User Push buttons
+- 1 x USART (RS-232 at J1 connector)
+- 1 x POT connected to an ADC input
+- Headphone interface
+- Micro SD Card Interface
+- USB FS connector
+- USB HS connector
+- 1 x CAN
+- Ethernet Interface
+- 3.5" RGB-LCD (320x480)
+- OV2640 Digital Camera
+- GD-Link on board programmer
+- J-Link/JTAG connector
+
+For more information about the GD32F450 SoC and GD32F450I-EVAL board:
+
+- `GigaDevice Cortex-M4F Stretch Performance SoC Website`_
+- `GD32F450xx Datasheet`_
+- `GD32F4xx User Manual`_
+- `GD32F450I-EVAL User Manual`_
+
+Supported Features
+==================
+
+The board configuration supports the following hardware features:
+
+.. list-table::
+   :header-rows: 1
+
+   * - Peripheral
+     - Kconfig option
+     - Devicetree compatible
+   * - NVIC
+     - N/A
+     - :dtcompatible:`arm,v7m-nvic`
+   * - SYSTICK
+     - N/A
+     - N/A
+   * - USART
+     - :kconfig:`CONFIG_SERIAL`
+     - :dtcompatible:`gd,gd32-usart`
+
+Serial Port
+===========
+
+The GD32F450I-EVAL board has one serial communication port. The default port
+is USART0 with TX connected at PA9 and RX at PA10.
+
+Programming and Debugging
+*************************
+
+Before programming your board make sure to configure boot and serial jumpers
+as follows:
+
+- J2/3: Select 2-3 for both (boot from user memory)
+- J5: Select 1-2 position (labeled as ``USART0``)
+
+Using GD-Link
+=============
+
+The GD32F450I-EVAL includes an onboard programmer/debugger (GD-Link) which
+allows flash programming and debugging over USB. There is also a JTAG header
+(J1) which can be used with tools like Segger J-Link.
+
+#. Build the Zephyr kernel and the :ref:`hello_world` sample application:
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/hello_world
+      :board: gd32f450i_eval
+      :goals: build
+      :compact:
+
+#. Run your favorite terminal program to listen for output. On Linux the
+   terminal should be something like ``/dev/ttyUSB0``. For example:
+
+   .. code-block:: console
+
+      minicom -D /dev/ttyUSB0 -o
+
+   The -o option tells minicom not to send the modem initialization
+   string. Connection should be configured as follows:
+
+      - Speed: 115200
+      - Data: 8 bits
+      - Parity: None
+      - Stop bits: 1
+
+#. To flash an image:
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/hello_world
+      :board: gd32f450i_eval
+      :goals: flash
+      :compact:
+
+   You should see "Hello World! gd32f450i_eval" in your terminal.
+
+#. To debug an image:
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/hello_world
+      :board: gd32f450i_eval
+      :goals: debug
+      :compact:
+
+
+.. _GigaDevice Cortex-M4F Stretch Performance SoC Website:
+   https://www.gigadevice.com/products/microcontrollers/gd32/arm-cortex-m4/stretch-performance-line/
+
+.. _GD32F450xx Datasheet:
+	https://gd32mcu.21ic.com/data/documents/shujushouce/GD32F450xx_Datasheet_Rev1.1.pdf
+
+.. _GD32F4xx User Manual:
+	https://www.gigadevice.com/manual/gd32f450xxxx-user-manual/
+
+.. _GD32F450I-EVAL User Manual:
+	http://www.gd32mcu.com/download/down/document_id/120/path_type/1
diff --git a/boards/arm/gd32f450i_eval/gd32f450i_eval.dts b/boards/arm/gd32f450i_eval/gd32f450i_eval.dts
new file mode 100644
index 0000000000000..56d6757461cf0
--- /dev/null
+++ b/boards/arm/gd32f450i_eval/gd32f450i_eval.dts
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2021, Teslabs Engineering S.L.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <gigadevice/gd32f4xx/gd32f450ik.dtsi>
+
+/ {
+	model = "GigaDevice GD32F450I-EVAL";
+	compatible = "gd,gd32f450i-eval";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &usart0;
+		zephyr,shell-uart = &usart0;
+	};
+};
+
+&usart0 {
+	status = "okay";
+	current-speed = <115200>;
+};
diff --git a/boards/arm/gd32f450i_eval/gd32f450i_eval.yaml b/boards/arm/gd32f450i_eval/gd32f450i_eval.yaml
new file mode 100644
index 0000000000000..af628d8cf6e8d
--- /dev/null
+++ b/boards/arm/gd32f450i_eval/gd32f450i_eval.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2021, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: gd32f450i_eval
+name: GigaDevice GD32F450I-EVAL
+type: mcu
+arch: arm
+ram: 112
+flash: 3072
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
diff --git a/boards/arm/gd32f450i_eval/gd32f450i_eval_defconfig b/boards/arm/gd32f450i_eval/gd32f450i_eval_defconfig
new file mode 100644
index 0000000000000..73a959c4ccad4
--- /dev/null
+++ b/boards/arm/gd32f450i_eval/gd32f450i_eval_defconfig
@@ -0,0 +1,14 @@
+# Copyright (c) 2021, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_GD32F4XX=y
+CONFIG_SOC_GD32F450=y
+CONFIG_BOARD_GD32F450I_EVAL=y
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+CONFIG_CORTEX_M_SYSTICK=y
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
diff --git a/boards/arm/gd32f450i_eval/support/openocd.cfg b/boards/arm/gd32f450i_eval/support/openocd.cfg
new file mode 100644
index 0000000000000..f40472e06da3b
--- /dev/null
+++ b/boards/arm/gd32f450i_eval/support/openocd.cfg
@@ -0,0 +1,25 @@
+# Copyright (c) 2021, ATL-Electronics
+# Copyright (c) 2021, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+source [find interface/cmsis-dap.cfg]
+transport select swd
+
+set CHIPNAME gd32f450ik
+set CPUTAPID 0x790007a3
+
+source [find target/stm32f4x.cfg]
+
+reset_config trst_and_srst separate
+
+$_TARGETNAME configure -event gdb-attach {
+	echo "Debugger attaching: halting execution"
+	reset halt
+	gdb_breakpoint_override hard
+}
+
+$_TARGETNAME configure -event gdb-detach {
+	echo "Debugger detaching: resuming execution"
+	resume
+}
+
diff --git a/dts/arm/gigadevice/gd32f403.dtsi b/dts/arm/gigadevice/gd32f403/gd32f403.dtsi
similarity index 100%
rename from dts/arm/gigadevice/gd32f403.dtsi
rename to dts/arm/gigadevice/gd32f403/gd32f403.dtsi
diff --git a/dts/arm/gigadevice/gd32f403zet6.dtsi b/dts/arm/gigadevice/gd32f403/gd32f403zet6.dtsi
similarity index 86%
rename from dts/arm/gigadevice/gd32f403zet6.dtsi
rename to dts/arm/gigadevice/gd32f403/gd32f403zet6.dtsi
index c96e65a40794c..36a2862c5804e 100644
--- a/dts/arm/gigadevice/gd32f403zet6.dtsi
+++ b/dts/arm/gigadevice/gd32f403/gd32f403zet6.dtsi
@@ -5,7 +5,7 @@
  */
 
 #include <mem.h>
-#include <gigadevice/gd32f403.dtsi>
+#include <gigadevice/gd32f403/gd32f403.dtsi>
 
 / {
 	soc {
diff --git a/dts/arm/gigadevice/gd32f4xx/gd32f450ik.dtsi b/dts/arm/gigadevice/gd32f4xx/gd32f450ik.dtsi
new file mode 100644
index 0000000000000..52b99098f096c
--- /dev/null
+++ b/dts/arm/gigadevice/gd32f4xx/gd32f450ik.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2021 Teslabs Engineering S.L.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <gigadevice/gd32f4xx/gd32f4xx.dtsi>
+
+/ {
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(3072)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi b/dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi
new file mode 100644
index 0000000000000..6dd0d177dd9a1
--- /dev/null
+++ b/dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2021, Teslabs Engineering S.L.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv7m-mpu";
+				reg = <0xe000ed90 0x40>;
+				arm,num-mpu-regions = <8>;
+			};
+		};
+	};
+
+	soc {
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(112)>;
+		};
+
+		fmc: flash-controller@40023c00 {
+			compatible = "gd,gd32-flash-controller";
+			label = "FMC";
+			reg = <0x40023c00 0x400>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "soc-nv-flash";
+				label = "FLASH0";
+			};
+		};
+
+		usart0: usart@40011000 {
+			compatible = "gd,gd32-usart";
+			reg = <0x40011000 0x400>;
+			rcu-periph-clock = <0x1104>;
+			status = "disabled";
+			label = "USART0";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/modules/hal_gigadevice/CMakeLists.txt b/modules/hal_gigadevice/CMakeLists.txt
index 822c2d7ff6b6b..ae3abd3bc5d3b 100644
--- a/modules/hal_gigadevice/CMakeLists.txt
+++ b/modules/hal_gigadevice/CMakeLists.txt
@@ -3,48 +3,53 @@
 
 if(CONFIG_HAS_GD32_HAL)
 
-zephyr_library_named(hal_gigadevice)
-
-if(CONFIG_SOC_SERIES_GD32F403)
-  set(gd32_soc_uc GD32F403)
-  set(gd32_soc_lc gd32f403)
-endif()
-
-zephyr_library_compile_definitions(${gd32_soc_uc})
+string(TOUPPER ${CONFIG_SOC_SERIES} gd32_soc_series_uc)
+string(TOUPPER ${CONFIG_SOC} gd32_soc_uc)
 
-set(gd32_soc_dir     ${ZEPHYR_HAL_GIGADEVICE_MODULE_DIR}/${gd32_soc_uc})
-set(gd32_cmsis_dir   ${gd32_soc_dir}/CMSIS/GD/${gd32_soc_uc})
+set(gd32_soc_dir     ${ZEPHYR_HAL_GIGADEVICE_MODULE_DIR}/${gd32_soc_series_uc})
+set(gd32_cmsis_dir   ${gd32_soc_dir}/CMSIS/GD/${gd32_soc_series_uc})
 set(gd32_std_dir     ${gd32_soc_dir}/standard_peripheral)
 set(gd32_std_src_dir ${gd32_std_dir}/Source)
 
+zephyr_library_named(hal_gigadevice)
+
+zephyr_compile_definitions(${gd32_soc_uc})
+
 # Global includes to be used outside hal_gigadevice
 zephyr_include_directories(${gd32_cmsis_dir}/Include)
 zephyr_include_directories(${gd32_std_dir}/Include)
 
-zephyr_library_sources(${gd32_cmsis_dir}/Source/system_${gd32_soc_lc}.c)
-
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_ADC   ${gd32_std_src_dir}/${gd32_soc_lc}_adc.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_BKP   ${gd32_std_src_dir}/${gd32_soc_lc}_bkp.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_CAN   ${gd32_std_src_dir}/${gd32_soc_lc}_can.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_CRC   ${gd32_std_src_dir}/${gd32_soc_lc}_crc.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_CTC   ${gd32_std_src_dir}/${gd32_soc_lc}_ctc.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_DAC   ${gd32_std_src_dir}/${gd32_soc_lc}_dac.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_DBG   ${gd32_std_src_dir}/${gd32_soc_lc}_dbg.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_DMA   ${gd32_std_src_dir}/${gd32_soc_lc}_dma.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_EXMC  ${gd32_std_src_dir}/${gd32_soc_lc}_exmc.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_EXTI  ${gd32_std_src_dir}/${gd32_soc_lc}_exti.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_FMC   ${gd32_std_src_dir}/${gd32_soc_lc}_fmc.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_FWDGT ${gd32_std_src_dir}/${gd32_soc_lc}_fwdgt.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_GPIO  ${gd32_std_src_dir}/${gd32_soc_lc}_gpio.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_I2C   ${gd32_std_src_dir}/${gd32_soc_lc}_i2c.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_MISC  ${gd32_std_src_dir}/${gd32_soc_lc}_misc.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_PMU   ${gd32_std_src_dir}/${gd32_soc_lc}_pmu.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_RCU   ${gd32_std_src_dir}/${gd32_soc_lc}_rcu.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_RTC   ${gd32_std_src_dir}/${gd32_soc_lc}_rtc.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_SDIO  ${gd32_std_src_dir}/${gd32_soc_lc}_sdio.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_SPI   ${gd32_std_src_dir}/${gd32_soc_lc}_spi.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_TIMER ${gd32_std_src_dir}/${gd32_soc_lc}_timer.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_USART ${gd32_std_src_dir}/${gd32_soc_lc}_usart.c)
-zephyr_library_sources_ifdef(CONFIG_USE_GD32_WWDGT ${gd32_std_src_dir}/${gd32_soc_lc}_wwdgt.c)
+zephyr_library_sources(${gd32_cmsis_dir}/Source/system_${CONFIG_SOC_SERIES}.c)
+
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_ADC    ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_adc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_BKP    ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_bkp.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_CAN    ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_can.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_CRC    ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_crc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_CTC    ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_ctc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_DAC    ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_dac.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_DBG    ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_dbg.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_DCI    ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_dci.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_DMA    ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_dma.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_ENET   ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_enet.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_EXMC   ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_exmc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_EXTI   ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_exti.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_FMC    ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_fmc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_FWDGT  ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_fwdgt.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_GPIO   ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_gpio.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_I2C    ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_i2c.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_IPA    ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_ipa.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_IREF   ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_iref.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_MISC   ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_misc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_PMU    ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_pmu.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_RCU    ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_rcu.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_RTC    ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_rtc.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_SDIO   ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_sdio.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_SPI    ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_spi.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_SYSCFG ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_syscfg.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_TIMER  ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_timer.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_TLI    ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_tli.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_TRNG   ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_trng.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_USART  ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_usart.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_WWDGT  ${gd32_std_src_dir}/${CONFIG_SOC_SERIES}_wwdgt.c)
 
 endif()
diff --git a/modules/hal_gigadevice/Kconfig b/modules/hal_gigadevice/Kconfig
index d82fef6629ea3..542c65620dbcc 100644
--- a/modules/hal_gigadevice/Kconfig
+++ b/modules/hal_gigadevice/Kconfig
@@ -51,6 +51,11 @@ config USE_GD32_DBG
 	help
 	  Enable GD32 Debug (DBG) HAL module driver
 
+config USE_GD32_DCI
+	bool
+	help
+		Enable GD32 Digital Camera Interface (DCI) HAL module driver
+
 config USE_GD32_DMA
 	bool
 	help
@@ -99,6 +104,16 @@ config USE_GD32_I2C
 	help
 	  Enable GD32 Inter-Integrated Circuit Interface (I2C) HAL module driver
 
+config USE_GD32_IPA
+	bool
+	help
+	  Enable GD32 Image Processing Accelerator (IPA) HAL module driver
+
+config USE_GD32_IREF
+	bool
+	help
+	  Enable GD32 Programmable Current Reference (IREF) HAL module driver
+
 config USE_GD32_MISC
 	bool
 	help
@@ -141,16 +156,31 @@ config USE_GD32_SHRTIMER
 	help
 	  Enable GD32 Super High-Resolution Timer (SHRTIMER) HAL module driver
 
+config USE_GD32_SYSCFG
+	bool
+	help
+	  Enable GD32 System Configuration (SYSCFG) HAL module driver
+
 config USE_GD32_TIMER
 	bool
 	help
 	  Enable GD32 Timer (TIMER) HAL module driver
 
+config USE_GD32_TLI
+	bool
+	help
+	  Enable GD32 TFT-LCD Interface (TLI) HAL module driver
+
 config USE_GD32_TMU
 	bool
 	help
 	  Enable GD32 Trigonometric Math Unit (TMU) HAL module driver
 
+config USE_GD32_TRNG
+	bool
+	help
+	  Enable GD32 True Random Number Generator (TRNG) HAL module driver
+
 config USE_GD32_USART
 	bool
 	help
diff --git a/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f403 b/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f403
deleted file mode 100644
index 0f06ef7072555..0000000000000
--- a/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f403
+++ /dev/null
@@ -1,21 +0,0 @@
-# Copyright (c) 2021, ATL Electronics
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_GD32F403R || SOC_GD32F403V || SOC_GD32F403Z
-
-config SOC
-	default	"gd32f403r" if SOC_GD32F403R
-	default	"gd32f403v" if SOC_GD32F403V
-	default	"gd32f403z" if SOC_GD32F403Z
-
-config SOC_SERIES_GD32F403
-	bool
-	default y
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 168000000
-
-config NUM_IRQS
-	default 68
-
-endif
diff --git a/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.series b/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.series
deleted file mode 100644
index 3e93f44e43aac..0000000000000
--- a/soc/arm/gigadevice/gd32f4/Kconfig.defconfig.series
+++ /dev/null
@@ -1,11 +0,0 @@
-# Copyright (c) 2021, ATL Electronics
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_GD32F4
-
-source "soc/arm/gigadevice/gd32f4/Kconfig.defconfig.gd32f4*"
-
-config SOC_SERIES
-	default "gd32f4"
-
-endif   # SOC_SERIES_GD32F4
diff --git a/soc/arm/gigadevice/gd32f4/Kconfig.soc b/soc/arm/gigadevice/gd32f4/Kconfig.soc
deleted file mode 100644
index cc23f5f862c38..0000000000000
--- a/soc/arm/gigadevice/gd32f4/Kconfig.soc
+++ /dev/null
@@ -1,17 +0,0 @@
-# Copyright (c) 2021, ATL Electronics
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "GigaDevice GD32F4xx MCU Selection"
-	depends on SOC_SERIES_GD32F4
-
-	config SOC_GD32F403R
-		bool "gd32f403r"
-
-	config SOC_GD32F403V
-		bool "gd32f403v"
-
-	config SOC_GD32F403Z
-		bool "gd32f403z"
-
-endchoice
diff --git a/soc/arm/gigadevice/gd32f4/soc.h b/soc/arm/gigadevice/gd32f4/soc.h
deleted file mode 100644
index 9fb29d9be2db3..0000000000000
--- a/soc/arm/gigadevice/gd32f4/soc.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (c) 2021, ATL Electronics
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief Board configuration macros
- *
- * This header file is used to specify and describe board-level aspects
- */
-
-#ifndef _SOC__H_
-#define _SOC__H_
-
-#include <sys/util.h>
-
-#ifndef _ASMLANGUAGE
-
-/* Add include for DTS generated information */
-#include <devicetree.h>
-
-#if defined(CONFIG_SOC_SERIES_GD32F403)
-#include <gd32f403.h>
-#else
-#error Library does not support the specified device.
-#endif
-
-#endif /* !_ASMLANGUAGE */
-
-#endif /* _SOC__H_ */
diff --git a/soc/arm/gigadevice/gd32f4/CMakeLists.txt b/soc/arm/gigadevice/gd32f403/CMakeLists.txt
similarity index 100%
rename from soc/arm/gigadevice/gd32f4/CMakeLists.txt
rename to soc/arm/gigadevice/gd32f403/CMakeLists.txt
diff --git a/soc/arm/gigadevice/gd32f403/Kconfig.defconfig.gd32f403 b/soc/arm/gigadevice/gd32f403/Kconfig.defconfig.gd32f403
new file mode 100644
index 0000000000000..f73a4b16b29ff
--- /dev/null
+++ b/soc/arm/gigadevice/gd32f403/Kconfig.defconfig.gd32f403
@@ -0,0 +1,11 @@
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC
+	default "gd32f403"
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 168000000
+
+config NUM_IRQS
+	default 68
diff --git a/soc/arm/gigadevice/gd32f403/Kconfig.defconfig.series b/soc/arm/gigadevice/gd32f403/Kconfig.defconfig.series
new file mode 100644
index 0000000000000..dbec480c29968
--- /dev/null
+++ b/soc/arm/gigadevice/gd32f403/Kconfig.defconfig.series
@@ -0,0 +1,11 @@
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_GD32F403
+
+source "soc/arm/gigadevice/gd32f403/Kconfig.defconfig.gd32f403"
+
+config SOC_SERIES
+	default "gd32f403"
+
+endif   # SOC_SERIES_GD32F403
diff --git a/soc/arm/gigadevice/gd32f4/Kconfig.series b/soc/arm/gigadevice/gd32f403/Kconfig.series
similarity index 65%
rename from soc/arm/gigadevice/gd32f4/Kconfig.series
rename to soc/arm/gigadevice/gd32f403/Kconfig.series
index 8f15ecdaa8259..9fe193e62c656 100644
--- a/soc/arm/gigadevice/gd32f4/Kconfig.series
+++ b/soc/arm/gigadevice/gd32f403/Kconfig.series
@@ -1,8 +1,8 @@
 # Copyright (c) 2021, ATL Electronics
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_GD32F4
-	bool "GigaDevice GD32F4xxx series Cortex-M4F MCU"
+config SOC_SERIES_GD32F403
+	bool "GigaDevice GD32F403 series Cortex-M4F MCU"
 	select ARM
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
@@ -11,4 +11,4 @@ config SOC_SERIES_GD32F4
 	select CPU_CORTEX_M_HAS_VTOR
 	select SOC_FAMILY_GD32_ARM
 	help
-	  Enable support for GigaDevice GD32F4xxx MCU series
+	  Enable support for GigaDevice GD32F403 MCU series
diff --git a/soc/arm/gigadevice/gd32f403/Kconfig.soc b/soc/arm/gigadevice/gd32f403/Kconfig.soc
new file mode 100644
index 0000000000000..17e960ce40ca6
--- /dev/null
+++ b/soc/arm/gigadevice/gd32f403/Kconfig.soc
@@ -0,0 +1,11 @@
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "GigaDevice GD32F403 MCU Selection"
+	depends on SOC_SERIES_GD32F403
+
+	config SOC_GD32F403
+		bool "gd32f403"
+
+endchoice
diff --git a/soc/arm/gigadevice/gd32f4/linker.ld b/soc/arm/gigadevice/gd32f403/linker.ld
similarity index 100%
rename from soc/arm/gigadevice/gd32f4/linker.ld
rename to soc/arm/gigadevice/gd32f403/linker.ld
diff --git a/soc/arm/gigadevice/gd32f4/soc.c b/soc/arm/gigadevice/gd32f403/soc.c
similarity index 100%
rename from soc/arm/gigadevice/gd32f4/soc.c
rename to soc/arm/gigadevice/gd32f403/soc.c
diff --git a/soc/arm/gigadevice/gd32f403/soc.h b/soc/arm/gigadevice/gd32f403/soc.h
new file mode 100644
index 0000000000000..4dcd6477c9ea7
--- /dev/null
+++ b/soc/arm/gigadevice/gd32f403/soc.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2021, ATL Electronics
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration header for the GD32F403 SoC series.
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+#include <sys/util.h>
+
+#ifndef _ASMLANGUAGE
+#include <devicetree.h>
+#include <gd32f403.h>
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _SOC__H_ */
diff --git a/soc/arm/gigadevice/gd32f4xx/CMakeLists.txt b/soc/arm/gigadevice/gd32f4xx/CMakeLists.txt
new file mode 100644
index 0000000000000..9d80226466cf0
--- /dev/null
+++ b/soc/arm/gigadevice/gd32f4xx/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright (c) 2021, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+zephyr_sources(soc.c)
diff --git a/soc/arm/gigadevice/gd32f4xx/Kconfig.defconfig.gd32f450 b/soc/arm/gigadevice/gd32f4xx/Kconfig.defconfig.gd32f450
new file mode 100644
index 0000000000000..6a07897740ba7
--- /dev/null
+++ b/soc/arm/gigadevice/gd32f4xx/Kconfig.defconfig.gd32f450
@@ -0,0 +1,11 @@
+# Copyright (c) 2021, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC
+	default "gd32f450"
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 200000000
+
+config NUM_IRQS
+	default 91
diff --git a/soc/arm/gigadevice/gd32f4xx/Kconfig.defconfig.series b/soc/arm/gigadevice/gd32f4xx/Kconfig.defconfig.series
new file mode 100644
index 0000000000000..f5ef03cd2765f
--- /dev/null
+++ b/soc/arm/gigadevice/gd32f4xx/Kconfig.defconfig.series
@@ -0,0 +1,11 @@
+# Copyright (c) 2021, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_GD32F4XX
+
+source "soc/arm/gigadevice/gd32f4xx/Kconfig.defconfig.gd32*"
+
+config SOC_SERIES
+	default "gd32f4xx"
+
+endif # SOC_SERIES_GD32F4XX
diff --git a/soc/arm/gigadevice/gd32f4xx/Kconfig.series b/soc/arm/gigadevice/gd32f4xx/Kconfig.series
new file mode 100644
index 0000000000000..7fcfca925816a
--- /dev/null
+++ b/soc/arm/gigadevice/gd32f4xx/Kconfig.series
@@ -0,0 +1,12 @@
+# Copyright (c) 2021, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_GD32F4XX
+	bool "GigaDevice GD32F4XX series Cortex-M4F MCU"
+	select ARM
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select CPU_CORTEX_M4
+	select SOC_FAMILY_GD32_ARM
+	help
+	  Enable support for GigaDevice GD32F4XX MCU series
diff --git a/soc/arm/gigadevice/gd32f4xx/Kconfig.soc b/soc/arm/gigadevice/gd32f4xx/Kconfig.soc
new file mode 100644
index 0000000000000..1a439a347c9a6
--- /dev/null
+++ b/soc/arm/gigadevice/gd32f4xx/Kconfig.soc
@@ -0,0 +1,11 @@
+# Copyright (c) 2021, Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "GigaDevice GD32F4XX MCU Selection"
+	depends on SOC_SERIES_GD32F4XX
+
+	config SOC_GD32F450
+		bool "gd32f450"
+
+endchoice
diff --git a/soc/arm/gigadevice/gd32f4xx/linker.ld b/soc/arm/gigadevice/gd32f4xx/linker.ld
new file mode 100644
index 0000000000000..d51a91910feb9
--- /dev/null
+++ b/soc/arm/gigadevice/gd32f4xx/linker.ld
@@ -0,0 +1,6 @@
+/*
+ * Copyright (c) 2021 Teslabs Engineering S.L.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>
diff --git a/soc/arm/gigadevice/gd32f4xx/soc.c b/soc/arm/gigadevice/gd32f4xx/soc.c
new file mode 100644
index 0000000000000..a7824b052fc63
--- /dev/null
+++ b/soc/arm/gigadevice/gd32f4xx/soc.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2021, Teslabs Engineering S.L.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <device.h>
+#include <init.h>
+
+static int gd32f4xx_soc_init(const struct device *dev)
+{
+	uint32_t key;
+
+	ARG_UNUSED(dev);
+
+	key = irq_lock();
+
+	SystemInit();
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	return 0;
+}
+
+SYS_INIT(gd32f4xx_soc_init, PRE_KERNEL_1, 0);
diff --git a/soc/arm/gigadevice/gd32f4xx/soc.h b/soc/arm/gigadevice/gd32f4xx/soc.h
new file mode 100644
index 0000000000000..16f546e090f93
--- /dev/null
+++ b/soc/arm/gigadevice/gd32f4xx/soc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2021, Teslabs Engineering S.L.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_ARM_GIGADEVICE_GD32F4XX_SOC_H_
+#define _SOC_ARM_GIGADEVICE_GD32F4XX_SOC_H_
+
+#ifndef _ASMLANGUAGE
+
+#include <devicetree.h>
+#include <gd32f4xx.h>
+
+#endif /* _ASMLANGUAGE */
+
+#endif /* _SOC_ARM_GIGADEVICE_GD32F4XX_SOC_H_ */
diff --git a/west.yml b/west.yml
index 70fb61bd596a4..11addd971e7b0 100644
--- a/west.yml
+++ b/west.yml
@@ -73,7 +73,7 @@ manifest:
       groups:
         - hal
     - name: hal_gigadevice
-      revision: ce323de9655972a545cbdddda813c1576d85d5d1
+      revision: 85f10a63f9ea550a6ebd62843a976df6bf49877b
       path: modules/hal/gigadevice
       groups:
         - hal