diff --git a/CODEOWNERS b/CODEOWNERS index df2803d80e08f..cc97b3f4155b2 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -71,6 +71,7 @@ /arch/riscv/ @kgugala @pgielda /soc/posix/ @aescolar @daor-oti /soc/riscv/ @kgugala @pgielda +/soc/riscv/bouffalolab/ @nandojve /soc/riscv/openisa*/ @dleach02 /soc/riscv/riscv-privilege/andes_v5/ @cwshu @Teng-Shih-Wei /soc/riscv/riscv-privilege/neorv32/ @henrikbrixandersen @@ -149,6 +150,7 @@ /boards/posix/ @aescolar @daor-oti /boards/posix/nrf52_bsim/ @aescolar @wopu-ot /boards/riscv/ @kgugala @pgielda +/boards/riscv/dt_bl10_devkit/ @nandojve /boards/riscv/rv32m1_vega/ @dleach02 /boards/riscv/beaglev_starlight_jh7100/ @rajnesh-kanwal /boards/riscv/adp_xc7k_ae350/ @cwshu @Teng-Shih-Wei @@ -188,6 +190,7 @@ /drivers/debug/ @nashif /drivers/*/*sam4l* @nandojve /drivers/*/*cc13xx_cc26xx* @bwitherspoon +/drivers/*/*bflb* @nandojve /drivers/*/*gd32* @nandojve /drivers/*/*litex* @mateusz-holenko @kgugala @pgielda /drivers/*/*mcux* @mmahadevan108 @dleach02 @@ -298,6 +301,7 @@ /drivers/pcie/ @dcpleung @nashif @jhedberg /drivers/peci/ @albertofloyd @franciscomunoz @scottwcpg /drivers/pinctrl/ @gmarull +/drivers/pinctrl/*bflb* @nandojve /drivers/pinmux/*b91* @yurvyn /drivers/pinmux/*hsdk* @iriszzw /drivers/pinmux/*it8xxx2* @ite @@ -429,6 +433,7 @@ /dts/arm/silabs/efr32mg21* @l-alfred /dts/arm/silabs/efr32fg13* @yonsch /dts/riscv/ @kgugala @pgielda +/dts/riscv/bouffalolab/ @nandojve /dts/riscv/it8xxx2.dtsi @ite /dts/riscv/microsemi-miv.dtsi @galak /dts/riscv/rv32m1* @dleach02 @@ -453,6 +458,7 @@ /dts/bindings/modem/*hl7800.yaml @LairdCP/zephyr /dts/bindings/serial/ns16550.yaml @dcpleung @nashif /dts/bindings/wifi/*esp-at.yaml @mniestroj +/dts/bindings/*/*bflb* @nandojve /dts/bindings/*/*gd32* @nandojve /dts/bindings/*/*npcx* @MulinChao @WealianLiao @ChiHuaL /dts/bindings/*/*psoc6* @nandojve @@ -530,6 +536,7 @@ /include/dt-bindings/clock/kinetis_scg.h @henrikbrixandersen /include/dt-bindings/ethernet/xlnx_gem.h @ibirnbaum /include/dt-bindings/pcie/ @dcpleung +/include/dt-bindings/pinctrl/*bflb* @nandojve /include/dt-bindings/pwm/*it8xxx2* @RuibinChang /include/dt-bindings/usb/usb.h @galak /include/drivers/emul.h @sjg20 @@ -576,6 +583,7 @@ /lib/libc/arcmwdt/ @abrodkin @ruuddw @evgeniy-paltsev /modules/ @nashif /modules/canopennode/ @henrikbrixandersen +/modules/hal_bouffalolab/ @nandojve /modules/mbedtls/ @ceolin @d3zd3z /modules/hal_gigadevice/ @nandojve /modules/trusted-firmware-m/ @ioannisg @microbuilder @@ -645,6 +653,7 @@ /scripts/twister @nashif /scripts/series-push-hook.sh @erwango /scripts/west_commands/ @mbolivar-nordic +/scripts/west_commands/runners/blflash.py @mbolivar-nordic @nandojve /scripts/west-commands.yml @mbolivar-nordic /scripts/zephyr_module.py @tejlmand /scripts/uf2conv.py @petejohanson diff --git a/boards/common/blflash.board.cmake b/boards/common/blflash.board.cmake new file mode 100644 index 0000000000000..5c99a2b913bf1 --- /dev/null +++ b/boards/common/blflash.board.cmake @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(blflash) +board_finalize_runner_args(blflash) diff --git a/boards/riscv/dt_bl10_devkit/Kconfig.board b/boards/riscv/dt_bl10_devkit/Kconfig.board new file mode 100644 index 0000000000000..98544424fe7ce --- /dev/null +++ b/boards/riscv/dt_bl10_devkit/Kconfig.board @@ -0,0 +1,8 @@ +# Bouffalo Lab BL602 DevKit +# +# Copyright (c) 2021 ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_DT_BL10_DEVKIT + bool "2.4GHz Wi-Fi and BLE coexistence Module Development Kit" + depends on SOC_PART_NUMBER_BL602C20Q2I diff --git a/boards/riscv/dt_bl10_devkit/Kconfig.defconfig b/boards/riscv/dt_bl10_devkit/Kconfig.defconfig new file mode 100644 index 0000000000000..2bf6b64554aaf --- /dev/null +++ b/boards/riscv/dt_bl10_devkit/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Bouffalo Lab BL602 DevKit +# +# Copyright (c) 2021 ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_DT_BL10_DEVKIT + +config BOARD + default "dt_bl10_devkit" + +endif # BOARD_DT_BL10_DEVKIT diff --git a/boards/riscv/dt_bl10_devkit/board.cmake b/boards/riscv/dt_bl10_devkit/board.cmake new file mode 100644 index 0000000000000..02dcd61a225d6 --- /dev/null +++ b/boards/riscv/dt_bl10_devkit/board.cmake @@ -0,0 +1,4 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/blflash.board.cmake) diff --git a/boards/riscv/dt_bl10_devkit/doc/img/dt_bl10_devkit.jpg b/boards/riscv/dt_bl10_devkit/doc/img/dt_bl10_devkit.jpg new file mode 100644 index 0000000000000..6dbe75cd8146d Binary files /dev/null and b/boards/riscv/dt_bl10_devkit/doc/img/dt_bl10_devkit.jpg differ diff --git a/boards/riscv/dt_bl10_devkit/doc/index.rst b/boards/riscv/dt_bl10_devkit/doc/index.rst new file mode 100644 index 0000000000000..f3952c3cce588 --- /dev/null +++ b/boards/riscv/dt_bl10_devkit/doc/index.rst @@ -0,0 +1,187 @@ +.. _dt_bl10_devkit: + +BL602 Development Board +####################### + +Overview +******** + +BL602/BL604 is a Wi-Fi+BLE chipset introduced by Bouffalo Lab, which is used +for low power consumption and high performance application development. The +wireless subsystem includes 2.4G radio, Wi-Fi 802.11b/g/n and BLE 5.0 +baseband/MAC design. The microcontroller subsystem includes a 32-bit RISC CPU +with low power consumption, cache and memory. The power management unit +controls the low power consumption mode. In addition, it also supports +various security features. The external interfaces include SDIO, SPI, UART, +I2C, IR remote, PWM, ADC, DAC, PIR and GPIO. + +The BL602 Development Board features a SiFive E24 32 bit RISC-V CPU with FPU, +it supports High Frequency clock up to 192Mhz, have 128k ROM, 276kB RAM, +2.4 GHz WIFI 1T1R mode, support 20 MHz, data rate up to 72.2 Mbps, BLE 5.0 +with 2MB phy. It is a secure MCU which supports Secure boot, ECC-256 signed +image, QSPI/SPI Flash On-The-Fly AES Decryption and PKA (Public Key +Accelerator). + +.. image:: img/dt_bl10_devkit.jpg + :width: 450px + :align: center + :alt: dt_bl10_devkit + +Hardware +******** + +For more information about the Bouffalo Lab BL-602 MCU: + +- `Bouffalo Lab BL602 MCU Website`_ +- `Bouffalo Lab BL602 MCU Datasheet`_ +- `Bouffalo Lab Development Zone`_ +- `dt_bl10_devkit Schematic`_ +- `Doctors of Intelligence & Technology (www.doiting.com)`_ +- `The RISC-V BL602 Book`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| MTIMER | on-chip | RISC-V Machine Timer | ++-----------+------------+-----------------------+ +| PINCTRL | on-chip | pin muxing | ++-----------+------------+-----------------------+ +| UART | on-chip | serial port-polling | ++-----------+------------+-----------------------+ + + +The default configurations can be found in the Kconfig +:zephyr_file:`boards/risc/dt_bl10_devkit/dt_bl10_devkit_defconfig`. + +System Clock +============ + +The BL602 Development Board is configured to run at max speed (192MHz). + +Serial Port +=========== + +The dt_bl10_devkit_ uses UART0 as default serial port. It is connected to +USB Serial converter and port is used for both program and console. + + +Programming and Debugging +************************* + +BL Flash tool +============= + +The BL-602 have a ROM bootloader that allows user flash device by serial port. +There are some tools available at internet and this will describe one of them. +The below guide was created based on RISC-V BL602 Book, chapter 3 +`Flashing Firmware to BL602`_. + +#. `Install Rustup`_ + +#. Clone blflash rust version + + .. code-block:: console + + $ git clone --recursive https://github.com/spacemeowx2/blflash + +#. Build blflash + + .. code-block:: console + + $ cd blflash + $ cargo build --release + +#. Install blflash. The recommended use is copy to home folder + + .. code-block:: console + + $ cp blflash ~/bin/ + +#. Test + + .. code-block:: console + + $ blflash -V + + It will print blflash version + + .. code-block:: console + + $ blflash 0.3.3 + +Samples +======= + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: dt_bl10_devkit + :goals: build + :compact: + +#. To flash an image using blflash runner: + + #. Press D8 button + + #. Press and release EN button + + #. Release D8 button + + .. code-block:: console + + west flash -r blflash + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + + Then, press and release EN button + + .. code-block:: console + + *** Booting Zephyr OS build zephyr-v2.6.0-1729-g22140c728537 *** + Hello World! dt_bl10_devkit + +Congratulations, you have `dt_bl10_devkit`_ configured and running Zephyr. + + +.. _Bouffalo Lab BL602 MCU Website: + https://www.bouffalolab.com/bl602 + +.. _Bouffalo Lab BL602 MCU Datasheet: + https://github.com/bouffalolab/bl_docs/tree/main/BL602_DS/en + +.. _Bouffalo Lab Development Zone: + https://dev.bouffalolab.com/home?id=guest + +.. _dt_bl10_devkit Schematic: + https://github.com/SmartArduino/Doiting_BL/blob/master/board/DT-BL10%20User%20Mannual.pdf + +.. _Doctors of Intelligence & Technology (www.doiting.com): + https://www.doiting.com + +.. _Install Rustup: + https://rustup.rs/ + +.. _The RISC-V BL602 Book: + https://lupyuen.github.io/articles/book + +.. _Flashing Firmware to BL602: + https://lupyuen.github.io/articles/book#flashing-firmware-to-bl602 diff --git a/boards/riscv/dt_bl10_devkit/dt_bl10_devkit-pinctrl.dtsi b/boards/riscv/dt_bl10_devkit/dt_bl10_devkit-pinctrl.dtsi new file mode 100644 index 0000000000000..6ec019a59d821 --- /dev/null +++ b/boards/riscv/dt_bl10_devkit/dt_bl10_devkit-pinctrl.dtsi @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2021, ATL Electronics + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart0_default: uart0_default { + pins1 { + bflb,pins = , + ; + bflb,signals = , + ; + bias-pull-up; + input-schmitt-enable; + }; + }; + uart0_sleep: uart0_sleep { + pins1 { + bflb,pins = , + ; + bflb,signals = , + ; + bias-high-impedance; + }; + }; +}; diff --git a/boards/riscv/dt_bl10_devkit/dt_bl10_devkit.dts b/boards/riscv/dt_bl10_devkit/dt_bl10_devkit.dts new file mode 100644 index 0000000000000..70e0e37b78eb3 --- /dev/null +++ b/boards/riscv/dt_bl10_devkit/dt_bl10_devkit.dts @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2021, ATL Electronics + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "dt_bl10_devkit-pinctrl.dtsi" + +/ { + model = "2.4GHz Wi-Fi and BLE coexistence Module Development Kit"; + compatible = "bflb,bl602"; + + chosen { + zephyr,flash = &flash0; + zephyr,itcm = &itcm; + zephyr,dtcm = &dtcm; + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; +}; + +&cpu0 { + clock-frequency = <160000000>; +}; + +&spi1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4000b000 0x1000 0x23000000 0xc00000>; + flash0: flash@0 { + compatible = "issi,is25lp128", "jedec,spi-nor"; + size = <134217728>; + label = "FLASH0"; + jedec-id = [96 60 18]; + reg = <0>; + // Dummy entry + spi-max-frequency = <0>; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/riscv/dt_bl10_devkit/dt_bl10_devkit.yaml b/boards/riscv/dt_bl10_devkit/dt_bl10_devkit.yaml new file mode 100644 index 0000000000000..f2c752513ee7d --- /dev/null +++ b/boards/riscv/dt_bl10_devkit/dt_bl10_devkit.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +identifier: dt_bl10_devkit +name: 2.4GHz Wi-Fi and BLE coexistence Module Development Kit +type: mcu +arch: riscv32 +ram: 64 +toolchain: + - zephyr +testing: + ignore_tags: + - net + - bluetooth diff --git a/boards/riscv/dt_bl10_devkit/dt_bl10_devkit_defconfig b/boards/riscv/dt_bl10_devkit/dt_bl10_devkit_defconfig new file mode 100644 index 0000000000000..576174027c6d0 --- /dev/null +++ b/boards/riscv/dt_bl10_devkit/dt_bl10_devkit_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_SERIES_BL6=y +CONFIG_SOC_PART_NUMBER_BL602C20Q2I=y +CONFIG_BOARD_DT_BL10_DEVKIT=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index cd3eca95d8d74..1fa8829a040ff 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -3,3 +3,4 @@ zephyr_library() zephyr_library_sources(common.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_BFLB pinctrl_bflb.c) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 7e1a67175b84c..8825e7cd22385 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -29,4 +29,6 @@ config PINCTRL_DYNAMIC runtime. This can be useful, for example, to change the pins assigned to a peripheral at early boot stages depending on a certain input. +source "drivers/pinctrl/Kconfig.bflb" + endif # PINCTRL diff --git a/drivers/pinctrl/Kconfig.bflb b/drivers/pinctrl/Kconfig.bflb new file mode 100644 index 0000000000000..8d9060ad80064 --- /dev/null +++ b/drivers/pinctrl/Kconfig.bflb @@ -0,0 +1,9 @@ +# Copyright (c) 2021 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config PINCTRL_BFLB + bool "Bouffalo Lab pin control driver" + depends on SOC_FAMILY_BFLB + default y + help + Bouffalo Lab pin control driver diff --git a/drivers/pinctrl/pinctrl_bflb.c b/drivers/pinctrl/pinctrl_bflb.c new file mode 100644 index 0000000000000..789e120123f00 --- /dev/null +++ b/drivers/pinctrl/pinctrl_bflb.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2021 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, + uintptr_t reg) +{ + GLB_GPIO_Cfg_Type pincfg; + uint8_t i; + + ARG_UNUSED(reg); + + for (i = 0U; i < pin_cnt; i++) { + pincfg.gpioFun = BFLB_FUN_2_FUNC(pins[i].fun); + pincfg.gpioMode = BFLB_FUN_2_MODE(pins[i].fun); + pincfg.gpioPin = pins[i].pin; + pincfg.pullType = BFLB_CFG_2_GPIO_MODE(pins[i].cfg); + pincfg.smtCtrl = BFLB_CFG_2_GPIO_INP_SMT(pins[i].cfg); + pincfg.drive = BFLB_CFG_2_GPIO_DRV_STR(pins[i].cfg); + + if (pincfg.gpioFun == GPIO_FUN_UART) { + GLB_UART_Fun_Sel(pincfg.gpioPin % 8, + (BFLB_FUN_2_INST(pins[i].fun)) + * BFLB_SIG_UART_LEN + + (pins[i].flags & BFLB_SIG_UART_MASK) + ); + } + + GLB_GPIO_Init(&pincfg); + } + + return 0; +} diff --git a/drivers/serial/CMakeLists.txt b/drivers/serial/CMakeLists.txt index a5c8c87c6c110..c245bba7702fc 100644 --- a/drivers/serial/CMakeLists.txt +++ b/drivers/serial/CMakeLists.txt @@ -44,6 +44,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_XEC uart_mchp_xec.c) zephyr_library_sources_ifdef(CONFIG_UART_NEORV32 uart_neorv32.c) zephyr_library_sources_ifdef(CONFIG_USART_GD32 usart_gd32.c) zephyr_library_sources_ifdef(CONFIG_UART_XEN_HVC uart_hvc_xen.c) +zephyr_library_sources_ifdef(CONFIG_UART_BFLB uart_bflb.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE uart_handlers.c) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 2729390b1806c..4d5bdaab89b53 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -169,4 +169,6 @@ source "drivers/serial/Kconfig.neorv32" source "drivers/serial/Kconfig.xen" +source "drivers/serial/Kconfig.bflb" + endif # SERIAL diff --git a/drivers/serial/Kconfig.bflb b/drivers/serial/Kconfig.bflb new file mode 100644 index 0000000000000..5e11ac54ce5a6 --- /dev/null +++ b/drivers/serial/Kconfig.bflb @@ -0,0 +1,16 @@ +# Bouffalo Lab UART configuration +# +# Copyright (c) 2021 ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +# Workaround for not being able to have commas in macro arguments +DT_COMPAT_BFLB_BL_UART := bflb,bl-uart + +config UART_BFLB + bool "Bouffalo Lab serial driver" + default $(dt_compat_enabled,$(DT_COMPAT_BFLB_BL_UART)) + depends on SOC_FAMILY_BFLB + select SERIAL_HAS_DRIVER + select USE_BFLB_UART + help + This option enables the UART driver for Bouffalo Lab SoC family. diff --git a/drivers/serial/uart_bflb.c b/drivers/serial/uart_bflb.c new file mode 100644 index 0000000000000..045068fd009e3 --- /dev/null +++ b/drivers/serial/uart_bflb.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2021, ATL Electronics + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT bflb_bl_uart + +/** + * @brief UART driver for Bouffalo Lab MCU family. + */ +#include +#include +#include +#include + +#define UART_CTS_FLOWCONTROL_ENABLE (0) +#define UART_RTS_FLOWCONTROL_ENABLE (0) +#define UART_MSB_FIRST_ENABLE (0) +#define UART_DEFAULT_RTO_TIMEOUT (255) +#define UART_CLOCK_DIV (0) + +struct bl_config { + const struct pinctrl_dev_config *pinctrl_cfg; + uint32_t periph_id; + UART_CFG_Type uart_cfg; + UART_FifoCfg_Type fifo_cfg; +}; + +static int uart_bl_init(const struct device *dev) +{ + const struct bl_config *cfg = dev->config; + + pinctrl_apply_state(cfg->pinctrl_cfg, PINCTRL_STATE_DEFAULT); + + GLB_Set_UART_CLK(1, HBN_UART_CLK_160M, UART_CLOCK_DIV); + + UART_IntMask(cfg->periph_id, UART_INT_ALL, 1); + UART_Disable(cfg->periph_id, UART_TXRX); + + UART_Init(cfg->periph_id, (UART_CFG_Type *)&cfg->uart_cfg); + UART_TxFreeRun(cfg->periph_id, 1); + UART_SetRxTimeoutValue(cfg->periph_id, UART_DEFAULT_RTO_TIMEOUT); + UART_FifoConfig(cfg->periph_id, (UART_FifoCfg_Type *)&cfg->fifo_cfg); + UART_Enable(cfg->periph_id, UART_TXRX); + + return 0; +} + +static int uart_bl_poll_in(const struct device *dev, unsigned char *c) +{ + const struct bl_config *cfg = dev->config; + + return UART_ReceiveData(cfg->periph_id, (uint8_t *)c, 1); +} + +static void uart_bl_poll_out(const struct device *dev, unsigned char c) +{ + const struct bl_config *cfg = dev->config; + + while (UART_GetTxFifoCount(cfg->periph_id) == 0) { + ; + } + + (void)UART_SendData(cfg->periph_id, (uint8_t *)&c, 1); +} + +#ifdef CONFIG_PM_DEVICE +static int uart_bl_pm_control(const struct device *dev, + enum pm_device_action action) +{ + const struct bl_config *cfg = dev->config; + + switch (action) { + case PM_DEVICE_ACTION_RESUME: + (void)pinctrl_apply_state(cfg->pinctrl_cfg, PINCTRL_STATE_DEFAULT); + UART_Enable(cfg->periph_id, UART_TXRX); + break; + case PM_DEVICE_ACTION_SUSPEND: + if (pinctrl_apply_state(cfg->pinctrl_cfg, PINCTRL_STATE_SLEEP)) { + return -ENOTSUP; + } + UART_Disable(cfg->periph_id, UART_TXRX); + break; + default: + return -ENOTSUP; + } + + return 0; +} +#endif /* CONFIG_PM_DEVICE */ + +static const struct uart_driver_api uart_bl_driver_api = { + .poll_in = uart_bl_poll_in, + .poll_out = uart_bl_poll_out, +}; + +#define BL_UART_INIT(n) \ + PINCTRL_DT_INST_DEFINE(n) \ + static const struct bl_config bl_uart##n##_config = { \ + .pinctrl_cfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ + .periph_id = DT_INST_PROP(n, peripheral_id), \ + \ + .uart_cfg.baudRate = DT_INST_PROP(n, current_speed), \ + .uart_cfg.dataBits = UART_DATABITS_8, \ + .uart_cfg.stopBits = UART_STOPBITS_1, \ + .uart_cfg.parity = UART_PARITY_NONE, \ + .uart_cfg.uartClk = SOC_BOUFFALOLAB_BL_PLL160_FREQ_HZ, \ + .uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE, \ + .uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE, \ + .uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE, \ + \ + .fifo_cfg.txFifoDmaThreshold = 1, \ + .fifo_cfg.rxFifoDmaThreshold = 1, \ + .fifo_cfg.txFifoDmaEnable = 0, \ + .fifo_cfg.rxFifoDmaEnable = 0, \ + }; \ + DEVICE_DT_INST_DEFINE(n, &uart_bl_init, \ + uart_bl_pm_control, \ + NULL, \ + &bl_uart##n##_config, PRE_KERNEL_1, \ + CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \ + &uart_bl_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(BL_UART_INIT) diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 864bea683238f..fe8fe8cbe1d45 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -218,7 +218,7 @@ source "drivers/timer/Kconfig.stm32_lptim" config RISCV_MACHINE_TIMER bool "RISCV Machine Timer" - depends on SOC_FAMILY_RISCV_PRIVILEGE + depends on SOC_FAMILY_RISCV_PRIVILEGE || SOC_FAMILY_BFLB select TICKLESS_CAPABLE help This module implements a kernel device driver for the generic RISCV machine diff --git a/dts/bindings/gpio/bflb,bl-gpio.yaml b/dts/bindings/gpio/bflb,bl-gpio.yaml new file mode 100644 index 0000000000000..4e17f8db26a88 --- /dev/null +++ b/dts/bindings/gpio/bflb,bl-gpio.yaml @@ -0,0 +1,40 @@ +# Copyright (c) 2021, Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +description: Bouffalo Lab GPIO node + +compatible: "bflb,bl-gpio" + +include: [gpio-controller.yaml, base.yaml] + +properties: + reg: + required: true + + interrupts: + required: false + + label: + required: true + + "#gpio-cells": + const: 0 + + "#bflb,pin-cells": + type: int + required: true + const: 2 + description: Number of items to expect in a bflb,pins specifier + + "#bflb,signal-cells": + type: int + required: false + const: 1 + description: Number of items to expect in a bflb,signals specifier + +bflb,pin-cells: + - fun + - pin + +bflb,signal-cells: + - flags diff --git a/dts/bindings/pinctrl/bflb,bl-pinctrl.yaml b/dts/bindings/pinctrl/bflb,bl-pinctrl.yaml new file mode 100644 index 0000000000000..00b7ab07f6d4b --- /dev/null +++ b/dts/bindings/pinctrl/bflb,bl-pinctrl.yaml @@ -0,0 +1,90 @@ +# Copyright (c) 2021, Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +description: Bouffalo Lab Pinctrl node + +compatible: "bflb,bl-pinctrl" + +include: + - name: base.yaml + - name: pincfg-node-group.yaml + child-binding: + child-binding: + property-allowlist: + - bias-high-impedance + - bias-pull-down + - bias-pull-up + - input-enable + - input-schmitt-enable + - output-enable + +properties: + "#address-cells": + required: true + const: 1 + "#size-cells": + required: true + const: 1 + +child-binding: + description: | + Bouffalo Lab pin controller pin configuration nodes. Each node is composed + by one or more groups, each defining the configuration for a set of pins. + + child-binding: + description: | + Bouffalo Lab pin controller pin configuration group. Each group contains + a list of pins sharing the same set of properties. Example: + uart0_default: uart0_default { + /* group 1 (name is arbitrary) */ + pins1 { + /* configure to uart0 function plus modem interrupt, pin 7 as UART_RX + pin 16 as UART_TX and finally pin 18 as gpio */ + bflb,pins = , + , + ; + bflb,signals = , + ; + bias-pull-up; + input-schmitt-enable; + }; + }; + The list of supported standard properties: + - bias-high-impedance: Disable pull-up/down (default behavior, not + required). + - bias-pull-up: Enable pull-up resistor. + - bias-pull-down: Enable pull-down resistor. + - input-enable: Enable GPIO as input (default behavior, not required). + - input-schmitt-enable: Enable Schimitt Trigger when GPIO is Input. + - output-enable: Enable GPIO as output. + + Note that bias options are mutually exclusive. It is the same with GPIO + input/output enable options. + properties: + "bflb,pins": + required: true + type: phandle-array + description: | + An phandle-array of pins sharing the same group properties. The pins + should be defined using the BFLB_PIN utility macro that encode + function and pin. Some special functions require a signal to complete + route matrix. + "bflb,signals": + required: false + type: array + description: | + An optional array that add flags to a pin. The signal flag is defined + at bflb-pinctrl.h and have BFLB_SIG_ as prefix. It don't require same + len that bflb,pins property. + drive-strength: + required: false + type: int + default: 0 + enum: + - 0 # Default value, lower strength, 8mA + - 1 # 9.6mA + - 2 # 11.2mA + - 3 # highest strength, 12.8mA + description: | + Pin drive strength. It tunes pin max current where 0 means lower + value, which is the default, and 3 represents max drive strength. diff --git a/dts/bindings/serial/bflb,bl-uart.yaml b/dts/bindings/serial/bflb,bl-uart.yaml new file mode 100644 index 0000000000000..d20d2f1ef01ea --- /dev/null +++ b/dts/bindings/serial/bflb,bl-uart.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +description: Bouffalo Lab UART + +compatible: "bflb,bl-uart" + +include: [uart-controller.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + peripheral-id: + type: int + description: peripheral ID + required: true diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt index 352177db2902a..5d1247e343d57 100644 --- a/dts/bindings/vendor-prefixes.txt +++ b/dts/bindings/vendor-prefixes.txt @@ -87,6 +87,7 @@ baikal BAIKAL ELECTRONICS, JSC bananapi BIPAI KEJI LIMITED beacon Compass Electronics Group, LLC beagle BeagleBoard.org Foundation +bflb Bouffalo Lab bhf Beckhoff Automation GmbH & Co. KG bitmain Bitmain Technologies blutek BluTek Power diff --git a/dts/riscv/bouffalolab/bl6.dtsi b/dts/riscv/bouffalolab/bl6.dtsi new file mode 100644 index 0000000000000..9662f1f7e93d9 --- /dev/null +++ b/dts/riscv/bouffalolab/bl6.dtsi @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2021, ATL Electronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + clock-frequency = <0>; + compatible = "riscv,sifive-e24", "riscv"; + device_type = "cpu"; + hardware-exec-breakpoint-count = <4>; + reg = <0>; + riscv,isa = "rv32imafcb"; + riscv,pmpregions = <4>; + + ictrl: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + itcm: itcm@22010000 { + compatible = "sifive,dtim0"; + reg = <0x22010000 DT_SIZE_K(16)>; + }; + dtcm: dtcm@42014000 { + compatible = "sifive,dtim0"; + reg = <0x42014000 DT_SIZE_K(48)>; + }; + + sram0: memory@42020000 { + compatible = "mmio-sram"; + }; + sram1: memory@42030000 { + compatible = "mmio-sram"; + reg = <0x42030000 DT_SIZE_K(112)>; + }; + + clint: clint@2000000 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,clint0"; + interrupts-extended = <&ictrl 3 &ictrl 7>; + reg = <0x2000000 0x10000>; + reg-names = "control"; + }; + + clic: clic@2000000 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "sifive,clic0"; + interrupts-extended = <&ictrl 3 &ictrl 7 &ictrl 11>; + reg = <0x2000000 0x10000>; + reg-names = "control"; + + sifive,numintbits = <4>; + sifive,numints = <64>; + sifive,numlevels = <16>; + }; + + pinctrl: pinctrl@40000000 { + compatible = "bflb,bl-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x40000000 0x40000000 0x1000>; + + glb: gpio@40000000 { + compatible = "bflb,bl-gpio"; + reg = <0x40000000 0x1000>; + label = "GLB"; + interrupts = <1 0>; + interrupt-parent = <&ictrl>; + gpio-controller; + #gpio-cells = <0>; + #bflb,pin-cells = <2>; + #bflb,signal-cells = <1>; + }; + }; + + spi0: spi@4000a200 { + compatible = "bflb,bl-spi"; + reg = <0x4000a200 0x100>; + peripheral-id = <0>; + interrupts = <27 0>; + interrupt-parent = <&ictrl>; + status = "disabled"; + label = "spi_0"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@4000b000 { + compatible = "bflb,bl-qspi"; + reg = <0x4000b000 0x1000>; + peripheral-id = <0>; + interrupts = <23 0>; + interrupt-parent = <&ictrl>; + status = "disabled"; + label = "qspi_0"; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart0: uart@4000a000 { + compatible = "bflb,bl-uart"; + reg = <0x4000a000 0x100>; + peripheral-id = <0>; + interrupts = <29 0>; + interrupt-parent = <&ictrl>; + status = "disabled"; + label = "uart_0"; + }; + uart1: uart@4000a100 { + compatible = "bflb,bl-uart"; + reg = <0x4000a100 0x100>; + peripheral-id = <1>; + interrupts = <30 0>; + interrupt-parent = <&ictrl>; + status = "disabled"; + label = "uart_1"; + }; + }; +}; diff --git a/dts/riscv/bouffalolab/bl602.dtsi b/dts/riscv/bouffalolab/bl602.dtsi new file mode 100644 index 0000000000000..2398e7f81e9e3 --- /dev/null +++ b/dts/riscv/bouffalolab/bl602.dtsi @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2021 ATL Electronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + sram0: memory@42020000 { + reg = <0x42020000 DT_SIZE_K(64)>; + }; + }; +}; diff --git a/include/arch/riscv/common/linker.ld b/include/arch/riscv/common/linker.ld index d032c6e442d83..564f1288f30d2 100644 --- a/include/arch/riscv/common/linker.ld +++ b/include/arch/riscv/common/linker.ld @@ -320,7 +320,7 @@ GROUP_START(ITCM) } GROUP_LINK_IN(ITCM AT> ROMABLE_REGION) __itcm_size = __itcm_end - __itcm_start; - __itcm_rom_start = LOADADDR(_ITCM_SECTION_NAME); + __itcm_load_start = LOADADDR(_ITCM_SECTION_NAME); GROUP_END(ITCM) #endif @@ -355,7 +355,7 @@ GROUP_START(DTCM) __dtcm_end = .; - __dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME); + __dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME); GROUP_END(DTCM) #endif diff --git a/include/dt-bindings/pinctrl/bflb-pinctrl.h b/include/dt-bindings/pinctrl/bflb-pinctrl.h new file mode 100644 index 0000000000000..f18ad9140eed8 --- /dev/null +++ b/include/dt-bindings/pinctrl/bflb-pinctrl.h @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2021 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_BFLB_PINCTRL_H_ +#define ZEPHYR_BFLB_PINCTRL_H_ + +/** + * @brief FUN configuration bitfield + * + * The Zephyr version of Bouffalo Lab function field encode 3 information: + * - The pin function itself + * - The peripheral instance (ex. uart0, uart1, etc) + * - The pin mode + * + * Because GPIO is a subset of functions, it is necessary define all modes + * when a pin is configured. To keep it simple, mode is already defined for all + * alternate functions and analog. In the case of GPIO, the pincfg-node should + * be used to configure GPIO function. + * + * Pin function configuration is coded using 2 bytes with the following fields + * Byte 0 - Function + * Byte 1 - Pin Mode [ 0 : 1 ] + * - Peripheral Instance [ 4 : 5 ] + * + * ex.: + * uart1 - 0x1207 + * 1 2 07 + * Instance Alternate Mode Function UART + * + * gpio - 0x010b + * 0 2 0b + * Instance Output Function GPIO + */ + +#define BFLB_FUN_clk_out 0x0200 +#define BFLB_FUN_bt_coexist 0x0201 +#define BFLB_FUN_flash_psram 0x0202 +#define BFLB_FUN_qspi 0x0202 +#define BFLB_FUN_i2s 0x0203 +#define BFLB_FUN_spi 0x0204 +#define BFLB_FUN_i2c 0x0206 +#define BFLB_FUN_uart0 0x0207 +#define BFLB_FUN_uart1 0x1207 +#define BFLB_FUN_pwm 0x0208 +#define BFLB_FUN_cam 0x0209 +#define BFLB_FUN_analog 0x030a +#define BFLB_FUN_gpio 0x000b +#define BFLB_FUN_rf_test 0x020c +#define BFLB_FUN_scan 0x020d +#define BFLB_FUN_jtag 0x020e +#define BFLB_FUN_debug 0x020f +#define BFLB_FUN_external_pa 0x0210 +#define BFLB_FUN_usb_transceiver 0x0211 +#define BFLB_FUN_usb_controller 0x0212 +#define BFLB_FUN_ether_mac 0x0213 +#define BFLB_FUN_emca 0x0213 +#define BFLB_FUN_qdec 0x0014 +#define BFLB_FUN_key_scan_in 0x0215 +#define BFLB_FUN_key_scan_row 0x0215 +#define BFLB_FUN_key_scan_drive 0x0216 +#define BFLB_FUN_key_scan_col 0x0216 +#define BFLB_FUN_cam_misc 0x0217 +#define BFLB_FUN_FUNC_POS 0U +#define BFLB_FUN_FUNC_MASK 0x1F + +#define BFLB_FUN_MODE_POS 8U +#define BFLB_FUN_MODE_MASK 0x03 +#define BFLB_FUN_MODE_INPUT (0x0 << BFLB_FUN_MODE_POS) +#define BFLB_FUN_MODE_OUTPUT (0x1 << BFLB_FUN_MODE_POS) +#define BFLB_FUN_MODE_AF (0x2 << BFLB_FUN_MODE_POS) +#define BFLB_FUN_MODE_ANALOG (0x3 << BFLB_FUN_MODE_POS) + +#define BFLB_FUN_INST_POS 12U +#define BFLB_FUN_INST_MASK 0x03 +#define BFLB_FUN_INST_0 (0x0 << BFLB_FUN_INST_POS) +#define BFLB_FUN_INST_1 (0x1 << BFLB_FUN_INST_POS) + +#define BFLB_SIG_UART_RTS 0x0 +#define BFLB_SIG_UART_CTS 0x1 +#define BFLB_SIG_UART_TXD 0x2 +#define BFLB_SIG_UART_RXD 0x3 +#define BFLB_SIG_UART_LEN 0x4 +#define BFLB_SIG_UART_MASK 0x3 + +/** + * @brief helper macro to encode an IO port pin in a numerical format + * + * - fun Function value. It should be lower case value defined by a + * BFLB_FUN_function. + * - pin Pin number. + * + * ex.: How to define uart0 rx/tx pins, which is define as BFLB_FUN_uart0 + * + * bflb,pins = , + * ; + */ +#define BFLB_PIN(fun, pin) &glb BFLB_FUN_##fun pin + +#define BFLB_FUN_2_FUNC(fun) (((fun) >> BFLB_FUN_FUNC_POS) & BFLB_FUN_FUNC_MASK) +#define BFLB_FUN_2_MODE(fun) (((fun) >> BFLB_FUN_MODE_POS) & BFLB_FUN_MODE_MASK) +#define BFLB_FUN_2_INST(fun) (((fun) >> BFLB_FUN_INST_POS) & BFLB_FUN_INST_MASK) + +/* + * Pin configuration is coded following below bit fields: + * - GPIO Mode [ 0 : 1 ] + * - GPIO Schmitt Trigger [ 2 ] + * - GPIO Drive Strength [ 3 : 4 ] + */ + +/* GPIO Pull-up/pull-down/High impedance */ +#define BFLB_GPIO_MODE_POS 0U +#define BFLB_GPIO_MODE_MASK 0x3 +#define BFLB_GPIO_MODE_HIGH_IMPEDANCE (0x0 << BFLB_GPIO_MODE_POS) +#define BFLB_GPIO_MODE_PULL_UP (0x1 << BFLB_GPIO_MODE_POS) +#define BFLB_GPIO_MODE_PULL_DOWN (0x2 << BFLB_GPIO_MODE_POS) +#define BFLB_CFG_2_GPIO_MODE(cfg) (((cfg) >> BFLB_GPIO_MODE_POS) & BFLB_GPIO_MODE_MASK) + +/* GPIO Input Schmitt trigger */ +#define BFLB_GPIO_INP_SMT_POS 2U +#define BFLB_GPIO_INP_SMT_MASK 0x1 +#define BFLB_GPIO_INP_SMT_EN (0x1 << BFLB_GPIO_INP_SMT_POS) +#define BFLB_CFG_2_GPIO_INP_SMT(cfg) (((cfg) >> BFLB_GPIO_INP_SMT_POS) & BFLB_GPIO_INP_SMT_MASK) + +/* GPIO Output Drive Strength */ +#define BFLB_GPIO_DRV_STR_POS 3U +#define BFLB_GPIO_DRV_STR_MASK 0x3 +#define BFLB_CFG_2_GPIO_DRV_STR(cfg) (((cfg) >> BFLB_GPIO_DRV_STR_POS) & BFLB_GPIO_DRV_STR_MASK) + +#endif /* ZEPHYR_BFLB_PINCTRL_H_ */ diff --git a/modules/Kconfig b/modules/Kconfig index 6cf510adcce14..3a599534d168d 100644 --- a/modules/Kconfig +++ b/modules/Kconfig @@ -46,6 +46,9 @@ comment "Unavailable modules, please install those via the project manifest." # config ZEPHYR__MODULE # bool +comment "hal_bouffalolab module not available." + depends on !ZEPHYR_HAL_BOUFFALOLAB_MODULE + comment "hal_gigadevice module not available." depends on !ZEPHYR_HAL_GIGADEVICE_MODULE diff --git a/modules/hal_bouffalolab/CMakeLists.txt b/modules/hal_bouffalolab/CMakeLists.txt new file mode 100644 index 0000000000000..edb14061323e0 --- /dev/null +++ b/modules/hal_bouffalolab/CMakeLists.txt @@ -0,0 +1,61 @@ + +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_FAMILY_BFLB) + +zephyr_library_named(hal_bouffalolab) + +zephyr_compile_definitions( + ARCH_RISCV +) + +zephyr_library_compile_definitions( + BFLB_USE_HAL_DRIVER + BFLB_USE_CUSTOM_LD_SECTIONS +) + +set(bflb_soc ${CONFIG_SOC_SUB_SERIES}) +set(bflb_drv_dir ${ZEPHYR_HAL_BOUFFALOLAB_MODULE_DIR}/drivers/${bflb_soc}_driver) +set(bflb_common_dir ${ZEPHYR_HAL_BOUFFALOLAB_MODULE_DIR}/common) +set(bflb_drv_src_dir ${bflb_drv_dir}/std_drv/src) + +# Global includes to be used outside hal_gigadevice +zephyr_include_directories( + include + + ${bflb_drv_dir}/regs + ${bflb_drv_dir}/startup + ${bflb_drv_dir}/std_drv/inc + + ${bflb_common_dir}/misc +) + +zephyr_library_include_directories( + ${bflb_common_dir}/soft_crc +) + +zephyr_library_sources( + ${bflb_drv_src_dir}/${bflb_soc}_aon.c + ${bflb_drv_src_dir}/${bflb_soc}_ef_ctrl.c + ${bflb_drv_src_dir}/${bflb_soc}_glb.c + ${bflb_drv_src_dir}/${bflb_soc}_hbn.c + ${bflb_drv_src_dir}/${bflb_soc}_l1c.c + ${bflb_drv_src_dir}/${bflb_soc}_pds.c + ${bflb_drv_src_dir}/${bflb_soc}_romapi.c + + ${bflb_common_dir}/soft_crc/softcrc.c +) + + + +zephyr_library_sources_ifdef(CONFIG_USE_BFLB_ACOMP ${bflb_drv_src_dir}/${bflb_soc}_acomp.c) +zephyr_library_sources_ifdef(CONFIG_USE_BFLB_ADC ${bflb_drv_src_dir}/${bflb_soc}_adc.c) +zephyr_library_sources_ifdef(CONFIG_USE_BFLB_DAC ${bflb_drv_src_dir}/${bflb_soc}_dac.c) +zephyr_library_sources_ifdef(CONFIG_USE_BFLB_DMA ${bflb_drv_src_dir}/${bflb_soc}_dma.c) +zephyr_library_sources_ifdef(CONFIG_USE_BFLB_I2C ${bflb_drv_src_dir}/${bflb_soc}_i2c.c) +zephyr_library_sources_ifdef(CONFIG_USE_BFLB_IR ${bflb_drv_src_dir}/${bflb_soc}_ir.c) +zephyr_library_sources_ifdef(CONFIG_USE_BFLB_PWM ${bflb_drv_src_dir}/${bflb_soc}_pwm.c) +zephyr_library_sources_ifdef(CONFIG_USE_BFLB_SPI ${bflb_drv_src_dir}/${bflb_soc}_spi.c) +zephyr_library_sources_ifdef(CONFIG_USE_BFLB_UART ${bflb_drv_src_dir}/${bflb_soc}_uart.c) + +endif() diff --git a/modules/hal_bouffalolab/Kconfig b/modules/hal_bouffalolab/Kconfig new file mode 100644 index 0000000000000..801fa4b3c4878 --- /dev/null +++ b/modules/hal_bouffalolab/Kconfig @@ -0,0 +1,58 @@ +# Copyright (c) 2021 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config ZEPHYR_HAL_BOUFFALOLAB_MODULE + bool + +config HAS_BFLB_HAL + bool + +if HAS_BFLB_HAL + +config USE_BFLB_ACOMP + bool + help + Enable BFLB Analog Comparator (ACOMP) HAL module driver + +config USE_BFLB_ADC + bool + help + Enable BFLB Analog-to-Digital Converter (ADC) HAL module driver + +config USE_BFLB_DAC + bool + help + Enable BFLB Digital-to-Analog Converter (DAC) HAL module driver + +config USE_BFLB_DMA + bool + help + Enable BFLB Direct Memory Access controller (DMA) HAL module driver + +config USE_BFLB_I2C + bool + help + Enable BFLB Inter-Integrated Circuit Interface (I2C) HAL module driver + +config USE_BFLB_IR + bool + help + Enable BFLB Infrared Remote controller (IR) HAL module driver + +config USE_BFLB_PWM + bool + help + Enable BFLB Pulse Width Modulation (PMU) HAL module driver + +config USE_BFLB_SPI + bool + help + Enable BFLB Serial Peripheral Interface(SPI) HAL module driver + +config USE_BFLB_UART + bool + help + Enable BFLB Universal Asynchronous Receiver/Transmitter (UART) + HAL module driver + +endif # HAS_BFLB_HAL diff --git a/modules/hal_bouffalolab/include/bflb_glb.h b/modules/hal_bouffalolab/include/bflb_glb.h new file mode 100644 index 0000000000000..d04d67c62a520 --- /dev/null +++ b/modules/hal_bouffalolab/include/bflb_glb.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2021 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_HAL_BFLB_GLB_H_ +#define ZEPHYR_HAL_BFLB_GLB_H_ + +#ifdef CONFIG_SOC_SERIES_BL6 + #include +#endif + +#endif /* ZEPHYR_HAL_BFLB_GLB_H_ */ diff --git a/modules/hal_bouffalolab/include/bflb_gpio.h b/modules/hal_bouffalolab/include/bflb_gpio.h new file mode 100644 index 0000000000000..769c4db3c25f5 --- /dev/null +++ b/modules/hal_bouffalolab/include/bflb_gpio.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2021 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_HAL_BFLB_GPIO_H_ +#define ZEPHYR_HAL_BFLB_GPIO_H_ + +#ifdef CONFIG_SOC_SERIES_BL6 + #include +#endif + +#endif /* ZEPHYR_HAL_BFLB_GPIO_H_ */ diff --git a/modules/hal_bouffalolab/include/bflb_hbn.h b/modules/hal_bouffalolab/include/bflb_hbn.h new file mode 100644 index 0000000000000..9b0e4eee1f05c --- /dev/null +++ b/modules/hal_bouffalolab/include/bflb_hbn.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2021 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_HAL_BFLB_HBN_H_ +#define ZEPHYR_HAL_BFLB_HBN_H_ + +#ifdef CONFIG_SOC_SERIES_BL6 + #include +#endif + +#endif /* ZEPHYR_HAL_BFLB_HBN_H_ */ diff --git a/modules/hal_bouffalolab/include/bflb_uart.h b/modules/hal_bouffalolab/include/bflb_uart.h new file mode 100644 index 0000000000000..8173f21df4b5b --- /dev/null +++ b/modules/hal_bouffalolab/include/bflb_uart.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2021 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_HAL_BFLB_UART_H_ +#define ZEPHYR_HAL_BFLB_UART_H_ + +#ifdef CONFIG_SOC_SERIES_BL6 + #include +#endif + +#endif /* ZEPHYR_HAL_BFLB_UART_H_ */ diff --git a/modules/hal_bouffalolab/include/bl_ld_sections.h b/modules/hal_bouffalolab/include/bl_ld_sections.h new file mode 100644 index 0000000000000..69e3ef3ba9864 --- /dev/null +++ b/modules/hal_bouffalolab/include/bl_ld_sections.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2021 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __BL_LD_SECTIONS_H +#define __BL_LD_SECTIONS_H + +#define ATTR_STRINGIFY(x) #x +#define ATTR_TOSTRING(x) ATTR_STRINGIFY(x) +#define ATTR_UNI_SYMBOL __FILE__ ATTR_TOSTRING(__LINE__) +#define ATTR_CLOCK_SECTION __attribute__((section(".itcm.sclock_rlt_code." ATTR_UNI_SYMBOL))) +#define ATTR_CLOCK_CONST_SECTION __attribute__((section(".itcm.sclock_rlt_const." ATTR_UNI_SYMBOL))) +#define ATTR_TCM_SECTION __attribute__((section(".itcm.code." ATTR_UNI_SYMBOL))) +#define ATTR_TCM_CONST_SECTION __attribute__((section(".itcm.const." ATTR_UNI_SYMBOL))) +#define ATTR_DTCM_SECTION __attribute__((section(".dtcm.data"))) +#define ATTR_HSRAM_SECTION __attribute__((section(".hsram_code"))) +#define ATTR_DMA_RAM_SECTION __attribute__((section(".system_ram"))) +#define ATTR_HBN_RAM_SECTION __attribute__((section(".hbn_ram_code"))) +#define ATTR_HBN_RAM_CONST_SECTION __attribute__((section(".hbn_ram_data"))) +#define ATTR_FALLTHROUGH() __attribute__((fallthrough)) +#define ATTR_USED __attribute__((__used__)) +#define ATTR_EALIGN(x) __aligned(size) + +#endif /* __BL_LD_SECTIONS_H */ diff --git a/scripts/west_commands/runners/__init__.py b/scripts/west_commands/runners/__init__.py index eb4816a9e1d12..167b59fd8f248 100644 --- a/scripts/west_commands/runners/__init__.py +++ b/scripts/west_commands/runners/__init__.py @@ -26,6 +26,7 @@ def _import_runner_module(runner_name): _names = [ 'blackmagicprobe', + 'blflash', 'bossac', 'canopen_program', 'dediprog', diff --git a/scripts/west_commands/runners/blflash.py b/scripts/west_commands/runners/blflash.py new file mode 100644 index 0000000000000..0fca611b2f6e9 --- /dev/null +++ b/scripts/west_commands/runners/blflash.py @@ -0,0 +1,59 @@ +# Copyright (c) 2021 Gerson Fernando Budke +# +# SPDX-License-Identifier: Apache-2.0 + +'''Bouffalo Lab flash tool (blflash) runner for serial boot ROM''' + +from runners.core import ZephyrBinaryRunner, RunnerCaps + +DEFAULT_BLFLASH_PORT = '/dev/ttyUSB0' +DEFAULT_BLFLASH_SPEED = '2000000' + +class BlFlashBinaryRunner(ZephyrBinaryRunner): + '''Runner front-end for blflash.''' + + def __init__(self, cfg, blflash='blflash', + port=DEFAULT_BLFLASH_PORT, + speed=DEFAULT_BLFLASH_SPEED): + super().__init__(cfg) + self.blflash = blflash + self.port = port + self.speed = speed + + @classmethod + def name(cls): + return 'blflash' + + @classmethod + def capabilities(cls): + return RunnerCaps(commands={'flash'}) + + @classmethod + def do_add_parser(cls, parser): + parser.add_argument('--blflash', default='blflash', + help='path to blflash, default is blflash') + parser.add_argument('--port', default=DEFAULT_BLFLASH_PORT, + help='serial port to use, default is ' + + str(DEFAULT_BLFLASH_PORT)) + parser.add_argument('--speed', default=DEFAULT_BLFLASH_SPEED, + help='serial port speed to use, default is ' + + DEFAULT_BLFLASH_SPEED) + + @classmethod + def do_create(cls, cfg, args): + return BlFlashBinaryRunner(cfg, + blflash=args.blflash, + port=args.port, + speed=args.speed) + + def do_run(self, command, **kwargs): + self.require(self.blflash) + self.ensure_output('bin') + + cmd_flash = [self.blflash, + 'flash', + self.cfg.bin_file, + '-p', self.port, + '-b', self.speed] + + self.check_call(cmd_flash) diff --git a/scripts/west_commands/tests/test_imports.py b/scripts/west_commands/tests/test_imports.py index 079f6b7607ae6..8aeba86eb85ac 100644 --- a/scripts/west_commands/tests/test_imports.py +++ b/scripts/west_commands/tests/test_imports.py @@ -16,6 +16,7 @@ def test_runner_imports(): # Please keep this sorted alphabetically. expected = set(('arc-nsim', 'blackmagicprobe', + 'blflash', 'bossac', 'canopen', 'dediprog', diff --git a/soc/riscv/bouffalolab/CMakeLists.txt b/soc/riscv/bouffalolab/CMakeLists.txt new file mode 100644 index 0000000000000..4a02603db81f5 --- /dev/null +++ b/soc/riscv/bouffalolab/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2021, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +add_subdirectory(common) +add_subdirectory(${SOC_SERIES}) diff --git a/soc/riscv/bouffalolab/Kconfig b/soc/riscv/bouffalolab/Kconfig new file mode 100644 index 0000000000000..950a4918735dd --- /dev/null +++ b/soc/riscv/bouffalolab/Kconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_BFLB + bool + select HAS_BFLB_HAL + select BUILD_OUTPUT_HEX + select PINCTRL + +config SOC_FAMILY + string + default "bouffalolab" + depends on SOC_FAMILY_BFLB + +if SOC_FAMILY_BFLB + +source "soc/riscv/bouffalolab/*/Kconfig.soc" + +endif # SOC_FAMILY_BFLB diff --git a/soc/riscv/bouffalolab/Kconfig.defconfig b/soc/riscv/bouffalolab/Kconfig.defconfig new file mode 100644 index 0000000000000..a8c37dd291008 --- /dev/null +++ b/soc/riscv/bouffalolab/Kconfig.defconfig @@ -0,0 +1,4 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +source "soc/riscv/bouffalolab/*/Kconfig.defconfig.series" diff --git a/soc/riscv/bouffalolab/Kconfig.soc b/soc/riscv/bouffalolab/Kconfig.soc new file mode 100644 index 0000000000000..68c645781f421 --- /dev/null +++ b/soc/riscv/bouffalolab/Kconfig.soc @@ -0,0 +1,4 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +source "soc/riscv/bouffalolab/*/Kconfig.series" diff --git a/soc/riscv/bouffalolab/bflb/CMakeLists.txt b/soc/riscv/bouffalolab/bflb/CMakeLists.txt new file mode 100644 index 0000000000000..73221684eaadf --- /dev/null +++ b/soc/riscv/bouffalolab/bflb/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2021, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_include_directories(.) +zephyr_sources(soc.c) + +zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_BFLB RODATA rodata.ld) diff --git a/soc/riscv/bouffalolab/bflb/Kconfig.defconfig.bl6 b/soc/riscv/bouffalolab/bflb/Kconfig.defconfig.bl6 new file mode 100644 index 0000000000000..c8e76e31c833f --- /dev/null +++ b/soc/riscv/bouffalolab/bflb/Kconfig.defconfig.bl6 @@ -0,0 +1,25 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_BL6 + +config SOC_SERIES + default "bflb" + +config SOC_SUB_SERIES + string + default "bl602" + +config SOC_PART_NUMBER + string + default "bl602c00q2i" if SOC_PART_NUMBER_BL602C00Q2I + default "bl602c20q2i" if SOC_PART_NUMBER_BL602C20Q2I + default "bl604e20q2i" if SOC_PART_NUMBER_BL604C20Q2I + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 192000000 + +config NUM_IRQS + default 64 + +endif # SOC_SERIES_BL6 diff --git a/soc/riscv/bouffalolab/bflb/Kconfig.defconfig.series b/soc/riscv/bouffalolab/bflb/Kconfig.defconfig.series new file mode 100644 index 0000000000000..4cb7f20c4b52a --- /dev/null +++ b/soc/riscv/bouffalolab/bflb/Kconfig.defconfig.series @@ -0,0 +1,4 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +source "soc/riscv/bouffalolab/bflb/Kconfig.defconfig.bl*" diff --git a/soc/riscv/bouffalolab/bflb/Kconfig.series b/soc/riscv/bouffalolab/bflb/Kconfig.series new file mode 100644 index 0000000000000..195502b12a43a --- /dev/null +++ b/soc/riscv/bouffalolab/bflb/Kconfig.series @@ -0,0 +1,15 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_BL6 + bool "Bouffalo Lab BL6 series MCU" + select RISCV +# select RISCV_GP + select RISCV_HAS_CPU_IDLE + select RISCV_MACHINE_TIMER + select ATOMIC_OPERATIONS_C + select COMPRESSED_ISA + select SOC_FAMILY_BFLB + select CPU_HAS_FPU + help + Enable support for Bouffalo Lab BL6 MCU series diff --git a/soc/riscv/bouffalolab/bflb/Kconfig.soc b/soc/riscv/bouffalolab/bflb/Kconfig.soc new file mode 100644 index 0000000000000..c17d43c3b4102 --- /dev/null +++ b/soc/riscv/bouffalolab/bflb/Kconfig.soc @@ -0,0 +1,4 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +source "soc/riscv/bouffalolab/bflb/Kconfig.soc.bl*" diff --git a/soc/riscv/bouffalolab/bflb/Kconfig.soc.bl6 b/soc/riscv/bouffalolab/bflb/Kconfig.soc.bl6 new file mode 100644 index 0000000000000..a946f365d4045 --- /dev/null +++ b/soc/riscv/bouffalolab/bflb/Kconfig.soc.bl6 @@ -0,0 +1,17 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "bouffalo Lab BL6 MCU Selection" + depends on SOC_SERIES_BL6 + + config SOC_PART_NUMBER_BL602C00Q2I + bool "BL602C00Q2I" + + config SOC_PART_NUMBER_BL602C20Q2I + bool "BL602C20Q2I" + + config SOC_PART_NUMBER_BL604C20Q2I + bool "BL604E20Q2I" + +endchoice diff --git a/soc/riscv/bouffalolab/bflb/linker.ld b/soc/riscv/bouffalolab/bflb/linker.ld new file mode 100644 index 0000000000000..4b7aedd9f9616 --- /dev/null +++ b/soc/riscv/bouffalolab/bflb/linker.ld @@ -0,0 +1,6 @@ +/* + * Copyright (c) 2021, ATL Electronics + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/riscv/bouffalolab/bflb/rodata.ld b/soc/riscv/bouffalolab/bflb/rodata.ld new file mode 100644 index 0000000000000..8c5b01869bd6a --- /dev/null +++ b/soc/riscv/bouffalolab/bflb/rodata.ld @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2021, ATL Electronics + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#if defined(CONFIG_SOC_SERIES_BL6) + +KEEP(*(SORT_NONE( EXCLUDE_FILE( *bl602_glb.o \ + *bl602_pds.o \ + *bl602_common.o \ + *bl602_sf_cfg.o \ + *bl602_sf_cfg_ext*.o* \ + *bl602_sf_ctrl.o \ + *bl602_sflash.o \ + *bl602_sflash_ext*.o* \ + *bl602_xip_sflash.o \ + *bl602_xip_sflash_ext*.o* \ + *bl602_ef_ctrl.o) .rodata*))) + +#endif diff --git a/soc/riscv/bouffalolab/bflb/soc.c b/soc/riscv/bouffalolab/bflb/soc.c new file mode 100644 index 0000000000000..9187f5cec9d2f --- /dev/null +++ b/soc/riscv/bouffalolab/bflb/soc.c @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2021, ATL Electronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Bouffalo Lab RISC-V MCU series initialization code + */ + +#include +#include + +#include +#include +#include + +#define ROOT_FCLK_DIV (0) +#define ROOT_BCLK_DIV (1) +#define ROOT_UART_CLOCK_DIV (0) + +static void system_bor_init(void) +{ + HBN_BOR_CFG_Type borCfg = { 1 /* pu_bor */, 0 /* irq_bor_en */, + 1 /* bor_vth */, 1 /* bor_sel */ }; + HBN_Set_BOR_Cfg(&borCfg); +} + +static uint32_t mtimer_get_clk_src_div(void) +{ + return ((SystemCoreClockGet() / (GLB_Get_BCLK_Div() + 1)) + / 1000 / 1000 - 1); +} + +static void system_clock_init(void) +{ + GLB_Set_System_CLK(GLB_PLL_XTAL_40M, GLB_SYS_CLK_PLL160M); + GLB_Set_System_CLK_Div(ROOT_FCLK_DIV, ROOT_BCLK_DIV); + GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div()); +} + +static void peripheral_clock_init(void) +{ + GLB_Set_UART_CLK(1, HBN_UART_CLK_160M, ROOT_UART_CLOCK_DIV); +} + +#ifdef CONFIG_RISCV_GP +ulong_t __soc_get_gp_initial_value(void) +{ + extern uint32_t __global_pointer$; + return (ulong_t)&__global_pointer$; +} +#endif + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ + +static int bl_riscv_init(const struct device *arg) +{ + uint32_t key; + uint32_t *p; + uint32_t i = 0; + uint32_t tmpVal = 0; + + ARG_UNUSED(arg); + + key = irq_lock(); + + __disable_irq(); + + /* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */ + tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); + tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD); + BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); + + /* GLB_Set_EM_Sel(GLB_EM_0KB); */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, GLB_EM_0KB); + BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal); + + /* Fix 26M xtal clkpll_sdmin */ + tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM); + + if (BL_GET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN) == 0x49D39D) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x49D89E); + BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmpVal); + } + + /* Restore default setting*/ + + /* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, UART_SIG_SWAP_NONE); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + /* GLB_JTAG_Sig_Swap_Set(JTAG_SIG_SWAP_NONE); */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_JTAG_SWAP_SET, JTAG_SIG_SWAP_NONE); + BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); + + /* CLear all interrupt */ + p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIE); + + for (i = 0; i < (IRQn_LAST + 3) / 4; i++) { + p[i] = 0; + } + + p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIP); + + for (i = 0; i < (IRQn_LAST + 3) / 4; i++) { + p[i] = 0; + } + + /* init bor for all platform */ + system_bor_init(); + /* global IRQ enable */ + __enable_irq(); + + system_clock_init(); + peripheral_clock_init(); + + irq_unlock(key); + + return 0; +} + +/* identify flash config automatically */ +extern BL_Err_Type flash_init(void); + +void System_Post_Init(void) +{ + PDS_Trim_RC32M(); + HBN_Trim_RC32K(); + flash_init(); +} + +SYS_INIT(bl_riscv_init, PRE_KERNEL_1, 0); diff --git a/soc/riscv/bouffalolab/bflb/soc.h b/soc/riscv/bouffalolab/bflb/soc.h new file mode 100644 index 0000000000000..a3a06b6c9de88 --- /dev/null +++ b/soc/riscv/bouffalolab/bflb/soc.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2021, ATL Electronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Board configuration macros + * + * This header file is used to specify and describe board-level aspects + */ + +#ifndef _SOC__H_ +#define _SOC__H_ + +#include +#include <../common/soc_common.h> + +#ifndef _ASMLANGUAGE + +/* Add include for DTS generated information */ +#include + +#if defined(CONFIG_SOC_SERIES_BL6) +#include +#else +#error Library does not support the specified device. +#endif + +/* RISC-V Machine Timer configuration */ +#define RISCV_MTIME_BASE 0x0200BFF8 +#define RISCV_MTIMECMP_BASE 0x02004000 + +/* lib-c hooks required RAM defined variables */ +#define RISCV_RAM_BASE DT_SRAM_BASE_ADDRESS +#define RISCV_RAM_SIZE KB(DT_SRAM_SIZE) + +#define SOC_BOUFFALOLAB_BL_PLL160_FREQ_HZ (160000000) +#define SOC_BOUFFALOLAB_BL_HCLK_FREQ_HZ \ + DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) + +#ifdef CONFIG_RISCV_GP +ulong_t __soc_get_gp_initial_value(void); +#endif + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC__H_ */ diff --git a/soc/riscv/bouffalolab/common/CMakeLists.txt b/soc/riscv/bouffalolab/common/CMakeLists.txt new file mode 100644 index 0000000000000..50ee91a2c33bd --- /dev/null +++ b/soc/riscv/bouffalolab/common/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + idle.c + soc_irq.S + soc_common_irq.c + vector.S + ) diff --git a/soc/riscv/bouffalolab/common/clic.h b/soc/riscv/bouffalolab/common/clic.h new file mode 100644 index 0000000000000..f13de0dfe4ba8 --- /dev/null +++ b/soc/riscv/bouffalolab/common/clic.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021, ATL Electronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SIFIVE_CLIC_H +#define _SIFIVE_CLIC_H + +#define CLIC_CTRL_ADDR 0x02000000UL +#define CLIC_HART0_ADDR 0x02800000UL + +#define CLIC_MSIP 0x0000 +#define CLIC_MSIP_size 0x4 +#define CLIC_MTIMECMP 0x4000 +#define CLIC_MTIMECMP_size 0x8 +#define CLIC_MTIME 0xBFF8 +#define CLIC_MTIME_size 0x8 + +#define CLIC_INTIP 0x000 +#define CLIC_INTIE 0x400 +#define CLIC_INTCFG 0x800 +#define CLIC_CFG 0xc00 + +#endif /* _SIFIVE_CLIC_H */ diff --git a/soc/riscv/bouffalolab/common/idle.c b/soc/riscv/bouffalolab/common/idle.c new file mode 100644 index 0000000000000..d14bac3fed013 --- /dev/null +++ b/soc/riscv/bouffalolab/common/idle.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2017 Jean-Paul Etienne + * Contributors: 2018 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include + +static ALWAYS_INLINE void riscv_idle(unsigned int key) +{ + sys_trace_idle(); + /* unlock interrupts */ + irq_unlock(key); + + /* Wait for interrupt */ + __asm__ volatile("wfi"); +} + +/** + * + * @brief Power save idle routine + * + * This function will be called by the kernel idle loop or possibly within + * an implementation of _pm_save_idle in the kernel when the + * '_pm_save_flag' variable is non-zero. + * + * @return N/A + */ +void arch_cpu_idle(void) +{ + riscv_idle(MSTATUS_IEN); +} + +/** + * + * @brief Atomically re-enable interrupts and enter low power mode + * + * INTERNAL + * The requirements for arch_cpu_atomic_idle() are as follows: + * 1) The enablement of interrupts and entering a low-power mode needs to be + * atomic, i.e. there should be no period of time where interrupts are + * enabled before the processor enters a low-power mode. See the comments + * in k_lifo_get(), for example, of the race condition that + * occurs if this requirement is not met. + * + * 2) After waking up from the low-power mode, the interrupt lockout state + * must be restored as indicated in the 'imask' input parameter. + * + * @return N/A + */ +void arch_cpu_atomic_idle(unsigned int key) +{ + riscv_idle(key); +} diff --git a/soc/riscv/bouffalolab/common/oldvector.S b/soc/riscv/bouffalolab/common/oldvector.S new file mode 100644 index 0000000000000..a084f140f906d --- /dev/null +++ b/soc/riscv/bouffalolab/common/oldvector.S @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2017 Jean-Paul Etienne + * Contributors: 2018 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#define __metal_chicken_bit 0 + +/* exports */ +GTEXT(__start) + +/* imports */ +GTEXT(__initialize) +GTEXT(__irq_wrapper) + +SECTION_FUNC(exception, ivt) + .option norvc + + /* Interrupts */ + j __irq_wrapper /* IRQ 0 */ + j __irq_wrapper /* IRQ 1 */ + j __irq_wrapper /* IRQ 2 */ + j __irq_wrapper /* IRQ 3 - clic_msip */ + j __irq_wrapper /* IRQ 4 */ + j __irq_wrapper /* IRQ 5 */ + j __irq_wrapper /* IRQ 6 */ + j __irq_wrapper /* IRQ 7 - clic_mtimer */ + j __irq_wrapper /* IRQ 8 - ? */ + j __irq_wrapper /* IRQ 9 - ? */ + j __irq_wrapper /* IRQ 10 - ? */ + j __irq_wrapper /* IRQ 11 - clic_mext */ + j __irq_wrapper /* IRQ 12 - clic_csoft */ + j __irq_wrapper /* IRQ 13 - ? */ + j __irq_wrapper /* IRQ 14 - Debug interrupt */ + j __irq_wrapper /* IRQ 15 */ + + /* CLIC Local Interrupts */ + j __irq_wrapper /* IRQ 16 + 0 - BMX_ERR */ + j __irq_wrapper /* IRQ 16 + 1 - BMX_TO */ + j __irq_wrapper /* IRQ 16 + 2 - L1C_BMX_ERR */ + j __irq_wrapper /* IRQ 16 + 3 - L1C_BMX_TO */ + j __irq_wrapper /* IRQ 16 + 4 - SEC_BMX_ERR */ + j __irq_wrapper /* IRQ 16 + 5 - RF_TOP_INT0 */ + j __irq_wrapper /* IRQ 16 + 6 - RF_TOP_INT1 */ + j __irq_wrapper /* IRQ 16 + 7 - SDIO */ + j __irq_wrapper /* IRQ 16 + 8 - DMA_BMX_ERR */ + j __irq_wrapper /* IRQ 16 + 9 - SEC_GMAC */ + j __irq_wrapper /* IRQ 16 + 10 - SEC_CDET */ + j __irq_wrapper /* IRQ 16 + 11 - SEC_PKA */ + j __irq_wrapper /* IRQ 16 + 12 - SEC_TRNG */ + j __irq_wrapper /* IRQ 16 + 13 - SEC_AES */ + j __irq_wrapper /* IRQ 16 + 14 - SEC_SHA */ + j __irq_wrapper /* IRQ 16 + 15 - DMA_ALL */ + j __irq_wrapper /* IRQ 16 + 16 */ + j __irq_wrapper /* IRQ 16 + 17 */ + j __irq_wrapper /* IRQ 16 + 18 */ + j __irq_wrapper /* IRQ 16 + 19 - IRTX */ + j __irq_wrapper /* IRQ 16 + 20 - IRRX */ + j __irq_wrapper /* IRQ 16 + 21 */ + j __irq_wrapper /* IRQ 16 + 22 */ + j __irq_wrapper /* IRQ 16 + 23 - SF_CTRL */ + j __irq_wrapper /* IRQ 16 + 24 */ + j __irq_wrapper /* IRQ 16 + 25 - GPADC_DMA */ + j __irq_wrapper /* IRQ 16 + 26 - EFUSE */ + j __irq_wrapper /* IRQ 16 + 27 - SPI */ + j __irq_wrapper /* IRQ 16 + 28 */ + j __irq_wrapper /* IRQ 16 + 29 - UART0 */ + j __irq_wrapper /* IRQ 16 + 30 - UART1 */ + j __irq_wrapper /* IRQ 16 + 31 */ + j __irq_wrapper /* IRQ 16 + 32 - I2C */ + j __irq_wrapper /* IRQ 16 + 33 */ + j __irq_wrapper /* IRQ 16 + 34 - PWM */ + j __irq_wrapper /* IRQ 16 + 35 */ + j __irq_wrapper /* IRQ 16 + 36 - TIMER_CH0 */ + j __irq_wrapper /* IRQ 16 + 37 - TIMER_CH1 */ + j __irq_wrapper /* IRQ 16 + 38 - TIMER_WDT */ + j __irq_wrapper /* IRQ 16 + 39 */ + j __irq_wrapper /* IRQ 16 + 40 */ + j __irq_wrapper /* IRQ 16 + 41 */ + j __irq_wrapper /* IRQ 16 + 42 */ + j __irq_wrapper /* IRQ 16 + 43 */ + j __irq_wrapper /* IRQ 16 + 44 - GPIO_INT0 */ + j __irq_wrapper /* IRQ 16 + 45 */ + j __irq_wrapper /* IRQ 16 + 46 */ + j __irq_wrapper /* IRQ 16 + 47 */ + j __irq_wrapper /* IRQ 16 + 48 */ + j __irq_wrapper /* IRQ 16 + 49 */ + j __irq_wrapper /* IRQ 16 + 50 - PDS_WAKEUP */ + j __irq_wrapper /* IRQ 16 + 51 - HBN_OUT0 */ + j __irq_wrapper /* IRQ 16 + 52 - HBN_OUT1 */ + j __irq_wrapper /* IRQ 16 + 53 - BOR */ + j __irq_wrapper /* IRQ 16 + 54 - WIFI */ + j __irq_wrapper /* IRQ 16 + 55 - BZ_PHY */ + j __irq_wrapper /* IRQ 16 + 56 - BLE */ + j __irq_wrapper /* IRQ 16 + 57 - MAC_TXRX_TIMER */ + j __irq_wrapper /* IRQ 16 + 58 - MAC_TXRX_MISC */ + j __irq_wrapper /* IRQ 16 + 59 - MAC_RX_TRG */ + j __irq_wrapper /* IRQ 16 + 60 - MAC_TX_TRG */ + j __irq_wrapper /* IRQ 16 + 61 - MAC_GEN */ + j __irq_wrapper /* IRQ 16 + 62 - MAC_PORT */ + j __irq_wrapper /* IRQ 16 + 63 - WIFI_IPC */ + +SECTION_FUNC(vectors, __start) + .cfi_startproc + + .option norvc + + /* Inform the debugger that there is nowhere to backtrace */ + .cfi_undefined ra + + /* Disable interrupts */ + li t0, MSTATUS_MIE + csrc mstatus, t0 + + /* The absolute first thing that must happen is configuring the global + * pointer register, which must be done with relaxation disabled + * because it's not valid to obtain the address of any symbol without + * GP configured. The C environment might go ahead and do this again, + * but that's safe as it's a fixed register. */ + .option push + .option norelax + la gp, __data_global_pointer + .option pop + + /* Set mtvec (Machine Trap-Vector Base-Address Register) */ + la t0, __irq_wrapper + + /* enable CLIC Vectored mode */ + /* ori t0, t0, 3 */ + /* enable CLINT Direct mode */ + ori t0, t0, 0 + csrw mtvec, t0 + + /* enable chicken bit if core is bullet series*/ + la t0, __metal_chicken_bit + beqz t0, 1f + csrwi 0x7C1, 0 +1: + + /* Check for an initialization routine and call it if one exists, + * otherwise just skip over the call entirely. Note that + * __metal_initialize isn't actually a full C function, as it doesn't + * end up with the .bss or .data segments having been initialized. + * This is done to avoid putting a burden on systems that can be + * initialized without having a C environment set up.*/ + call SystemInit + + /* start load code to itcm like.*/ + call start_load + + /* Jump to __initialize */ + tail __initialize + + .cfi_endproc diff --git a/soc/riscv/bouffalolab/common/pinctrl_soc.h b/soc/riscv/bouffalolab/common/pinctrl_soc.h new file mode 100644 index 0000000000000..7853d8a1da8a8 --- /dev/null +++ b/soc/riscv/bouffalolab/common/pinctrl_soc.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2021 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * Bouffalo Lab SoC specific helpers for pinctrl driver + */ + +#ifndef ZEPHYR_SOC_RISCV_BFLB_COMMON_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_RISCV_BFLB_COMMON_PINCTRL_SOC_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** @cond INTERNAL_HIDDEN */ + +typedef struct pinctrl_soc_pin { + uint16_t fun; + uint16_t cfg; + uint8_t pin; + uint8_t flags; +} pinctrl_soc_pin_t; + +/** + * @brief Utility macro to initialize fun field in #pinctrl_soc_pin_t. + * + * @param node_id Node identifier. + */ +#define Z_PINCTRL_BFLB_FUN_INIT(node_id, prop, idx) \ + ( \ + DT_PHA_BY_IDX(node_id, prop, idx, fun) | \ + (BFLB_FUN_MODE_INPUT * DT_PROP_OR(node_id, input_enable, 0)) | \ + (BFLB_FUN_MODE_OUTPUT * DT_PROP_OR(node_id, output_enable, 0)) \ + ) + +/** + * @brief Utility macro to initialize flags field in #pinctrl_soc_pin_t. + * + * @param node_id Node identifier. + */ +#define Z_PINCTRL_BFLB_CFG_INIT(node_id) \ + ( \ + (BFLB_GPIO_MODE_PULL_UP * DT_PROP_OR(node_id, bias_pull_up, 0)) | \ + (BFLB_GPIO_MODE_PULL_DOWN * DT_PROP_OR(node_id, bias_pull_down, 0)) | \ + (BFLB_GPIO_INP_SMT_EN * DT_PROP_OR(node_id, input_schmitt_enable, 0)) |\ + (DT_PROP_OR(node_id, drive_strength, 0) << BFLB_GPIO_DRV_STR_POS) \ + ) + +/** + * @brief Utility macro to initialize pin field in #pinctrl_soc_pin_t. + * + * @param node_id Node identifier. + */ +#define Z_PINCTRL_BFLB_PIN_INIT(node_id, prop, idx) \ + DT_PHA_BY_IDX(node_id, prop, idx, pin) + +/** + * @brief Utility macro to initialize flags field in #pinctrl_soc_pin_t. + * + * @param node_id Node identifier. + */ +#define Z_PINCTRL_BFLB_FLAGS_INIT(node_id, prop, idx) \ + COND_CODE_1(DT_PROP_HAS_IDX(node_id, prop, idx), \ + (DT_PROP_BY_IDX(node_id, prop, idx)), (0)) + +/** + * @brief Utility macro to initialize each pin. + * + * @param node_id Node identifier. + * @param prop Property name. + * @param idx Property entry index. + */ +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ + { .fun = Z_PINCTRL_BFLB_FUN_INIT(node_id, prop, idx), \ + .cfg = Z_PINCTRL_BFLB_CFG_INIT(node_id), \ + .pin = Z_PINCTRL_BFLB_PIN_INIT(node_id, prop, idx), \ + .flags = Z_PINCTRL_BFLB_FLAGS_INIT(node_id, bflb_signals, idx), \ + }, + +/** + * @brief Utility macro to initialize state pins contained in a given property. + * + * @param node_id Node identifier. + * @param prop Property name describing state pins. + */ +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_CHILD_VARGS(DT_PROP_BY_IDX(node_id, prop, 0), \ + DT_FOREACH_PROP_ELEM, bflb_pins, \ + Z_PINCTRL_STATE_PIN_INIT)} + +/** @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_RISCV_BFLB_COMMON_PINCTRL_SOC_H_ */ diff --git a/soc/riscv/bouffalolab/common/soc_common.h b/soc/riscv/bouffalolab/common/soc_common.h new file mode 100644 index 0000000000000..67fb90beb845e --- /dev/null +++ b/soc/riscv/bouffalolab/common/soc_common.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2021 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file interrupt management code for riscv SOCs supporting the SiFive clic + */ + +#ifndef __SOC_COMMON_H_ +#define __SOC_COMMON_H_ + +/* IRQ numbers */ +#define RISCV_MACHINE_SOFT_IRQ 3 /* Machine Software Interrupt */ +#define RISCV_MACHINE_TIMER_IRQ 7 /* Machine Timer Interrupt */ +#define RISCV_MACHINE_EXT_IRQ 11 /* Machine External Interrupt */ + +/* ECALL Exception numbers */ +#define SOC_MCAUSE_ECALL_EXP 11 /* Machine ECALL instruction */ +#define SOC_MCAUSE_USER_ECALL_EXP 8 /* User ECALL instruction */ + +/* SOC-specific MCAUSE bitfields */ +#ifdef CONFIG_64BIT +/* Interrupt Mask */ +#define SOC_MCAUSE_IRQ_MASK (1 << 63) +/* Exception code Mask */ +#define SOC_MCAUSE_EXP_MASK 0x7FFFFFFFFFFFFFFF +#else +/* Interrupt Mask */ +#define SOC_MCAUSE_IRQ_MASK (1 << 31) +/* Exception code Mask */ +#define SOC_MCAUSE_EXP_MASK 0x7FFFFFFF +#endif + +/* SOC-Specific EXIT ISR command */ +#define SOC_ERET mret + +/* CLINT Base Address */ + +#define CLIC_TIMER_ENABLE_ADDRESS (0x02800407) + +/* In mstatus register */ + +#define SOC_MIE_MSIE (0x1 << 3) /* Machine Software Interrupt Enable */ + +/* IRQ 0-15 : (exception:interrupt=0) */ + +#define SOC_IRQ_IAMISALIGNED (0) /* Instruction Address Misaligned */ +#define SOC_IRQ_IAFAULT (1) /* Instruction Address Fault */ +#define SOC_IRQ_IINSTRUCTION (2) /* Illegal Instruction */ +#define SOC_IRQ_BPOINT (3) /* Break Point */ +#define SOC_IRQ_LAMISALIGNED (4) /* Load Address Misaligned */ +#define SOC_IRQ_LAFAULT (5) /* Load Access Fault */ +#define SOC_IRQ_SAMISALIGNED (6) /* Store/AMO Address Misaligned */ +#define SOC_IRQ_SAFAULT (7) /* Store/AMO Access Fault */ +#define SOC_IRQ_ECALLU (8) /* Environment Call from U-mode */ + /* 9-10: Reserved */ +#define SOC_IRQ_ECALLM (11) /* Environment Call from M-mode */ + /* 12-15: Reserved */ + /* IRQ 16- : (async event:interrupt=1) */ +#define SOC_IRQ_NUM_BASE (16) +#define SOC_IRQ_ASYNC (16) + +/* Machine Software Int */ +#define SOC_IRQ_MSOFT (SOC_IRQ_ASYNC + RISCV_MACHINE_SOFT_IRQ) +/* Machine Timer Int */ +#define SOC_IRQ_MTIMER (SOC_IRQ_ASYNC + RISCV_MACHINE_TIMER_IRQ) +/* Machine External Int */ +#define SOC_IRQ_MEXT (SOC_IRQ_ASYNC + RISCV_MACHINE_EXT_IRQ) + +/* Machine Global External Interrupt */ +#define SOC_NR_MGEI_IRQS (64) + +/* Total number of IRQs */ +#define SOC_NR_IRQS (SOC_NR_MGEI_IRQS + SOC_IRQ_NUM_BASE) + +#endif /* __SOC_COMMON_H_ */ diff --git a/soc/riscv/bouffalolab/common/soc_common_irq.c b/soc/riscv/bouffalolab/common/soc_common_irq.c new file mode 100644 index 0000000000000..53601cd0b625f --- /dev/null +++ b/soc/riscv/bouffalolab/common/soc_common_irq.c @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2021 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief interrupt management code for riscv SOCs supporting the SiFive clic + */ +#include +#include +#include + +static void clic_irq_enable(unsigned int irq) +{ + *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + irq) = 1; +} + +static void clic_irq_disable(unsigned int irq) +{ + *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + irq) = 0; +} + +void arch_irq_enable(unsigned int irq) +{ + uint32_t mie; + + if (irq == SOC_IRQ_MSOFT) { + + /* Read mstatus & set machine software interrupt enable in mie */ + + __asm__ volatile("csrrs %0, mie, %1" + : "=r"(mie) + : "r"(BIT(RISCV_MACHINE_SOFT_IRQ))); + + } else if (irq == SOC_IRQ_MTIMER) { + *(volatile uint8_t *)CLIC_TIMER_ENABLE_ADDRESS = 1; + + /* Read mstatus & set machine timer interrupt enable in mie */ + __asm__ volatile("csrrs %0, mie, %1" + : "=r"(mie) + : "r"(BIT(RISCV_MACHINE_TIMER_IRQ) + | BIT(RISCV_MACHINE_EXT_IRQ))); + } else { + clic_irq_enable(irq - SOC_IRQ_ASYNC); + } +} + +void arch_irq_disable(unsigned int irq) +{ + uint32_t mie; + + if (irq == SOC_IRQ_MSOFT) { + + /* Read mstatus & set machine software interrupt enable in mie */ + + __asm__ volatile("csrrc %0, mie, %1" + : "=r"(mie) + : "r"(BIT(RISCV_MACHINE_SOFT_IRQ))); + + } else if (irq == SOC_IRQ_MTIMER) { + *(volatile uint8_t *)CLIC_TIMER_ENABLE_ADDRESS = 0; + + /* Read mstatus & set machine timer interrupt enable in mie */ + __asm__ volatile("csrrc %0, mie, %1" + : "=r"(mie) + : "r"(BIT(RISCV_MACHINE_TIMER_IRQ) + | BIT(RISCV_MACHINE_EXT_IRQ))); + } else { + clic_irq_disable(irq - SOC_IRQ_ASYNC); + } +} + +void arch_irq_priority_set(unsigned int irq, unsigned int prio) +{ + ARG_UNUSED(irq); + ARG_UNUSED(prio); +} + +int arch_irq_is_enabled(unsigned int irq) +{ + uint32_t mie; + + /* Enable MEIE (machine external interrupt enable) */ + __asm__ volatile("csrrs %0, mie, %1" + : "=r"(mie) + : "r"(BIT(RISCV_MACHINE_EXT_IRQ))); + + /* Read mstatus & set machine interrupt enable (MIE) in mstatus */ + __asm__ volatile("csrrs %0, mstatus, %1" + : "=r"(mie) + : "r"(MSTATUS_MIE)); + + return !!(mie & SOC_MIE_MSIE); +} diff --git a/soc/riscv/bouffalolab/common/soc_irq.S b/soc/riscv/bouffalolab/common/soc_irq.S new file mode 100644 index 0000000000000..3a8904d043762 --- /dev/null +++ b/soc/riscv/bouffalolab/common/soc_irq.S @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2017 Jean-Paul Etienne + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * common interrupt management code for riscv SOCs supporting the riscv + * privileged architecture specification + */ +#include +#include +#include +#include +#include + +/* exports */ +GTEXT(__soc_handle_irq) + +/* + * SOC-specific function to handle pending IRQ number generating the interrupt. + * Exception number is given as parameter via register a0. + */ +SECTION_FUNC(exception.other, __soc_handle_irq) + /* Clear exception number from CSR mip register */ + li t1, 1 + sll t0, t1, a0 + csrrc t1, mip, t0 + + /* Return */ + jalr x0, ra + +/* + * __soc_is_irq is defined as .weak to allow re-implementation by + * SOCs that does not truly follow the riscv privilege specification. + */ +WTEXT(__soc_is_irq) + +/* + * SOC-specific function to determine if the exception is the result of a + * an interrupt or an exception + * return 1 (interrupt) or 0 (exception) + * + */ +SECTION_FUNC(exception.other, __soc_is_irq) + /* Read mcause and check if interrupt bit is set */ + csrr t0, mcause + li t1, SOC_MCAUSE_IRQ_MASK + and t0, t0, t1 + + /* If interrupt bit is not set, return with 0 */ + addi a0, x0, 0 + beqz t0, not_interrupt + addi a0, a0, 1 + +not_interrupt: + /* return */ + jalr x0, ra diff --git a/soc/riscv/bouffalolab/common/vector.S b/soc/riscv/bouffalolab/common/vector.S new file mode 100644 index 0000000000000..d6780f32b32f4 --- /dev/null +++ b/soc/riscv/bouffalolab/common/vector.S @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2021 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/* exports */ +GTEXT(__start) + +/* imports */ +GTEXT(__initialize) +GTEXT(__irq_wrapper) + +SECTION_FUNC(vectors, __start) + .cfi_startproc + + .option norvc + + /* Inform the debugger that there is nowhere to backtrace */ + .cfi_undefined ra + + /* Disable interrupts */ + li t0, MSTATUS_MIE + csrc mstatus, t0 + +#ifdef CONFIG_RISCV_GP + /* The absolute first thing that must happen is configuring the global + * pointer register, which must be done with relaxation disabled + * because it's not valid to obtain the address of any symbol without + * GP configured. The C environment might go ahead and do this again, + * but that's safe as it's a fixed register. */ + .option push + .option norelax + la gp, __global_pointer$ + .option pop +#endif + + /* + * Set mtvec (Machine Trap-Vector Base-Address Register) + * CLINT Direct mode + */ + la t0, __irq_wrapper + csrw mtvec, t0 + + /* Jump to __initialize */ + tail __initialize + + .cfi_endproc diff --git a/west.yml b/west.yml index d59033c9d85a8..d805c34f519cd 100644 --- a/west.yml +++ b/west.yml @@ -21,6 +21,8 @@ manifest: remotes: - name: upstream url-base: https://github.com/zephyrproject-rtos + - name: nandojve + url-base: https://github.com/nandojve # # Please add items below based on alphabetical order @@ -61,6 +63,12 @@ manifest: path: modules/hal/atmel groups: - hal + - name: bl_mcu_sdk + remote: nandojve + path: modules/hal/bouffalolab + revision: f33ca054e51fd77bc6768e70b9e06be230015b48 + groups: + - hal - name: hal_cypress revision: 81a059f21435bc7e315bccd720da5a9b615bbb50 path: modules/hal/cypress