diff --git a/boards/arm/nucleo_h743zi/doc/index.rst b/boards/arm/nucleo_h743zi/doc/index.rst index 9ca300600236a..90c051adbde48 100644 --- a/boards/arm/nucleo_h743zi/doc/index.rst +++ b/boards/arm/nucleo_h743zi/doc/index.rst @@ -111,6 +111,8 @@ features: +-----------+------------+-------------------------------------+ | PWM | on-chip | pwm | +-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. @@ -131,6 +133,7 @@ and a ST morpho connector. Board is configured as follows: - LD2 : PB7 - LD3 : PB14 - I2C : PB8, PB9 +- ADC12_INP15 : PA3 System Clock ------------ diff --git a/boards/arm/nucleo_h743zi/nucleo_h743zi.dts b/boards/arm/nucleo_h743zi/nucleo_h743zi.dts index 82c8ad550ceca..288255118bbde 100644 --- a/boards/arm/nucleo_h743zi/nucleo_h743zi.dts +++ b/boards/arm/nucleo_h743zi/nucleo_h743zi.dts @@ -77,3 +77,7 @@ status = "okay"; }; }; + +&adc1_2 { + status = "okay"; +}; diff --git a/boards/arm/nucleo_h743zi/nucleo_h743zi.yaml b/boards/arm/nucleo_h743zi/nucleo_h743zi.yaml index 6b27e938c6f39..164fa2d387df6 100644 --- a/boards/arm/nucleo_h743zi/nucleo_h743zi.yaml +++ b/boards/arm/nucleo_h743zi/nucleo_h743zi.yaml @@ -16,3 +16,4 @@ supported: - counter - i2c - pwm + - adc diff --git a/boards/arm/nucleo_h743zi/pinmux.c b/boards/arm/nucleo_h743zi/pinmux.c index 01604b98f5bd4..0c42209ecb463 100644 --- a/boards/arm/nucleo_h743zi/pinmux.c +++ b/boards/arm/nucleo_h743zi/pinmux.c @@ -23,7 +23,10 @@ static const struct pin_config pinconf[] = { { STM32_PIN_PB9, STM32H7_PINMUX_FUNC_PB9_I2C1_SDA }, #endif #if DT_HAS_NODE_STATUS_OKAY(DT_NODELABEL(pwm12)) - { STM32_PIN_PB14, STM32H7_PINMUX_FUNC_PB14_PWM12_CH1 } + { STM32_PIN_PB14, STM32H7_PINMUX_FUNC_PB14_PWM12_CH1 }, +#endif +#if DT_HAS_NODE_STATUS_OKAY(DT_NODELABEL(adc1_2)) + { STM32_PIN_PA3, STM32H7_PINMUX_FUNC_PA3_ADC12_INP15 }, #endif }; diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c index a262df7309c01..f2ce2b4f468d2 100644 --- a/drivers/adc/adc_stm32.c +++ b/drivers/adc/adc_stm32.c @@ -2,6 +2,7 @@ * Copyright (c) 2018 Kokoon Technology Limited * Copyright (c) 2019 Song Qiang * Copyright (c) 2019 Endre Karlson + * Copyright (c) 2020 Teslabs Engineering S.L. * * SPDX-License-Identifier: Apache-2.0 */ @@ -70,12 +71,20 @@ static const u32_t table_seq_len[] = { #define RES(n) LL_ADC_RESOLUTION_##n##B static const u32_t table_resolution[] = { -#if !defined(CONFIG_SOC_SERIES_STM32F1X) +#if defined(CONFIG_SOC_SERIES_STM32F1X) + RES(12), +#elif !defined(CONFIG_SOC_SERIES_STM32H7X) RES(6), RES(8), RES(10), -#endif RES(12), +#else + RES(8), + RES(10), + RES(12), + RES(14), + RES(16), +#endif }; #define SMP_TIME(x, y) LL_ADC_SAMPLINGTIME_##x##CYCLE##y @@ -175,10 +184,22 @@ static const u32_t table_samp_time[] = { SMP_TIME(192, S), SMP_TIME(384, S), }; +#elif defined(CONFIG_SOC_SERIES_STM32H7X) +static const u16_t acq_time_tbl[8] = {2, 3, 9, 17, 33, 65, 388, 811}; +static const u32_t table_samp_time[] = { + SMP_TIME(1, _5), + SMP_TIME(2, S_5), + SMP_TIME(8, S_5), + SMP_TIME(16, S_5), + SMP_TIME(32, S_5), + SMP_TIME(64, S_5), + SMP_TIME(387, S_5), + SMP_TIME(810, S_5), +}; #endif -/* 16 external channels. */ -#define STM32_CHANNEL_COUNT 16 +/* External channels (maximum). */ +#define STM32_CHANNEL_COUNT 20 struct adc_stm32_data { struct adc_context ctx; @@ -234,7 +255,8 @@ static void adc_stm32_start_conversion(struct device *dev) defined(CONFIG_SOC_SERIES_STM32L0X) || \ defined(CONFIG_SOC_SERIES_STM32L4X) || \ defined(CONFIG_SOC_SERIES_STM32WBX) || \ - defined(CONFIG_SOC_SERIES_STM32G4X) + defined(CONFIG_SOC_SERIES_STM32G4X) || \ + defined(CONFIG_SOC_SERIES_STM32H7X) LL_ADC_REG_StartConversion(adc); #else LL_ADC_REG_StartConversionSWStart(adc); @@ -250,7 +272,11 @@ static int start_read(struct device *dev, const struct adc_sequence *sequence) int err; switch (sequence->resolution) { -#if !defined(CONFIG_SOC_SERIES_STM32F1X) +#if defined(CONFIG_SOC_SERIES_STM32F1X) + case 12: + resolution = table_resolution[0]; + break; +#elif !defined(CONFIG_SOC_SERIES_STM32H7X) case 6: resolution = table_resolution[0]; break; @@ -264,9 +290,21 @@ static int start_read(struct device *dev, const struct adc_sequence *sequence) resolution = table_resolution[3]; break; #else - case 12: + case 8: resolution = table_resolution[0]; break; + case 10: + resolution = table_resolution[1]; + break; + case 12: + resolution = table_resolution[2]; + break; + case 14: + resolution = table_resolution[3]; + break; + case 16: + resolution = table_resolution[4]; + break; #endif default: LOG_ERR("Invalid resolution"); @@ -280,6 +318,15 @@ static int start_read(struct device *dev, const struct adc_sequence *sequence) index = find_lsb_set(channels) - 1; u32_t channel = __LL_ADC_DECIMAL_NB_TO_CHANNEL(index); +#if defined(CONFIG_SOC_SERIES_STM32H7X) + /* + * Each channel in the sequence must be previously enabled in PCSEL. + * This register controls the analog switch integrated in the IO level. + * NOTE: There is no LL API to control this register yet. + */ + adc->PCSEL |= channels & ADC_PCSEL_PCSEL_Msk; +#endif + #if defined(CONFIG_SOC_SERIES_STM32F0X) || \ defined(CONFIG_SOC_SERIES_STM32L0X) LL_ADC_REG_SetSequencerChannels(adc, channel); @@ -303,7 +350,8 @@ static int start_read(struct device *dev, const struct adc_sequence *sequence) defined(CONFIG_SOC_SERIES_STM32L0X) || \ defined(CONFIG_SOC_SERIES_STM32L4X) || \ defined(CONFIG_SOC_SERIES_STM32WBX) || \ - defined(CONFIG_SOC_SERIES_STM32G4X) + defined(CONFIG_SOC_SERIES_STM32G4X) || \ + defined(CONFIG_SOC_SERIES_STM32H7X) LL_ADC_EnableIT_EOC(adc); #elif defined(CONFIG_SOC_SERIES_STM32F1X) LL_ADC_EnableIT_EOS(adc); @@ -486,6 +534,8 @@ static void adc_stm32_calib(struct device *dev) #elif defined(CONFIG_SOC_SERIES_STM32F0X) || \ defined(CONFIG_SOC_SERIES_STM32L0X) LL_ADC_StartCalibration(adc); +#elif defined(CONFIG_SOC_SERIES_STM32H7X) + LL_ADC_StartCalibration(adc, LL_ADC_CALIB_OFFSET, LL_ADC_SINGLE_ENDED); #endif while (LL_ADC_IsCalibrationOnGoing(adc)) { } @@ -520,11 +570,12 @@ static int adc_stm32_init(struct device *dev) #if defined(CONFIG_SOC_SERIES_STM32L4X) || \ defined(CONFIG_SOC_SERIES_STM32WBX) || \ - defined(CONFIG_SOC_SERIES_STM32G4X) + defined(CONFIG_SOC_SERIES_STM32G4X) || \ + defined(CONFIG_SOC_SERIES_STM32H7X) /* - * L4, WB and G4 series STM32 needs to be awaken from deep sleep mode, - * and restore its calibration parameters if there are some previously - * stored calibration parameters. + * L4, WB, G4 and H7 series STM32 needs to be awaken from deep sleep + * mode, and restore its calibration parameters if there are some + * previously stored calibration parameters. */ LL_ADC_DisableDeepPowerDown(adc); #endif @@ -535,7 +586,8 @@ static int adc_stm32_init(struct device *dev) #if defined(CONFIG_SOC_SERIES_STM32F3X) || \ defined(CONFIG_SOC_SERIES_STM32L4X) || \ defined(CONFIG_SOC_SERIES_STM32WBX) || \ - defined(CONFIG_SOC_SERIES_STM32G4X) + defined(CONFIG_SOC_SERIES_STM32G4X) || \ + defined(CONFIG_SOC_SERIES_STM32H7X) LL_ADC_EnableInternalRegulator(adc); k_busy_wait(LL_ADC_DELAY_INTERNAL_REGUL_STAB_US); #endif @@ -546,9 +598,10 @@ static int adc_stm32_init(struct device *dev) #elif defined(CONFIG_SOC_SERIES_STM32F3X) || \ defined(CONFIG_SOC_SERIES_STM32L4X) || \ defined(CONFIG_SOC_SERIES_STM32WBX) || \ - defined(CONFIG_SOC_SERIES_STM32G4X) + defined(CONFIG_SOC_SERIES_STM32G4X) || \ + defined(CONFIG_SOC_SERIES_STM32H7X) LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(adc), - LL_ADC_CLOCK_SYNC_PCLK_DIV4); + LL_ADC_CLOCK_SYNC_PCLK_DIV4); #elif defined(CONFIG_SOC_SERIES_STM32L1X) LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(adc), LL_ADC_CLOCK_ASYNC_DIV4); @@ -570,17 +623,18 @@ static int adc_stm32_init(struct device *dev) defined(CONFIG_SOC_SERIES_STM32L0X) || \ defined(CONFIG_SOC_SERIES_STM32L4X) || \ defined(CONFIG_SOC_SERIES_STM32WBX) || \ - defined(CONFIG_SOC_SERIES_STM32G4X) + defined(CONFIG_SOC_SERIES_STM32G4X) || \ + defined(CONFIG_SOC_SERIES_STM32H7X) if (LL_ADC_IsActiveFlag_ADRDY(adc)) { LL_ADC_ClearFlag_ADRDY(adc); } /* - * These two series STM32 has one internal voltage reference source + * These STM32 series has one internal voltage reference source * to be enabled. */ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(adc), - LL_ADC_PATH_INTERNAL_VREFINT); + LL_ADC_PATH_INTERNAL_VREFINT); #endif #if defined(CONFIG_SOC_SERIES_STM32F0X) || \ @@ -588,7 +642,8 @@ static int adc_stm32_init(struct device *dev) defined(CONFIG_SOC_SERIES_STM32L0X) || \ defined(CONFIG_SOC_SERIES_STM32L4X) || \ defined(CONFIG_SOC_SERIES_STM32WBX) || \ - defined(CONFIG_SOC_SERIES_STM32G4X) + defined(CONFIG_SOC_SERIES_STM32G4X) || \ + defined(CONFIG_SOC_SERIES_STM32H7X) /* * ADC modules on these series have to wait for some cycles to be * enabled. @@ -611,7 +666,8 @@ static int adc_stm32_init(struct device *dev) #if defined(CONFIG_SOC_SERIES_STM32L4X) || \ defined(CONFIG_SOC_SERIES_STM32WBX) || \ - defined(CONFIG_SOC_SERIES_STM32G4X) + defined(CONFIG_SOC_SERIES_STM32G4X) || \ + defined(CONFIG_SOC_SERIES_STM32H7X) /* * Enabling ADC modules in L4, WB and G4 series may fail if they are * still not stabilized, this will wait for a short time to ensure ADC @@ -682,6 +738,4 @@ static void adc_stm32_cfg_func_##index(void) \ irq_enable(DT_INST_IRQN(index)); \ } -#if DT_HAS_DRV_INST(0) -STM32_ADC_INIT(0); -#endif /* DT_HAS_DRV_INST(0) */ +DT_INST_FOREACH(STM32_ADC_INIT) diff --git a/drivers/pinmux/stm32/pinmux_stm32h7.h b/drivers/pinmux/stm32/pinmux_stm32h7.h index 1917229b5082c..0e803b014dfe7 100644 --- a/drivers/pinmux/stm32/pinmux_stm32h7.h +++ b/drivers/pinmux/stm32/pinmux_stm32h7.h @@ -21,6 +21,12 @@ (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP) #define STM32H7_PINMUX_FUNC_PA0_UART4_TX \ (STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP) +#define STM32H7_PINMUX_FUNC_PA0_ADC1_INP16 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PA0_C_ADC12_INN1 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PA0_C_ADC12_INP0 \ + STM32_MODER_ANALOG_MODE #define STM32H7_PINMUX_FUNC_PA1_PWM2_CH2 \ (STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP) @@ -32,6 +38,12 @@ (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP) #define STM32H7_PINMUX_FUNC_PA1_UART4_RX \ (STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_NOPULL) +#define STM32H7_PINMUX_FUNC_PA1_ADC1_INN16 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PA1_ADC1_INP17 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PA1_C_ADC12_INP1 \ + STM32_MODER_ANALOG_MODE #define STM32H7_PINMUX_FUNC_PA2_PWM2_CH3 \ (STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP) @@ -41,7 +53,8 @@ (STM32_PINMUX_ALT_FUNC_4 | STM32_PUSHPULL_PULLUP) #define STM32H7_PINMUX_FUNC_PA2_USART2_TX \ (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP) - +#define STM32H7_PINMUX_FUNC_PA2_ADC12_INP14 \ + STM32_MODER_ANALOG_MODE #define STM32H7_PINMUX_FUNC_PA3_PWM2_CH4 \ (STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP) @@ -51,16 +64,27 @@ (STM32_PINMUX_ALT_FUNC_4 | STM32_PUSHPULL_PULLUP) #define STM32H7_PINMUX_FUNC_PA3_USART2_RX \ (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL) +#define STM32H7_PINMUX_FUNC_PA3_ADC12_INP15 \ + STM32_MODER_ANALOG_MODE + +#define STM32H7_PINMUX_FUNC_PA4_ADC12_INP18 \ + STM32_MODER_ANALOG_MODE #define STM32H7_PINMUX_FUNC_PA5_PWM2_CH1 \ (STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP) #define STM32H7_PINMUX_FUNC_PA5_PWM8_CH1N \ (STM32_PINMUX_ALT_FUNC_3 | STM32_PUSHPULL_PULLUP) +#define STM32H7_PINMUX_FUNC_PA5_ADC12_INN18 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PA5_ADC12_INP19 \ + STM32_MODER_ANALOG_MODE #define STM32H7_PINMUX_FUNC_PA6_PWM3_CH1 \ (STM32_PINMUX_ALT_FUNC_2 | STM32_PUSHPULL_PULLUP) #define STM32H7_PINMUX_FUNC_PA6_PWM13_CH1 \ (STM32_PINMUX_ALT_FUNC_9 | STM32_PUSHPULL_PULLUP) +#define STM32H7_PINMUX_FUNC_PA6_ADC12_INP3 \ + STM32_MODER_ANALOG_MODE #define STM32H7_PINMUX_FUNC_PA7_PWM1_CH1N \ (STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP) @@ -70,6 +94,10 @@ (STM32_PINMUX_ALT_FUNC_3 | STM32_PUSHPULL_PULLUP) #define STM32H7_PINMUX_FUNC_PA7_PWM14_CH1 \ (STM32_PINMUX_ALT_FUNC_9 | STM32_PUSHPULL_PULLUP) +#define STM32H7_PINMUX_FUNC_PA7_ADC12_INN3 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PA7_ADC12_INP7 \ + STM32_MODER_ANALOG_MODE #define STM32H7_PINMUX_FUNC_PA8_PWM1_CH1 \ (STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP) @@ -112,6 +140,10 @@ (STM32_PINMUX_ALT_FUNC_2 | STM32_PUSHPULL_PULLUP) #define STM32H7_PINMUX_FUNC_PB0_PWM8_CH2N \ (STM32_PINMUX_ALT_FUNC_3 | STM32_PUSHPULL_PULLUP) +#define STM32H7_PINMUX_FUNC_PB0_ADC12_INN5 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PB0_ADC12_INP9 \ + STM32_MODER_ANALOG_MODE #define STM32H7_PINMUX_FUNC_PB1_PWM1_CH3N \ (STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP) @@ -119,6 +151,8 @@ (STM32_PINMUX_ALT_FUNC_2 | STM32_PUSHPULL_PULLUP) #define STM32H7_PINMUX_FUNC_PB1_PWM8_CH3N \ (STM32_PINMUX_ALT_FUNC_3 | STM32_PUSHPULL_PULLUP) +#define STM32H7_PINMUX_FUNC_PB1_ADC12_INP5 \ + STM32_MODER_ANALOG_MODE #define STM32H7_PINMUX_FUNC_PB3_PWM2_CH2 \ (STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP) @@ -211,6 +245,38 @@ (STM32_PINMUX_ALT_FUNC_3 | STM32_PUSHPULL_PULLUP) /* Port C */ +#define STM32H7_PINMUX_FUNC_PC0_ADC123_INP10 \ + STM32_MODER_ANALOG_MODE + +#define STM32H7_PINMUX_FUNC_PC1_ADC123_INN10 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PC1_ADC123_INP11 \ + STM32_MODER_ANALOG_MODE + +#define STM32H7_PINMUX_FUNC_PC2_ADC123_INN11 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PC2_ADC123_INP12 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PC2_C_ADC3_INN1 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PC2_C_ADC3_INP0 \ + STM32_MODER_ANALOG_MODE + +#define STM32H7_PINMUX_FUNC_PC3_ADC12_INN12 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PC3_ADC12_INP13 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PC3_C_ADC3_INP1 \ + STM32_MODER_ANALOG_MODE + +#define STM32H7_PINMUX_FUNC_PC4_ADC12_INP4 \ + STM32_MODER_ANALOG_MODE + +#define STM32H7_PINMUX_FUNC_PC5_ADC12_INN4 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PC5_ADC12_INP8 \ + STM32_MODER_ANALOG_MODE + #define STM32H7_PINMUX_FUNC_PC6_PWM3_CH1 \ (STM32_PINMUX_ALT_FUNC_2 | STM32_PUSHPULL_PULLUP) #define STM32H7_PINMUX_FUNC_PC6_PWM8_CH1 \ @@ -354,15 +420,32 @@ #define STM32H7_PINMUX_FUNC_PF1_I2C2_SCL \ (STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP) +#define STM32H7_PINMUX_FUNC_PF3_ADC3_INP5 \ + STM32_MODER_ANALOG_MODE + +#define STM32H7_PINMUX_FUNC_PF4_ADC3_INN5 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PF4_ADC3_INP9 \ + STM32_MODER_ANALOG_MODE + +#define STM32H7_PINMUX_FUNC_PF5_ADC3_INP4 \ + STM32_MODER_ANALOG_MODE + #define STM32H7_PINMUX_FUNC_PF6_PWM16_CH1 \ (STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP) #define STM32H7_PINMUX_FUNC_PF6_UART7_RX \ (STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_NOPULL) +#define STM32H7_PINMUX_FUNC_PF6_ADC3_INN4 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PF6_ADC3_INP8 \ + STM32_MODER_ANALOG_MODE #define STM32H7_PINMUX_FUNC_PF7_PWM17_CH1 \ (STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP) #define STM32H7_PINMUX_FUNC_PF7_UART7_TX \ (STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP) +#define STM32H7_PINMUX_FUNC_PF7_ADC3_INP3 \ + STM32_MODER_ANALOG_MODE #define STM32H7_PINMUX_FUNC_PF8_PWM16_CH1N \ (STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP) @@ -370,6 +453,10 @@ (STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP) #define STM32H7_PINMUX_FUNC_PF8_PWM13_CH1 \ (STM32_PINMUX_ALT_FUNC_9 | STM32_PUSHPULL_PULLUP) +#define STM32H7_PINMUX_FUNC_PF8_ADC3_INN3 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PF8_ADC3_INP7 \ + STM32_MODER_ANALOG_MODE #define STM32H7_PINMUX_FUNC_PF9_PWM17_CH1N \ (STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP) @@ -377,9 +464,31 @@ (STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP) #define STM32H7_PINMUX_FUNC_PF9_PWM14_CH1 \ (STM32_PINMUX_ALT_FUNC_9 | STM32_PUSHPULL_PULLUP) +#define STM32H7_PINMUX_FUNC_PF9_ADC3_INP2 \ + STM32_MODER_ANALOG_MODE + +#define STM32H7_PINMUX_FUNC_PF10_ADC3_INN2 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PF10_ADC3_INP6 \ + STM32_MODER_ANALOG_MODE + +#define STM32H7_PINMUX_FUNC_PF11_ADC1_INP2 \ + STM32_MODER_ANALOG_MODE + +#define STM32H7_PINMUX_FUNC_PF12_ADC1_INN2 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PF12_ADC1_INP6 \ + STM32_MODER_ANALOG_MODE + +#define STM32H7_PINMUX_FUNC_PF13_ADC1_INP2 \ + STM32_MODER_ANALOG_MODE #define STM32H7_PINMUX_FUNC_PF14_I2C4_SCL \ (STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP) +#define STM32H7_PINMUX_FUNC_PF14_ADC2_INN2 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PF14_ADC2_INP6 \ + STM32_MODER_ANALOG_MODE #define STM32H7_PINMUX_FUNC_PF15_I2C4_SDA \ (STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP) @@ -404,11 +513,24 @@ (STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP) /* Port H */ +#define STM32H7_PINMUX_FUNC_PH3_ADC3_INN13 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PH3_ADC3_INP14 \ + STM32_MODER_ANALOG_MODE + #define STM32H7_PINMUX_FUNC_PH4_I2C2_SCL \ (STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP) +#define STM32H7_PINMUX_FUNC_PH4_ADC3_INN14 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PH4_ADC3_INP15 \ + STM32_MODER_ANALOG_MODE #define STM32H7_PINMUX_FUNC_PH5_I2C2_SDA \ (STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP) +#define STM32H7_PINMUX_FUNC_PH5_ADC3_INN15 \ + STM32_MODER_ANALOG_MODE +#define STM32H7_PINMUX_FUNC_PH5_ADC3_INP16 \ + STM32_MODER_ANALOG_MODE #define STM32H7_PINMUX_FUNC_PH6_PWM12_CH1 \ (STM32_PINMUX_ALT_FUNC_2 | STM32_PUSHPULL_PULLUP) diff --git a/dts/arm/st/h7/stm32h7.dtsi b/dts/arm/st/h7/stm32h7.dtsi index d8b79245a998d..66f74f5b7510c 100644 --- a/dts/arm/st/h7/stm32h7.dtsi +++ b/dts/arm/st/h7/stm32h7.dtsi @@ -546,6 +546,26 @@ #pwm-cells = <2>; }; }; + + adc1_2: adc@40022000 { + compatible = "st,stm32-adc"; + reg = <0x40022000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>; + interrupts = <18 0>; + status = "disabled"; + label = "ADC_1_2"; + #io-channel-cells = <1>; + }; + + adc3: adc@58026000 { + compatible = "st,stm32-adc"; + reg = <0x58026000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x01000000>; + interrupts = <127 0>; + status = "disabled"; + label = "ADC_3"; + #io-channel-cells = <1>; + }; }; }; diff --git a/soc/arm/st_stm32/stm32h7/soc.h b/soc/arm/st_stm32/stm32h7/soc.h index 8174de72b541b..7c90dbe1479ff 100644 --- a/soc/arm/st_stm32/stm32h7/soc.h +++ b/soc/arm/st_stm32/stm32h7/soc.h @@ -74,6 +74,10 @@ #include #endif /* CONFIG_I2C_STM32 */ +#ifdef CONFIG_ADC_STM32 +#include +#endif /* CONFIG_ADC_STM32 */ + #endif /* !_ASMLANGUAGE */ #endif /* _STM32F7_SOC_H7_ */ diff --git a/tests/drivers/adc/adc_api/src/test_adc.c b/tests/drivers/adc/adc_api/src/test_adc.c index 9e87dd52ed098..dffe338398475 100644 --- a/tests/drivers/adc/adc_api/src/test_adc.c +++ b/tests/drivers/adc/adc_api/src/test_adc.c @@ -168,6 +168,14 @@ #define ADC_ACQUISITION_TIME ADC_ACQ_TIME_DEFAULT #define ADC_1ST_CHANNEL_ID 1 +#elif defined(CONFIG_BOARD_NUCLEO_H743ZI) +#define ADC_DEVICE_NAME DT_LABEL(DT_INST(0, st_stm32_adc)) +#define ADC_RESOLUTION 16 +#define ADC_GAIN ADC_GAIN_1 +#define ADC_REFERENCE ADC_REF_INTERNAL +#define ADC_ACQUISITION_TIME ADC_ACQ_TIME_DEFAULT +#define ADC_1ST_CHANNEL_ID 0 + #elif defined(CONFIG_BOARD_TWR_KE18F) #define ADC_DEVICE_NAME DT_LABEL(DT_INST(0, nxp_kinetis_adc12)) #define ADC_RESOLUTION 12