From 3d8a45cdfb7f64d487fa0ad04ef8601e7565a6a8 Mon Sep 17 00:00:00 2001 From: Piotr Mienkowski Date: Sat, 12 Oct 2019 00:35:09 +0200 Subject: [PATCH 01/17] CODEOWNERS: Add entry for gpio drivers Adding code owners of gpio drivers. Signed-off-by: Piotr Mienkowski --- CODEOWNERS | 1 + 1 file changed, 1 insertion(+) diff --git a/CODEOWNERS b/CODEOWNERS index d359bbd17572f..692b58f182c6c 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -131,6 +131,7 @@ /drivers/flash/*nrf* @nvlsianpu /drivers/flash/*spi_nor* @pabigot /drivers/flash/*stm32* @superna9999 +/drivers/gpio/ @mnkp @pabigot /drivers/gpio/*ht16k33* @henrikbrixandersen /drivers/gpio/*stm32* @rsalveti @idlethread /drivers/hwinfo/ @alexanderwachter From f1276fead5a5b7b02c610ce749c0206fb18162c9 Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Mon, 7 Oct 2019 10:49:17 +0200 Subject: [PATCH 02/17] drivers/gpio: stm32: Rework configure function exit for dual core With dual core handling introduction, we now need to take care to always release lock before exiting function. Rework gpio_stm32_config to take this into account. Additionally, since ENOSYS usage is resevred to system calls handling, replace with EIO. Signed-off-by: Erwan Gouriou --- drivers/gpio/gpio_stm32.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/gpio/gpio_stm32.c b/drivers/gpio/gpio_stm32.c index 94676d687e2be..d292092b36a42 100644 --- a/drivers/gpio/gpio_stm32.c +++ b/drivers/gpio/gpio_stm32.c @@ -260,6 +260,7 @@ static int gpio_stm32_config(struct device *dev, int access_op, u32_t pin, int flags) { const struct gpio_stm32_config *cfg = dev->config->config_info; + int err = 0; int pincfg; int map_res; @@ -282,18 +283,21 @@ static int gpio_stm32_config(struct device *dev, int access_op, */ map_res = gpio_stm32_flags_to_conf(flags, &pincfg); if (map_res != 0) { - return map_res; + err = map_res; + goto release_lock; } if (gpio_stm32_configure(cfg->base, pin, pincfg, 0) != 0) { - return -EIO; + err = -EIO; + goto release_lock; } if (IS_ENABLED(CONFIG_EXTI_STM32) && (flags & GPIO_INT) != 0) { if (stm32_exti_set_callback(pin, cfg->port, gpio_stm32_isr, dev) != 0) { - return -EBUSY; + err = -EBUSY; + goto release_lock; } gpio_stm32_enable_int(cfg->port, pin); @@ -313,20 +317,23 @@ static int gpio_stm32_config(struct device *dev, int access_op, stm32_exti_trigger(pin, edge); } else { /* Level trigger interrupts not supported */ - return -ENOTSUP; + err = -ENOTSUP; + goto release_lock; } if (stm32_exti_enable(pin) != 0) { - return -ENOSYS; + err = -EIO; + goto release_lock; } } +release_lock: #if defined(CONFIG_STM32H7_DUAL_CORE) LL_HSEM_ReleaseLock(HSEM, LL_HSEM_ID_1, 0); #endif /* CONFIG_STM32H7_DUAL_CORE */ - return 0; + return err; } /** From 9d6ba14e9dee6f7bd31556838aa67b48c9cacb98 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Wed, 18 Sep 2019 18:38:35 +0200 Subject: [PATCH 03/17] gpio: stm32: statify gpio_stm32_enable_int() This allows compiler to inline function body and reduce overall code size. Signed-off-by: Marcin Niestroj --- drivers/gpio/gpio_stm32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio_stm32.c b/drivers/gpio/gpio_stm32.c index d292092b36a42..57335775d1385 100644 --- a/drivers/gpio/gpio_stm32.c +++ b/drivers/gpio/gpio_stm32.c @@ -188,7 +188,7 @@ int gpio_stm32_configure(u32_t *base_addr, int pin, int conf, int altf) /** * @brief Enable EXTI of the specific line */ -const int gpio_stm32_enable_int(int port, int pin) +static int gpio_stm32_enable_int(int port, int pin) { #if defined(CONFIG_SOC_SERIES_STM32F2X) || \ defined(CONFIG_SOC_SERIES_STM32F3X) || \ From 84d75595b3d94db922555bd5cc5844086d34387e Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Wed, 18 Sep 2019 17:44:47 +0200 Subject: [PATCH 04/17] gpio: stm32: split helper functions from gpio_stm32_enable_int() This patch doesn't change functionality, but is only related to improved readability and reusability. Signed-off-by: Marcin Niestroj --- drivers/gpio/gpio_stm32.c | 74 ++++++++++++++++++++++----------------- 1 file changed, 41 insertions(+), 33 deletions(-) diff --git a/drivers/gpio/gpio_stm32.c b/drivers/gpio/gpio_stm32.c index 57335775d1385..3d60bea7b58c1 100644 --- a/drivers/gpio/gpio_stm32.c +++ b/drivers/gpio/gpio_stm32.c @@ -185,6 +185,46 @@ int gpio_stm32_configure(u32_t *base_addr, int pin, int conf, int altf) return 0; } +static inline uint32_t gpio_stm32_pin_to_exti_line(int pin) +{ +#if defined(CONFIG_SOC_SERIES_STM32L0X) || \ + defined(CONFIG_SOC_SERIES_STM32F0X) + return ((pin % 4 * 4) << 16) | (pin / 4); +#elif defined(CONFIG_SOC_SERIES_STM32MP1X) + return (((pin * 8) % 32) << 16) | (pin / 4); +#elif defined(CONFIG_SOC_SERIES_STM32G0X) + return ((pin & 0x3) << (16 + 3)) | (pin >> 2); +#else + return (0xF << ((pin % 4 * 4) + 16)) | (pin / 4); +#endif +} + +static void gpio_stm32_set_exti_source(int port, int pin) +{ + uint32_t line = gpio_stm32_pin_to_exti_line(pin); + +#if defined(CONFIG_SOC_SERIES_STM32L0X) && defined(LL_SYSCFG_EXTI_PORTH) + /* + * Ports F and G are not present on some STM32L0 parts, so + * for these parts port H external interrupt should be enabled + * by writing value 0x5 instead of 0x7. + */ + if (port == STM32_PORTH) { + port = LL_SYSCFG_EXTI_PORTH; + } +#endif + +#ifdef CONFIG_SOC_SERIES_STM32F1X + LL_GPIO_AF_SetEXTISource(port, line); +#elif CONFIG_SOC_SERIES_STM32MP1X + LL_EXTI_SetEXTISource(port, line); +#elif defined(CONFIG_SOC_SERIES_STM32G0X) + LL_EXTI_SetEXTISource(port, line); +#else + LL_SYSCFG_SetEXTISource(port, line); +#endif +} + /** * @brief Enable EXTI of the specific line */ @@ -212,43 +252,11 @@ static int gpio_stm32_enable_int(int port, int pin) clock_control_on(clk, (clock_control_subsys_t *) &pclken); #endif - uint32_t line; - if (pin > 15) { return -EINVAL; } -#if defined(CONFIG_SOC_SERIES_STM32L0X) || \ - defined(CONFIG_SOC_SERIES_STM32F0X) - line = ((pin % 4 * 4) << 16) | (pin / 4); -#elif defined(CONFIG_SOC_SERIES_STM32MP1X) - line = (((pin * 8) % 32) << 16) | (pin / 4); -#elif defined(CONFIG_SOC_SERIES_STM32G0X) - line = ((pin & 0x3) << (16 + 3)) | (pin >> 2); -#else - line = (0xF << ((pin % 4 * 4) + 16)) | (pin / 4); -#endif - -#if defined(CONFIG_SOC_SERIES_STM32L0X) && defined(LL_SYSCFG_EXTI_PORTH) - /* - * Ports F and G are not present on some STM32L0 parts, so - * for these parts port H external interrupt should be enabled - * by writing value 0x5 instead of 0x7. - */ - if (port == STM32_PORTH) { - port = LL_SYSCFG_EXTI_PORTH; - } -#endif - -#ifdef CONFIG_SOC_SERIES_STM32F1X - LL_GPIO_AF_SetEXTISource(port, line); -#elif CONFIG_SOC_SERIES_STM32MP1X - LL_EXTI_SetEXTISource(port, line); -#elif defined(CONFIG_SOC_SERIES_STM32G0X) - LL_EXTI_SetEXTISource(port, line); -#else - LL_SYSCFG_SetEXTISource(port, line); -#endif + gpio_stm32_set_exti_source(port, pin); return 0; } From 7f26a2a2a5a4fbe5e48bf039aa72c7c935cc11de Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Wed, 18 Sep 2019 23:38:02 +0200 Subject: [PATCH 05/17] gpio: stm32: support disabling and reenabling interrupts on gpio pin Up to now interrupts could be only configured once, with no way to disable them in runtime. Allow interrupts to be disabled in runtime and then properly reenabled on user request. This allows to ignore interrupts when software is not expecting them. The improvement over previously reverted patch [1] is that we disable interrupts only when we configure port for which interrupt line was previously selected. This for example prevents to disable interrupts line 2 in case PA2 was previously configured as interrupt source, but we are currently configuring PB2 as output. [1] 0951ce2d34b6 ("gpio: stm32: support disabling and reenabling interrupts on pin") Signed-off-by: Marcin Niestroj --- drivers/gpio/gpio_stm32.c | 52 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 50 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio_stm32.c b/drivers/gpio/gpio_stm32.c index 3d60bea7b58c1..24a65bda45a07 100644 --- a/drivers/gpio/gpio_stm32.c +++ b/drivers/gpio/gpio_stm32.c @@ -225,6 +225,35 @@ static void gpio_stm32_set_exti_source(int port, int pin) #endif } +static int gpio_stm32_get_exti_source(int pin) +{ + uint32_t line = gpio_stm32_pin_to_exti_line(pin); + int port; + +#ifdef CONFIG_SOC_SERIES_STM32F1X + port = LL_GPIO_AF_GetEXTISource(line); +#elif CONFIG_SOC_SERIES_STM32MP1X + port = LL_EXTI_GetEXTISource(line); +#elif defined(CONFIG_SOC_SERIES_STM32G0X) + port = LL_EXTI_GetEXTISource(line); +#else + port = LL_SYSCFG_GetEXTISource(line); +#endif + +#if defined(CONFIG_SOC_SERIES_STM32L0X) && defined(LL_SYSCFG_EXTI_PORTH) + /* + * Ports F and G are not present on some STM32L0 parts, so + * for these parts port H external interrupt is enabled + * by writing value 0x5 instead of 0x7. + */ + if (port == LL_SYSCFG_EXTI_PORTH) { + port = STM32_PORTH; + } +#endif + + return port; +} + /** * @brief Enable EXTI of the specific line */ @@ -261,6 +290,18 @@ static int gpio_stm32_enable_int(int port, int pin) return 0; } +/** + * @brief Get enabled GPIO port for EXTI of the specific pin number + */ +static int gpio_stm32_int_enabled_port(int pin) +{ + if (pin > 15) { + return -EINVAL; + } + + return gpio_stm32_get_exti_source(pin); +} + /** * @brief Configure pin or port */ @@ -300,8 +341,11 @@ static int gpio_stm32_config(struct device *dev, int access_op, goto release_lock; } - if (IS_ENABLED(CONFIG_EXTI_STM32) && (flags & GPIO_INT) != 0) { + if (!IS_ENABLED(CONFIG_EXTI_STM32)) { + goto release_lock; + } + if (flags & GPIO_INT) { if (stm32_exti_set_callback(pin, cfg->port, gpio_stm32_isr, dev) != 0) { err = -EBUSY; @@ -333,7 +377,11 @@ static int gpio_stm32_config(struct device *dev, int access_op, err = -EIO; goto release_lock; } - + } else { + if (gpio_stm32_int_enabled_port(pin) == cfg->port) { + stm32_exti_disable(pin); + stm32_exti_unset_callback(pin); + } } release_lock: From 86dcd394e1877ed9b948fccf8b0d65d0b881f4fb Mon Sep 17 00:00:00 2001 From: Stanislav Poboril Date: Thu, 3 Oct 2019 10:48:18 +0200 Subject: [PATCH 06/17] dts: nxp_imx6sx_m4: fix gpio5 int num Fix interrupt number for gpio5 Signed-off-by: Stanislav Poboril --- dts/arm/nxp/nxp_imx6sx_m4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/arm/nxp/nxp_imx6sx_m4.dtsi b/dts/arm/nxp/nxp_imx6sx_m4.dtsi index b40e35bb1e3e7..f6c124660156d 100644 --- a/dts/arm/nxp/nxp_imx6sx_m4.dtsi +++ b/dts/arm/nxp/nxp_imx6sx_m4.dtsi @@ -201,7 +201,7 @@ gpio5:gpio@420ac000 { compatible = "nxp,imx-gpio"; reg = <0x420ac000 0x4000>; - interrupts = <74 0>, <74 0>; + interrupts = <74 0>, <75 0>; rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ RDC_DOMAIN_PERM_RW)|\ RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ From d8f6e9813acbb264f2938873e28a3423a93151f3 Mon Sep 17 00:00:00 2001 From: Andrei Gansari Date: Tue, 4 Jun 2019 09:03:13 +0300 Subject: [PATCH 07/17] dts: NXP LPC gpio updates NXP's LPC family of MCU's GPIOs parameters is udated. Boards LPC54xxx and LPC55xxx have updated values according pin and interrupt layout. Signed-off-by: Andrei Gansari --- dts/arm/nxp/nxp_lpc54xxx.dtsi | 4 ++-- dts/arm/nxp/nxp_lpc55S6x.dtsi | 28 ++++++++++++++++++++++------ dts/bindings/gpio/nxp,lpc-gpio.yaml | 25 +++++++++++++++++++++++++ 3 files changed, 49 insertions(+), 8 deletions(-) create mode 100644 dts/bindings/gpio/nxp,lpc-gpio.yaml diff --git a/dts/arm/nxp/nxp_lpc54xxx.dtsi b/dts/arm/nxp/nxp_lpc54xxx.dtsi index 31dad79df35a9..6f584e87c4cf5 100644 --- a/dts/arm/nxp/nxp_lpc54xxx.dtsi +++ b/dts/arm/nxp/nxp_lpc54xxx.dtsi @@ -58,7 +58,7 @@ }; gpio0: gpio@0 { - compatible = "nxp,kinetis-gpio"; + compatible = "nxp,lpc-gpio"; reg = <0x4008c000 0x2488>; interrupts = <2 2>; label = "GPIO_0"; @@ -67,7 +67,7 @@ }; gpio1: gpio@1 { - compatible = "nxp,kinetis-gpio"; + compatible = "nxp,lpc-gpio"; reg = <0x4008C000 0x2488>; interrupts = <3 2>; label = "GPIO_1"; diff --git a/dts/arm/nxp/nxp_lpc55S6x.dtsi b/dts/arm/nxp/nxp_lpc55S6x.dtsi index 094dc26a2fda8..1cf5e7d6a2237 100644 --- a/dts/arm/nxp/nxp_lpc55S6x.dtsi +++ b/dts/arm/nxp/nxp_lpc55S6x.dtsi @@ -63,23 +63,39 @@ status = "disabled"; }; - gpio0: gpio@0 { - compatible = "nxp,kinetis-gpio"; + gpio0:gpio@0 { + compatible = "nxp,lpc-gpio"; reg = <0x5008c000 0x2488>; - interrupts = <2 2>; + interrupts = <4 2>; label = "GPIO_0"; gpio-controller; #gpio-cells = <2>; }; - gpio1: gpio@1 { - compatible = "nxp,kinetis-gpio"; + gpio1:gpio@1 { + compatible = "nxp,lpc-gpio"; reg = <0x5008c000 0x2488>; - interrupts = <3 2>; + interrupts = <5 2>,<6 2>; label = "GPIO_1"; gpio-controller; #gpio-cells = <2>; }; + + gpio2:gpio@2 { + compatible = "nxp,lpc-gpio"; + reg = <0x5008c000 0x2488>; + label = "GPIO_2"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio3:gpio@3 { + compatible = "nxp,lpc-gpio"; + reg = <0x5008c000 0x2488>; + label = "GPIO_3"; + gpio-controller; + #gpio-cells = <2>; + }; }; }; diff --git a/dts/bindings/gpio/nxp,lpc-gpio.yaml b/dts/bindings/gpio/nxp,lpc-gpio.yaml new file mode 100644 index 0000000000000..8ae2c49c0c255 --- /dev/null +++ b/dts/bindings/gpio/nxp,lpc-gpio.yaml @@ -0,0 +1,25 @@ +# Copyright (c) 2019, NXP +# SPDX-License-Identifier: Apache-2.0 + +title: LPC GPIO + +description: | + This is a representation of the LPC GPIO nodes + +compatible: "nxp,lpc-gpio" + +include: [gpio-controller.yaml, base.yaml] + +properties: + reg: + required: true + + label: + required: true + + "#gpio-cells": + const: 2 + +gpio-cells: + - pin + - flags From 2796c31e4a269d505c8349b6059642d222498976 Mon Sep 17 00:00:00 2001 From: Andrei Gansari Date: Wed, 9 Oct 2019 15:31:03 +0300 Subject: [PATCH 08/17] dts: lpc devices allocate all gpio interrupts Allocate all 8 PINT interrupts to ports 0 and 1, allocate 4 to each. Signed-off-by: Andrei Gansari --- dts/arm/nxp/nxp_lpc54xxx.dtsi | 4 ++-- dts/arm/nxp/nxp_lpc55S6x.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/dts/arm/nxp/nxp_lpc54xxx.dtsi b/dts/arm/nxp/nxp_lpc54xxx.dtsi index 6f584e87c4cf5..e12c316d0c62e 100644 --- a/dts/arm/nxp/nxp_lpc54xxx.dtsi +++ b/dts/arm/nxp/nxp_lpc54xxx.dtsi @@ -60,7 +60,7 @@ gpio0: gpio@0 { compatible = "nxp,lpc-gpio"; reg = <0x4008c000 0x2488>; - interrupts = <2 2>; + interrupts = <4 2>,<5 2>,<6 2>,<7 2>; label = "GPIO_0"; gpio-controller; #gpio-cells = <2>; @@ -69,7 +69,7 @@ gpio1: gpio@1 { compatible = "nxp,lpc-gpio"; reg = <0x4008C000 0x2488>; - interrupts = <3 2>; + interrupts = <32 2>,<33 2>,<34 2>,<35 2>; label = "GPIO_1"; gpio-controller; #gpio-cells = <2>; diff --git a/dts/arm/nxp/nxp_lpc55S6x.dtsi b/dts/arm/nxp/nxp_lpc55S6x.dtsi index 1cf5e7d6a2237..a8f7b732e1207 100644 --- a/dts/arm/nxp/nxp_lpc55S6x.dtsi +++ b/dts/arm/nxp/nxp_lpc55S6x.dtsi @@ -66,7 +66,7 @@ gpio0:gpio@0 { compatible = "nxp,lpc-gpio"; reg = <0x5008c000 0x2488>; - interrupts = <4 2>; + interrupts = <4 2>,<5 2>,<6 2>,<7 2>; label = "GPIO_0"; gpio-controller; #gpio-cells = <2>; @@ -75,7 +75,7 @@ gpio1:gpio@1 { compatible = "nxp,lpc-gpio"; reg = <0x5008c000 0x2488>; - interrupts = <5 2>,<6 2>; + interrupts = <32 2>,<33 2>,<34 2>,<35 2>; label = "GPIO_1"; gpio-controller; #gpio-cells = <2>; From 908fc98a35ed3605ce6b42f76d804422115f94d4 Mon Sep 17 00:00:00 2001 From: Andrei Gansari Date: Tue, 28 May 2019 16:24:10 +0300 Subject: [PATCH 09/17] boards: lpcxpresso55s69 pinmux macros refactor Board is refactored to use DTS generated value, not use magic numbers. Signed-off-by: Andrei Gansari --- boards/arm/lpcxpresso55s69/pinmux.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/boards/arm/lpcxpresso55s69/pinmux.c b/boards/arm/lpcxpresso55s69/pinmux.c index fd24f1f476805..73a23df14bc44 100644 --- a/boards/arm/lpcxpresso55s69/pinmux.c +++ b/boards/arm/lpcxpresso55s69/pinmux.c @@ -48,8 +48,8 @@ static int lpcxpresso_55s69_pinmux_init(struct device *dev) #endif -#ifdef CONFIG_GPIO_MCUX_LPC_PORT0 - const u32_t port0_pin5_config = ( +#ifdef DT_GPIO_KEYS_SW0_GPIO_CONTROLLER + const u32_t sw0_config = ( IOCON_PIO_FUNC0 | IOCON_PIO_MODE_PULLUP | IOCON_PIO_INV_DI | @@ -58,12 +58,11 @@ static int lpcxpresso_55s69_pinmux_init(struct device *dev) IOCON_PIO_SLEW_STANDARD | IOCON_PIO_OPENDRAIN_DI ); - - pinmux_pin_set(port0, 5, port0_pin5_config); + pinmux_pin_set(port0, DT_ALIAS_SW0_GPIOS_PIN, sw0_config); #endif -#ifdef CONFIG_GPIO_MCUX_LPC_PORT0 - const u32_t port1_pin18_config = ( +#ifdef DT_GPIO_KEYS_SW1_GPIO_CONTROLLER + const u32_t sw1_config = ( IOCON_PIO_FUNC0 | IOCON_PIO_MODE_PULLUP | IOCON_PIO_INV_DI | @@ -72,10 +71,11 @@ static int lpcxpresso_55s69_pinmux_init(struct device *dev) IOCON_PIO_SLEW_STANDARD | IOCON_PIO_OPENDRAIN_DI ); + pinmux_pin_set(port1, DT_ALIAS_SW0_GPIOS_PIN, sw1_config); +#endif - pinmux_pin_set(port1, 18, port1_pin18_config); - - const u32_t port1_pin9_config = ( +#ifdef DT_GPIO_KEYS_SW2_GPIO_CONTROLLER + const u32_t sw2_config = ( IOCON_PIO_FUNC0 | IOCON_PIO_MODE_PULLUP | IOCON_PIO_INV_DI | @@ -84,8 +84,7 @@ static int lpcxpresso_55s69_pinmux_init(struct device *dev) IOCON_PIO_SLEW_STANDARD | IOCON_PIO_OPENDRAIN_DI ); - - pinmux_pin_set(port1, 9, port1_pin9_config); + pinmux_pin_set(port1, DT_ALIAS_SW0_GPIOS_PIN, sw2_config); #endif return 0; From 3247fb6ca12a5fb603a6563d0c910bbada831caa Mon Sep 17 00:00:00 2001 From: Andrei Gansari Date: Thu, 8 Aug 2019 14:17:29 +0300 Subject: [PATCH 10/17] soc: enable PINT device at LPC SoC boot PINT device is enabled when SoC is booting up. Applies to LPC54xxx and LPC55xxx families. Signed-off-by: Andrei Gansari --- soc/arm/nxp_lpc/lpc54xxx/soc.c | 6 ++++++ soc/arm/nxp_lpc/lpc55xxx/soc.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/soc/arm/nxp_lpc/lpc54xxx/soc.c b/soc/arm/nxp_lpc/lpc54xxx/soc.c index 869a85f9ef5b5..a9273d7769d91 100644 --- a/soc/arm/nxp_lpc/lpc54xxx/soc.c +++ b/soc/arm/nxp_lpc/lpc54xxx/soc.c @@ -24,6 +24,7 @@ #include #include #include +#include /** * @@ -90,6 +91,11 @@ static int nxp_lpc54114_init(struct device *arg) /* Initialize FRO/system clock to 48 MHz */ clock_init(); +#ifdef CONFIG_GPIO_MCUX_LPC + /* Turn on PINT device*/ + PINT_Init(PINT); +#endif + /* * install default handler that simply resets the CPU if configured in * the kernel, NOP otherwise diff --git a/soc/arm/nxp_lpc/lpc55xxx/soc.c b/soc/arm/nxp_lpc/lpc55xxx/soc.c index 8a7eb674f7651..47c5f43085158 100644 --- a/soc/arm/nxp_lpc/lpc55xxx/soc.c +++ b/soc/arm/nxp_lpc/lpc55xxx/soc.c @@ -24,6 +24,7 @@ #include #include #include +#include /** * @@ -87,6 +88,11 @@ static int nxp_lpc55s69_init(struct device *arg) /* Initialize FRO/system clock to 48 MHz */ clock_init(); +#ifdef CONFIG_GPIO_MCUX_LPC + /* Turn on PINT device*/ + PINT_Init(PINT); +#endif + /* * install default handler that simply resets the CPU if configured in * the kernel, NOP otherwise From 7d9109968c1f0b6052b00804268af0a610fb488a Mon Sep 17 00:00:00 2001 From: Andrei Gansari Date: Wed, 9 Oct 2019 14:52:07 +0300 Subject: [PATCH 11/17] soc: LPC55xxx clock comment fix SoC initialization had an incorrect comment regarding system clock. Corrected from 48Mhz -> 96Mhz. Signed-off-by: Andrei Gansari --- soc/arm/nxp_lpc/lpc55xxx/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/arm/nxp_lpc/lpc55xxx/soc.c b/soc/arm/nxp_lpc/lpc55xxx/soc.c index 47c5f43085158..29e25342185d8 100644 --- a/soc/arm/nxp_lpc/lpc55xxx/soc.c +++ b/soc/arm/nxp_lpc/lpc55xxx/soc.c @@ -85,7 +85,7 @@ static int nxp_lpc55s69_init(struct device *arg) z_arm_clear_faults(); - /* Initialize FRO/system clock to 48 MHz */ + /* Initialize FRO/system clock to 96 MHz */ clock_init(); #ifdef CONFIG_GPIO_MCUX_LPC From 0f93dad172159512ef448aaf867505c651f5ec9b Mon Sep 17 00:00:00 2001 From: Andrei Gansari Date: Wed, 9 Oct 2019 15:28:11 +0300 Subject: [PATCH 12/17] soc: define gpio pull-down for LPC54114 Add define that maps to IOCON register PULL-DOWN bit. Signed-off-by: Andrei Gansari --- soc/arm/nxp_lpc/lpc54xxx/soc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/soc/arm/nxp_lpc/lpc54xxx/soc.h b/soc/arm/nxp_lpc/lpc54xxx/soc.h index 91d7dd0744ed3..3372c51ab1057 100644 --- a/soc/arm/nxp_lpc/lpc54xxx/soc.h +++ b/soc/arm/nxp_lpc/lpc54xxx/soc.h @@ -34,5 +34,6 @@ #define IOCON_PIO_OPENDRAIN_DI 0x00u #define IOCON_PIO_SLEW_STANDARD 0x00u #define IOCON_PIO_MODE_PULLUP 0x10u +#define IOCON_PIO_MODE_PULLDOWN 0x08u #endif /* _SOC__H_ */ From a30fa3d280ef7b7bfffe0e3f8bad617ac32dcb68 Mon Sep 17 00:00:00 2001 From: Christian Taedcke Date: Mon, 28 Oct 2019 10:54:35 +0100 Subject: [PATCH 13/17] gpio: silabs gecko: Use macro for port initialization This removes a lot of copy-and-paste. Signed-off-by: Christian Taedcke --- drivers/gpio/gpio_gecko.c | 148 ++++++++------------------------------ 1 file changed, 28 insertions(+), 120 deletions(-) diff --git a/drivers/gpio/gpio_gecko.c b/drivers/gpio/gpio_gecko.c index e3e97ddfba518..db84524f25579 100644 --- a/drivers/gpio/gpio_gecko.c +++ b/drivers/gpio/gpio_gecko.c @@ -315,141 +315,49 @@ static int gpio_gecko_common_init(struct device *dev) } #endif /* CONFIG_GPIO_GECKO */ +#define GPIO_PORT_INIT(pl, pu) \ +static int gpio_gecko_port##pl##_init(struct device *dev); \ +\ +static const struct gpio_gecko_config gpio_gecko_port##pl##_config = { \ + .gpio_base = &GPIO->P[gpioPort##pu], \ + .gpio_index = gpioPort##pu, \ +}; \ +\ +static struct gpio_gecko_data gpio_gecko_port##pl##_data; \ +\ +DEVICE_AND_API_INIT(gpio_gecko_port##pl, DT_GPIO_GECKO_PORT##pu##_NAME, \ + gpio_gecko_port##pl##_init, \ + &gpio_gecko_port##pl##_data, \ + &gpio_gecko_port##pl##_config, \ + POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \ + &gpio_gecko_driver_api); \ +\ +static int gpio_gecko_port##pl##_init(struct device *dev) \ +{ \ + gpio_gecko_add_port(&gpio_gecko_common_data, dev); \ + return 0; \ +} #ifdef CONFIG_GPIO_GECKO_PORTA -static int gpio_gecko_porta_init(struct device *dev); - -static const struct gpio_gecko_config gpio_gecko_porta_config = { - .gpio_base = &GPIO->P[gpioPortA], - .gpio_index = gpioPortA, -}; - -static struct gpio_gecko_data gpio_gecko_porta_data; - -DEVICE_AND_API_INIT(gpio_gecko_porta, DT_GPIO_GECKO_PORTA_NAME, - gpio_gecko_porta_init, - &gpio_gecko_porta_data, &gpio_gecko_porta_config, - POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, - &gpio_gecko_driver_api); - -static int gpio_gecko_porta_init(struct device *dev) -{ - gpio_gecko_add_port(&gpio_gecko_common_data, dev); - return 0; -} +GPIO_PORT_INIT(a, A) #endif /* CONFIG_GPIO_GECKO_PORTA */ #ifdef CONFIG_GPIO_GECKO_PORTB -static int gpio_gecko_portb_init(struct device *dev); - -static const struct gpio_gecko_config gpio_gecko_portb_config = { - .gpio_base = &GPIO->P[gpioPortB], - .gpio_index = gpioPortB, -}; - -static struct gpio_gecko_data gpio_gecko_portb_data; - -DEVICE_AND_API_INIT(gpio_gecko_portb, DT_GPIO_GECKO_PORTB_NAME, - gpio_gecko_portb_init, - &gpio_gecko_portb_data, &gpio_gecko_portb_config, - POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, - &gpio_gecko_driver_api); - -static int gpio_gecko_portb_init(struct device *dev) -{ - gpio_gecko_add_port(&gpio_gecko_common_data, dev); - return 0; -} +GPIO_PORT_INIT(b, B) #endif /* CONFIG_GPIO_GECKO_PORTB */ #ifdef CONFIG_GPIO_GECKO_PORTC -static int gpio_gecko_portc_init(struct device *dev); - -static const struct gpio_gecko_config gpio_gecko_portc_config = { - .gpio_base = &GPIO->P[gpioPortC], - .gpio_index = gpioPortC, -}; - -static struct gpio_gecko_data gpio_gecko_portc_data; - -DEVICE_AND_API_INIT(gpio_gecko_portc, DT_GPIO_GECKO_PORTC_NAME, - gpio_gecko_portc_init, - &gpio_gecko_portc_data, &gpio_gecko_portc_config, - POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, - &gpio_gecko_driver_api); - -static int gpio_gecko_portc_init(struct device *dev) -{ - gpio_gecko_add_port(&gpio_gecko_common_data, dev); - return 0; -} +GPIO_PORT_INIT(c, C) #endif /* CONFIG_GPIO_GECKO_PORTC */ #ifdef CONFIG_GPIO_GECKO_PORTD -static int gpio_gecko_portd_init(struct device *dev); - -static const struct gpio_gecko_config gpio_gecko_portd_config = { - .gpio_base = &GPIO->P[gpioPortD], - .gpio_index = gpioPortD, -}; - -static struct gpio_gecko_data gpio_gecko_portd_data; - -DEVICE_AND_API_INIT(gpio_gecko_portd, DT_GPIO_GECKO_PORTD_NAME, - gpio_gecko_portd_init, - &gpio_gecko_portd_data, &gpio_gecko_portd_config, - POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, - &gpio_gecko_driver_api); - -static int gpio_gecko_portd_init(struct device *dev) -{ - gpio_gecko_add_port(&gpio_gecko_common_data, dev); - return 0; -} +GPIO_PORT_INIT(d, D) #endif /* CONFIG_GPIO_GECKO_PORTD */ #ifdef CONFIG_GPIO_GECKO_PORTE -static int gpio_gecko_porte_init(struct device *dev); - -static const struct gpio_gecko_config gpio_gecko_porte_config = { - .gpio_base = &GPIO->P[gpioPortE], - .gpio_index = gpioPortE, -}; - -static struct gpio_gecko_data gpio_gecko_porte_data; - -DEVICE_AND_API_INIT(gpio_gecko_porte, DT_GPIO_GECKO_PORTE_NAME, - gpio_gecko_porte_init, - &gpio_gecko_porte_data, &gpio_gecko_porte_config, - POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, - &gpio_gecko_driver_api); - -static int gpio_gecko_porte_init(struct device *dev) -{ - gpio_gecko_add_port(&gpio_gecko_common_data, dev); - return 0; -} +GPIO_PORT_INIT(e, E) #endif /* CONFIG_GPIO_GECKO_PORTE */ #ifdef CONFIG_GPIO_GECKO_PORTF -static int gpio_gecko_portf_init(struct device *dev); - -static const struct gpio_gecko_config gpio_gecko_portf_config = { - .gpio_base = &GPIO->P[gpioPortF], - .gpio_index = gpioPortF, -}; - -static struct gpio_gecko_data gpio_gecko_portf_data; - -DEVICE_AND_API_INIT(gpio_gecko_portf, DT_GPIO_GECKO_PORTF_NAME, - gpio_gecko_portf_init, - &gpio_gecko_portf_data, &gpio_gecko_portf_config, - POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, - &gpio_gecko_driver_api); - -static int gpio_gecko_portf_init(struct device *dev) -{ - gpio_gecko_add_port(&gpio_gecko_common_data, dev); - return 0; -} +GPIO_PORT_INIT(f, F) #endif /* CONFIG_GPIO_GECKO_PORTF */ From 32f137060fb8c3bc267ef10975c4db2518609286 Mon Sep 17 00:00:00 2001 From: Christian Taedcke Date: Mon, 28 Oct 2019 10:59:22 +0100 Subject: [PATCH 14/17] gpio: silabs gecko: Add support for more ports The gecko gpio driver can now utilize ports a to k. Signed-off-by: Christian Taedcke --- drivers/gpio/Kconfig.gecko | 25 +++++++++++++++++++++++++ drivers/gpio/gpio_gecko.c | 20 ++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/drivers/gpio/Kconfig.gecko b/drivers/gpio/Kconfig.gecko index b339625eb57d8..4751f53c428f8 100644 --- a/drivers/gpio/Kconfig.gecko +++ b/drivers/gpio/Kconfig.gecko @@ -47,4 +47,29 @@ config GPIO_GECKO_PORTF help Enable Port F. +config GPIO_GECKO_PORTG + bool "Port G" + help + Enable Port G. + +config GPIO_GECKO_PORTH + bool "Port H" + help + Enable Port H. + +config GPIO_GECKO_PORTI + bool "Port I" + help + Enable Port I. + +config GPIO_GECKO_PORTJ + bool "Port J" + help + Enable Port J. + +config GPIO_GECKO_PORTK + bool "Port K" + help + Enable Port K. + endif # GPIO_GECKO diff --git a/drivers/gpio/gpio_gecko.c b/drivers/gpio/gpio_gecko.c index db84524f25579..6e209f4c33cb2 100644 --- a/drivers/gpio/gpio_gecko.c +++ b/drivers/gpio/gpio_gecko.c @@ -361,3 +361,23 @@ GPIO_PORT_INIT(e, E) #ifdef CONFIG_GPIO_GECKO_PORTF GPIO_PORT_INIT(f, F) #endif /* CONFIG_GPIO_GECKO_PORTF */ + +#ifdef CONFIG_GPIO_GECKO_PORTG +GPIO_PORT_INIT(g, G) +#endif /* CONFIG_GPIO_GECKO_PORTG */ + +#ifdef CONFIG_GPIO_GECKO_PORTH +GPIO_PORT_INIT(h, H) +#endif /* CONFIG_GPIO_GECKO_PORTH */ + +#ifdef CONFIG_GPIO_GECKO_PORTI +GPIO_PORT_INIT(i, I) +#endif /* CONFIG_GPIO_GECKO_PORTI */ + +#ifdef CONFIG_GPIO_GECKO_PORTJ +GPIO_PORT_INIT(j, J) +#endif /* CONFIG_GPIO_GECKO_PORTJ */ + +#ifdef CONFIG_GPIO_GECKO_PORTK +GPIO_PORT_INIT(k, K) +#endif /* CONFIG_GPIO_GECKO_PORTK */ From 517f3b9e591bae600ad979bc32898e70e283b8c2 Mon Sep 17 00:00:00 2001 From: Christian Taedcke Date: Mon, 28 Oct 2019 11:36:29 +0100 Subject: [PATCH 15/17] dts: silabs: Define all available gpio ports for efr32mg12p Add device tree elements for all gpio ports of the efr32mg12p including the dts fixup entries. Also remove gpio port e since this is not available in efr32mg12p socs. Signed-off-by: Christian Taedcke --- dts/arm/silabs/efr32mg.dtsi | 28 ++++++++++++++++----- soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h | 4 ++- 2 files changed, 25 insertions(+), 7 deletions(-) diff --git a/dts/arm/silabs/efr32mg.dtsi b/dts/arm/silabs/efr32mg.dtsi index bfce45146825a..7824e91b814b6 100644 --- a/dts/arm/silabs/efr32mg.dtsi +++ b/dts/arm/silabs/efr32mg.dtsi @@ -162,18 +162,34 @@ #gpio-cells = <2>; }; - gpioe: gpio@4000a0c0 { + gpiof: gpio@4000a0f0 { compatible = "silabs,efr32mg-gpio-port"; - reg = <0x4000a0c0 0x30>; - label = "GPIO_E"; + reg = <0x4000a0f0 0x30>; + label = "GPIO_F"; gpio-controller; #gpio-cells = <2>; }; - gpiof: gpio@4000a0f0 { + gpioi: gpio@4000a180 { compatible = "silabs,efr32mg-gpio-port"; - reg = <0x4000a0f0 0x30>; - label = "GPIO_F"; + reg = <0x4000a180 0x30>; + label = "GPIO_I"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioj: gpio@4000a1b0 { + compatible = "silabs,efr32mg-gpio-port"; + reg = <0x4000a1b0 0x30>; + label = "GPIO_J"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpiok: gpio@4000a1e0 { + compatible = "silabs,efr32mg-gpio-port"; + reg = <0x4000a1e0 0x30>; + label = "GPIO_K"; gpio-controller; #gpio-cells = <2>; }; diff --git a/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h b/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h index 8ff92e043782c..235521996f47d 100644 --- a/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h +++ b/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h @@ -25,7 +25,9 @@ #define DT_GPIO_GECKO_PORTB_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A030_LABEL #define DT_GPIO_GECKO_PORTC_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A060_LABEL #define DT_GPIO_GECKO_PORTD_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A090_LABEL -#define DT_GPIO_GECKO_PORTE_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A0C0_LABEL #define DT_GPIO_GECKO_PORTF_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A0F0_LABEL +#define DT_GPIO_GECKO_PORTI_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A180_LABEL +#define DT_GPIO_GECKO_PORTJ_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A1B0_LABEL +#define DT_GPIO_GECKO_PORTK_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A1E0_LABEL /* End of SoC Level DTS fixup file */ From 2f1a0c8ae9b850e10edbd241fed68ee283efb9cb Mon Sep 17 00:00:00 2001 From: Peter Bigot Date: Tue, 29 Oct 2019 11:47:48 -0500 Subject: [PATCH 16/17] boards: mark gpio as supported capability where known missing Some board description files failed to note where gpio was supported, causing tests to be inappropriately filtered. Add the feature where the gpio_basic_api test would use it. Signed-off-by: Peter Bigot --- boards/arm/atsamd21_xpro/atsamd21_xpro.yaml | 2 ++ boards/arm/mimxrt1060_evk/mimxrt1060_evk.yaml | 1 + 2 files changed, 3 insertions(+) diff --git a/boards/arm/atsamd21_xpro/atsamd21_xpro.yaml b/boards/arm/atsamd21_xpro/atsamd21_xpro.yaml index 2e805eac02626..d3f0b982255d1 100644 --- a/boards/arm/atsamd21_xpro/atsamd21_xpro.yaml +++ b/boards/arm/atsamd21_xpro/atsamd21_xpro.yaml @@ -10,3 +10,5 @@ toolchain: - zephyr - gnuarmemb - xtools +supported: + - gpio diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.yaml b/boards/arm/mimxrt1060_evk/mimxrt1060_evk.yaml index c03c84f75b61b..12567885b869b 100644 --- a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.yaml +++ b/boards/arm/mimxrt1060_evk/mimxrt1060_evk.yaml @@ -16,6 +16,7 @@ ram: 32768 flash: 8192 supported: - display + - gpio - hwinfo - i2c - netif:eth From 29e4afba922b6ce5ce054d7881644d2733ae9de9 Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Mon, 7 Oct 2019 14:56:41 -0500 Subject: [PATCH 17/17] boards: rv32m1_vega: Configure led pinmuxes as gpios Explicitly configures the rgb led pinmuxes as gpios. Currently the gpio driver quietly changes the pinmux to gpio mode when configuring a gpio pin, but this behavior is about to change. Signed-off-by: Maureen Helm --- boards/riscv/rv32m1_vega/pinmux.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/boards/riscv/rv32m1_vega/pinmux.c b/boards/riscv/rv32m1_vega/pinmux.c index 5fc6a8070be00..79cad65bf1c7f 100644 --- a/boards/riscv/rv32m1_vega/pinmux.c +++ b/boards/riscv/rv32m1_vega/pinmux.c @@ -69,6 +69,11 @@ static int rv32m1_vega_pinmux_init(struct device *dev) pinmux_pin_set(porte, 22, PORT_PCR_MUX(kPORT_MuxAsGpio)); pinmux_pin_set(porte, 27, PORT_PCR_MUX(kPORT_MuxAsGpio)); + /* RGB LEDs */ + pinmux_pin_set(porta, 22, PORT_PCR_MUX(kPORT_MuxAsGpio)); + pinmux_pin_set(porta, 23, PORT_PCR_MUX(kPORT_MuxAsGpio)); + pinmux_pin_set(porta, 24, PORT_PCR_MUX(kPORT_MuxAsGpio)); + #if CONFIG_SPI_1 /* LPSPI1 SCK, SIN, SOUT, CS */ pinmux_pin_set(portb, 20, PORT_PCR_MUX(kPORT_MuxAlt2));