diff --git a/CODEOWNERS b/CODEOWNERS
index d359bbd17572f..692b58f182c6c 100644
--- a/CODEOWNERS
+++ b/CODEOWNERS
@@ -131,6 +131,7 @@
 /drivers/flash/*nrf*                      @nvlsianpu
 /drivers/flash/*spi_nor*                  @pabigot
 /drivers/flash/*stm32*                    @superna9999
+/drivers/gpio/                            @mnkp @pabigot
 /drivers/gpio/*ht16k33*                   @henrikbrixandersen
 /drivers/gpio/*stm32*                     @rsalveti @idlethread
 /drivers/hwinfo/                          @alexanderwachter
diff --git a/boards/arm/atsamd21_xpro/atsamd21_xpro.yaml b/boards/arm/atsamd21_xpro/atsamd21_xpro.yaml
index 2e805eac02626..d3f0b982255d1 100644
--- a/boards/arm/atsamd21_xpro/atsamd21_xpro.yaml
+++ b/boards/arm/atsamd21_xpro/atsamd21_xpro.yaml
@@ -10,3 +10,5 @@ toolchain:
   - zephyr
   - gnuarmemb
   - xtools
+supported:
+  - gpio
diff --git a/boards/arm/lpcxpresso55s69/pinmux.c b/boards/arm/lpcxpresso55s69/pinmux.c
index fd24f1f476805..73a23df14bc44 100644
--- a/boards/arm/lpcxpresso55s69/pinmux.c
+++ b/boards/arm/lpcxpresso55s69/pinmux.c
@@ -48,8 +48,8 @@ static int lpcxpresso_55s69_pinmux_init(struct device *dev)
 
 #endif
 
-#ifdef CONFIG_GPIO_MCUX_LPC_PORT0
-	const u32_t port0_pin5_config = (
+#ifdef DT_GPIO_KEYS_SW0_GPIO_CONTROLLER
+	const u32_t sw0_config = (
 			IOCON_PIO_FUNC0 |
 			IOCON_PIO_MODE_PULLUP |
 			IOCON_PIO_INV_DI |
@@ -58,12 +58,11 @@ static int lpcxpresso_55s69_pinmux_init(struct device *dev)
 			IOCON_PIO_SLEW_STANDARD |
 			IOCON_PIO_OPENDRAIN_DI
 			);
-
-	pinmux_pin_set(port0, 5, port0_pin5_config);
+	pinmux_pin_set(port0, DT_ALIAS_SW0_GPIOS_PIN, sw0_config);
 #endif
 
-#ifdef CONFIG_GPIO_MCUX_LPC_PORT0
-	const u32_t port1_pin18_config = (
+#ifdef DT_GPIO_KEYS_SW1_GPIO_CONTROLLER
+	const u32_t sw1_config = (
 			IOCON_PIO_FUNC0 |
 			IOCON_PIO_MODE_PULLUP |
 			IOCON_PIO_INV_DI |
@@ -72,10 +71,11 @@ static int lpcxpresso_55s69_pinmux_init(struct device *dev)
 			IOCON_PIO_SLEW_STANDARD |
 			IOCON_PIO_OPENDRAIN_DI
 			);
+	pinmux_pin_set(port1, DT_ALIAS_SW0_GPIOS_PIN, sw1_config);
+#endif
 
-	pinmux_pin_set(port1, 18, port1_pin18_config);
-
-	const u32_t port1_pin9_config = (
+#ifdef DT_GPIO_KEYS_SW2_GPIO_CONTROLLER
+	const u32_t sw2_config = (
 			IOCON_PIO_FUNC0 |
 			IOCON_PIO_MODE_PULLUP |
 			IOCON_PIO_INV_DI |
@@ -84,8 +84,7 @@ static int lpcxpresso_55s69_pinmux_init(struct device *dev)
 			IOCON_PIO_SLEW_STANDARD |
 			IOCON_PIO_OPENDRAIN_DI
 			);
-
-	pinmux_pin_set(port1, 9, port1_pin9_config);
+	pinmux_pin_set(port1, DT_ALIAS_SW0_GPIOS_PIN, sw2_config);
 #endif
 
 	return 0;
diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.yaml b/boards/arm/mimxrt1060_evk/mimxrt1060_evk.yaml
index c03c84f75b61b..12567885b869b 100644
--- a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.yaml
+++ b/boards/arm/mimxrt1060_evk/mimxrt1060_evk.yaml
@@ -16,6 +16,7 @@ ram: 32768
 flash: 8192
 supported:
   - display
+  - gpio
   - hwinfo
   - i2c
   - netif:eth
diff --git a/boards/riscv/rv32m1_vega/pinmux.c b/boards/riscv/rv32m1_vega/pinmux.c
index 5fc6a8070be00..79cad65bf1c7f 100644
--- a/boards/riscv/rv32m1_vega/pinmux.c
+++ b/boards/riscv/rv32m1_vega/pinmux.c
@@ -69,6 +69,11 @@ static int rv32m1_vega_pinmux_init(struct device *dev)
 	pinmux_pin_set(porte, 22, PORT_PCR_MUX(kPORT_MuxAsGpio));
 	pinmux_pin_set(porte, 27, PORT_PCR_MUX(kPORT_MuxAsGpio));
 
+	/* RGB LEDs */
+	pinmux_pin_set(porta, 22, PORT_PCR_MUX(kPORT_MuxAsGpio));
+	pinmux_pin_set(porta, 23, PORT_PCR_MUX(kPORT_MuxAsGpio));
+	pinmux_pin_set(porta, 24, PORT_PCR_MUX(kPORT_MuxAsGpio));
+
 #if CONFIG_SPI_1
 	/* LPSPI1 SCK, SIN, SOUT, CS */
 	pinmux_pin_set(portb, 20, PORT_PCR_MUX(kPORT_MuxAlt2));
diff --git a/drivers/gpio/Kconfig.gecko b/drivers/gpio/Kconfig.gecko
index b339625eb57d8..4751f53c428f8 100644
--- a/drivers/gpio/Kconfig.gecko
+++ b/drivers/gpio/Kconfig.gecko
@@ -47,4 +47,29 @@ config GPIO_GECKO_PORTF
 	help
 	  Enable Port F.
 
+config GPIO_GECKO_PORTG
+	bool "Port G"
+	help
+	  Enable Port G.
+
+config GPIO_GECKO_PORTH
+	bool "Port H"
+	help
+	  Enable Port H.
+
+config GPIO_GECKO_PORTI
+	bool "Port I"
+	help
+	  Enable Port I.
+
+config GPIO_GECKO_PORTJ
+	bool "Port J"
+	help
+	  Enable Port J.
+
+config GPIO_GECKO_PORTK
+	bool "Port K"
+	help
+	  Enable Port K.
+
 endif # GPIO_GECKO
diff --git a/drivers/gpio/gpio_gecko.c b/drivers/gpio/gpio_gecko.c
index e3e97ddfba518..6e209f4c33cb2 100644
--- a/drivers/gpio/gpio_gecko.c
+++ b/drivers/gpio/gpio_gecko.c
@@ -315,141 +315,69 @@ static int gpio_gecko_common_init(struct device *dev)
 }
 #endif /* CONFIG_GPIO_GECKO */
 
+#define GPIO_PORT_INIT(pl, pu) \
+static int gpio_gecko_port##pl##_init(struct device *dev); \
+\
+static const struct gpio_gecko_config gpio_gecko_port##pl##_config = { \
+	.gpio_base = &GPIO->P[gpioPort##pu], \
+	.gpio_index = gpioPort##pu, \
+}; \
+\
+static struct gpio_gecko_data gpio_gecko_port##pl##_data; \
+\
+DEVICE_AND_API_INIT(gpio_gecko_port##pl, DT_GPIO_GECKO_PORT##pu##_NAME, \
+		    gpio_gecko_port##pl##_init, \
+		    &gpio_gecko_port##pl##_data, \
+		    &gpio_gecko_port##pl##_config, \
+		    POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
+		    &gpio_gecko_driver_api); \
+\
+static int gpio_gecko_port##pl##_init(struct device *dev) \
+{ \
+	gpio_gecko_add_port(&gpio_gecko_common_data, dev); \
+	return 0; \
+}
 
 #ifdef CONFIG_GPIO_GECKO_PORTA
-static int gpio_gecko_porta_init(struct device *dev);
-
-static const struct gpio_gecko_config gpio_gecko_porta_config = {
-	.gpio_base = &GPIO->P[gpioPortA],
-	.gpio_index = gpioPortA,
-};
-
-static struct gpio_gecko_data gpio_gecko_porta_data;
-
-DEVICE_AND_API_INIT(gpio_gecko_porta, DT_GPIO_GECKO_PORTA_NAME,
-		    gpio_gecko_porta_init,
-		    &gpio_gecko_porta_data, &gpio_gecko_porta_config,
-		    POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
-		    &gpio_gecko_driver_api);
-
-static int gpio_gecko_porta_init(struct device *dev)
-{
-	gpio_gecko_add_port(&gpio_gecko_common_data, dev);
-	return 0;
-}
+GPIO_PORT_INIT(a, A)
 #endif /* CONFIG_GPIO_GECKO_PORTA */
 
 #ifdef CONFIG_GPIO_GECKO_PORTB
-static int gpio_gecko_portb_init(struct device *dev);
-
-static const struct gpio_gecko_config gpio_gecko_portb_config = {
-	.gpio_base = &GPIO->P[gpioPortB],
-	.gpio_index = gpioPortB,
-};
-
-static struct gpio_gecko_data gpio_gecko_portb_data;
-
-DEVICE_AND_API_INIT(gpio_gecko_portb, DT_GPIO_GECKO_PORTB_NAME,
-		    gpio_gecko_portb_init,
-		    &gpio_gecko_portb_data, &gpio_gecko_portb_config,
-		    POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
-		    &gpio_gecko_driver_api);
-
-static int gpio_gecko_portb_init(struct device *dev)
-{
-	gpio_gecko_add_port(&gpio_gecko_common_data, dev);
-	return 0;
-}
+GPIO_PORT_INIT(b, B)
 #endif /* CONFIG_GPIO_GECKO_PORTB */
 
 #ifdef CONFIG_GPIO_GECKO_PORTC
-static int gpio_gecko_portc_init(struct device *dev);
-
-static const struct gpio_gecko_config gpio_gecko_portc_config = {
-	.gpio_base = &GPIO->P[gpioPortC],
-	.gpio_index = gpioPortC,
-};
-
-static struct gpio_gecko_data gpio_gecko_portc_data;
-
-DEVICE_AND_API_INIT(gpio_gecko_portc, DT_GPIO_GECKO_PORTC_NAME,
-		    gpio_gecko_portc_init,
-		    &gpio_gecko_portc_data, &gpio_gecko_portc_config,
-		    POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
-		    &gpio_gecko_driver_api);
-
-static int gpio_gecko_portc_init(struct device *dev)
-{
-	gpio_gecko_add_port(&gpio_gecko_common_data, dev);
-	return 0;
-}
+GPIO_PORT_INIT(c, C)
 #endif /* CONFIG_GPIO_GECKO_PORTC */
 
 #ifdef CONFIG_GPIO_GECKO_PORTD
-static int gpio_gecko_portd_init(struct device *dev);
-
-static const struct gpio_gecko_config gpio_gecko_portd_config = {
-	.gpio_base = &GPIO->P[gpioPortD],
-	.gpio_index = gpioPortD,
-};
-
-static struct gpio_gecko_data gpio_gecko_portd_data;
-
-DEVICE_AND_API_INIT(gpio_gecko_portd, DT_GPIO_GECKO_PORTD_NAME,
-		    gpio_gecko_portd_init,
-		    &gpio_gecko_portd_data, &gpio_gecko_portd_config,
-		    POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
-		    &gpio_gecko_driver_api);
-
-static int gpio_gecko_portd_init(struct device *dev)
-{
-	gpio_gecko_add_port(&gpio_gecko_common_data, dev);
-	return 0;
-}
+GPIO_PORT_INIT(d, D)
 #endif /* CONFIG_GPIO_GECKO_PORTD */
 
 #ifdef CONFIG_GPIO_GECKO_PORTE
-static int gpio_gecko_porte_init(struct device *dev);
-
-static const struct gpio_gecko_config gpio_gecko_porte_config = {
-	.gpio_base = &GPIO->P[gpioPortE],
-	.gpio_index = gpioPortE,
-};
-
-static struct gpio_gecko_data gpio_gecko_porte_data;
-
-DEVICE_AND_API_INIT(gpio_gecko_porte, DT_GPIO_GECKO_PORTE_NAME,
-		    gpio_gecko_porte_init,
-		    &gpio_gecko_porte_data, &gpio_gecko_porte_config,
-		    POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
-		    &gpio_gecko_driver_api);
-
-static int gpio_gecko_porte_init(struct device *dev)
-{
-	gpio_gecko_add_port(&gpio_gecko_common_data, dev);
-	return 0;
-}
+GPIO_PORT_INIT(e, E)
 #endif /* CONFIG_GPIO_GECKO_PORTE */
 
 #ifdef CONFIG_GPIO_GECKO_PORTF
-static int gpio_gecko_portf_init(struct device *dev);
+GPIO_PORT_INIT(f, F)
+#endif /* CONFIG_GPIO_GECKO_PORTF */
 
-static const struct gpio_gecko_config gpio_gecko_portf_config = {
-	.gpio_base = &GPIO->P[gpioPortF],
-	.gpio_index = gpioPortF,
-};
+#ifdef CONFIG_GPIO_GECKO_PORTG
+GPIO_PORT_INIT(g, G)
+#endif /* CONFIG_GPIO_GECKO_PORTG */
 
-static struct gpio_gecko_data gpio_gecko_portf_data;
+#ifdef CONFIG_GPIO_GECKO_PORTH
+GPIO_PORT_INIT(h, H)
+#endif /* CONFIG_GPIO_GECKO_PORTH */
 
-DEVICE_AND_API_INIT(gpio_gecko_portf, DT_GPIO_GECKO_PORTF_NAME,
-		    gpio_gecko_portf_init,
-		    &gpio_gecko_portf_data, &gpio_gecko_portf_config,
-		    POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
-		    &gpio_gecko_driver_api);
+#ifdef CONFIG_GPIO_GECKO_PORTI
+GPIO_PORT_INIT(i, I)
+#endif /* CONFIG_GPIO_GECKO_PORTI */
 
-static int gpio_gecko_portf_init(struct device *dev)
-{
-	gpio_gecko_add_port(&gpio_gecko_common_data, dev);
-	return 0;
-}
-#endif /* CONFIG_GPIO_GECKO_PORTF */
+#ifdef CONFIG_GPIO_GECKO_PORTJ
+GPIO_PORT_INIT(j, J)
+#endif /* CONFIG_GPIO_GECKO_PORTJ */
+
+#ifdef CONFIG_GPIO_GECKO_PORTK
+GPIO_PORT_INIT(k, K)
+#endif /* CONFIG_GPIO_GECKO_PORTK */
diff --git a/drivers/gpio/gpio_stm32.c b/drivers/gpio/gpio_stm32.c
index 94676d687e2be..24a65bda45a07 100644
--- a/drivers/gpio/gpio_stm32.c
+++ b/drivers/gpio/gpio_stm32.c
@@ -185,10 +185,79 @@ int gpio_stm32_configure(u32_t *base_addr, int pin, int conf, int altf)
 	return 0;
 }
 
+static inline uint32_t gpio_stm32_pin_to_exti_line(int pin)
+{
+#if defined(CONFIG_SOC_SERIES_STM32L0X) || \
+	defined(CONFIG_SOC_SERIES_STM32F0X)
+	return ((pin % 4 * 4) << 16) | (pin / 4);
+#elif defined(CONFIG_SOC_SERIES_STM32MP1X)
+	return (((pin * 8) % 32) << 16) | (pin / 4);
+#elif defined(CONFIG_SOC_SERIES_STM32G0X)
+	return ((pin & 0x3) << (16 + 3)) | (pin >> 2);
+#else
+	return (0xF << ((pin % 4 * 4) + 16)) | (pin / 4);
+#endif
+}
+
+static void gpio_stm32_set_exti_source(int port, int pin)
+{
+	uint32_t line = gpio_stm32_pin_to_exti_line(pin);
+
+#if defined(CONFIG_SOC_SERIES_STM32L0X) && defined(LL_SYSCFG_EXTI_PORTH)
+	/*
+	 * Ports F and G are not present on some STM32L0 parts, so
+	 * for these parts port H external interrupt should be enabled
+	 * by writing value 0x5 instead of 0x7.
+	 */
+	if (port == STM32_PORTH) {
+		port = LL_SYSCFG_EXTI_PORTH;
+	}
+#endif
+
+#ifdef CONFIG_SOC_SERIES_STM32F1X
+	LL_GPIO_AF_SetEXTISource(port, line);
+#elif CONFIG_SOC_SERIES_STM32MP1X
+	LL_EXTI_SetEXTISource(port, line);
+#elif defined(CONFIG_SOC_SERIES_STM32G0X)
+	LL_EXTI_SetEXTISource(port, line);
+#else
+	LL_SYSCFG_SetEXTISource(port, line);
+#endif
+}
+
+static int gpio_stm32_get_exti_source(int pin)
+{
+	uint32_t line = gpio_stm32_pin_to_exti_line(pin);
+	int port;
+
+#ifdef CONFIG_SOC_SERIES_STM32F1X
+	port = LL_GPIO_AF_GetEXTISource(line);
+#elif CONFIG_SOC_SERIES_STM32MP1X
+	port = LL_EXTI_GetEXTISource(line);
+#elif defined(CONFIG_SOC_SERIES_STM32G0X)
+	port = LL_EXTI_GetEXTISource(line);
+#else
+	port = LL_SYSCFG_GetEXTISource(line);
+#endif
+
+#if defined(CONFIG_SOC_SERIES_STM32L0X) && defined(LL_SYSCFG_EXTI_PORTH)
+	/*
+	 * Ports F and G are not present on some STM32L0 parts, so
+	 * for these parts port H external interrupt is enabled
+	 * by writing value 0x5 instead of 0x7.
+	 */
+	if (port == LL_SYSCFG_EXTI_PORTH) {
+		port = STM32_PORTH;
+	}
+#endif
+
+	return port;
+}
+
 /**
  * @brief Enable EXTI of the specific line
  */
-const int gpio_stm32_enable_int(int port, int pin)
+static int gpio_stm32_enable_int(int port, int pin)
 {
 #if defined(CONFIG_SOC_SERIES_STM32F2X) ||     \
 	defined(CONFIG_SOC_SERIES_STM32F3X) || \
@@ -212,45 +281,25 @@ const int gpio_stm32_enable_int(int port, int pin)
 	clock_control_on(clk, (clock_control_subsys_t *) &pclken);
 #endif
 
-	uint32_t line;
-
 	if (pin > 15) {
 		return -EINVAL;
 	}
 
-#if defined(CONFIG_SOC_SERIES_STM32L0X) || \
-	defined(CONFIG_SOC_SERIES_STM32F0X)
-	line = ((pin % 4 * 4) << 16) | (pin / 4);
-#elif defined(CONFIG_SOC_SERIES_STM32MP1X)
-	line = (((pin * 8) % 32) << 16) | (pin / 4);
-#elif defined(CONFIG_SOC_SERIES_STM32G0X)
-	line = ((pin & 0x3) << (16 + 3)) | (pin >> 2);
-#else
-	line = (0xF << ((pin % 4 * 4) + 16)) | (pin / 4);
-#endif
+	gpio_stm32_set_exti_source(port, pin);
 
-#if defined(CONFIG_SOC_SERIES_STM32L0X) && defined(LL_SYSCFG_EXTI_PORTH)
-	/*
-	 * Ports F and G are not present on some STM32L0 parts, so
-	 * for these parts port H external interrupt should be enabled
-	 * by writing value 0x5 instead of 0x7.
-	 */
-	if (port == STM32_PORTH) {
-		port = LL_SYSCFG_EXTI_PORTH;
-	}
-#endif
+	return 0;
+}
 
-#ifdef CONFIG_SOC_SERIES_STM32F1X
-	LL_GPIO_AF_SetEXTISource(port, line);
-#elif CONFIG_SOC_SERIES_STM32MP1X
-	LL_EXTI_SetEXTISource(port, line);
-#elif defined(CONFIG_SOC_SERIES_STM32G0X)
-	LL_EXTI_SetEXTISource(port, line);
-#else
-	LL_SYSCFG_SetEXTISource(port, line);
-#endif
+/**
+ * @brief Get enabled GPIO port for EXTI of the specific pin number
+ */
+static int gpio_stm32_int_enabled_port(int pin)
+{
+	if (pin > 15) {
+		return -EINVAL;
+	}
 
-	return 0;
+	return gpio_stm32_get_exti_source(pin);
 }
 
 /**
@@ -260,6 +309,7 @@ static int gpio_stm32_config(struct device *dev, int access_op,
 			     u32_t pin, int flags)
 {
 	const struct gpio_stm32_config *cfg = dev->config->config_info;
+	int err = 0;
 	int pincfg;
 	int map_res;
 
@@ -282,18 +332,24 @@ static int gpio_stm32_config(struct device *dev, int access_op,
 	 */
 	map_res = gpio_stm32_flags_to_conf(flags, &pincfg);
 	if (map_res != 0) {
-		return map_res;
+		err = map_res;
+		goto release_lock;
 	}
 
 	if (gpio_stm32_configure(cfg->base, pin, pincfg, 0) != 0) {
-		return -EIO;
+		err = -EIO;
+		goto release_lock;
 	}
 
-	if (IS_ENABLED(CONFIG_EXTI_STM32) && (flags & GPIO_INT) != 0) {
+	if (!IS_ENABLED(CONFIG_EXTI_STM32)) {
+		goto release_lock;
+	}
 
+	if (flags & GPIO_INT) {
 		if (stm32_exti_set_callback(pin, cfg->port,
 					    gpio_stm32_isr, dev) != 0) {
-			return -EBUSY;
+			err = -EBUSY;
+			goto release_lock;
 		}
 
 		gpio_stm32_enable_int(cfg->port, pin);
@@ -313,20 +369,27 @@ static int gpio_stm32_config(struct device *dev, int access_op,
 			stm32_exti_trigger(pin, edge);
 		} else {
 			/* Level trigger interrupts not supported */
-			return -ENOTSUP;
+			err = -ENOTSUP;
+			goto release_lock;
 		}
 
 		if (stm32_exti_enable(pin) != 0) {
-			return -ENOSYS;
+			err = -EIO;
+			goto release_lock;
+		}
+	} else {
+		if (gpio_stm32_int_enabled_port(pin) == cfg->port) {
+			stm32_exti_disable(pin);
+			stm32_exti_unset_callback(pin);
 		}
-
 	}
 
+release_lock:
 #if defined(CONFIG_STM32H7_DUAL_CORE)
 	LL_HSEM_ReleaseLock(HSEM, LL_HSEM_ID_1, 0);
 #endif /* CONFIG_STM32H7_DUAL_CORE */
 
-	return 0;
+	return err;
 }
 
 /**
diff --git a/dts/arm/nxp/nxp_imx6sx_m4.dtsi b/dts/arm/nxp/nxp_imx6sx_m4.dtsi
index b40e35bb1e3e7..f6c124660156d 100644
--- a/dts/arm/nxp/nxp_imx6sx_m4.dtsi
+++ b/dts/arm/nxp/nxp_imx6sx_m4.dtsi
@@ -201,7 +201,7 @@
 		gpio5:gpio@420ac000 {
 			compatible = "nxp,imx-gpio";
 			reg = <0x420ac000 0x4000>;
-			interrupts = <74 0>, <74 0>;
+			interrupts = <74 0>, <75 0>;
 			rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
 					       RDC_DOMAIN_PERM_RW)|\
 			       RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
diff --git a/dts/arm/nxp/nxp_lpc54xxx.dtsi b/dts/arm/nxp/nxp_lpc54xxx.dtsi
index 31dad79df35a9..e12c316d0c62e 100644
--- a/dts/arm/nxp/nxp_lpc54xxx.dtsi
+++ b/dts/arm/nxp/nxp_lpc54xxx.dtsi
@@ -58,18 +58,18 @@
 		};
 
 		gpio0: gpio@0 {
-			compatible = "nxp,kinetis-gpio";
+			compatible = "nxp,lpc-gpio";
 			reg = <0x4008c000 0x2488>;
-			interrupts = <2 2>;
+			interrupts = <4 2>,<5 2>,<6 2>,<7 2>;
 			label = "GPIO_0";
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
 
 		gpio1: gpio@1 {
-			compatible = "nxp,kinetis-gpio";
+			compatible = "nxp,lpc-gpio";
 			reg = <0x4008C000 0x2488>;
-			interrupts = <3 2>;
+			interrupts = <32 2>,<33 2>,<34 2>,<35 2>;
 			label = "GPIO_1";
 			gpio-controller;
 			#gpio-cells = <2>;
diff --git a/dts/arm/nxp/nxp_lpc55S6x.dtsi b/dts/arm/nxp/nxp_lpc55S6x.dtsi
index 094dc26a2fda8..a8f7b732e1207 100644
--- a/dts/arm/nxp/nxp_lpc55S6x.dtsi
+++ b/dts/arm/nxp/nxp_lpc55S6x.dtsi
@@ -63,23 +63,39 @@
 			status = "disabled";
 		};
 
-		gpio0: gpio@0 {
-			compatible = "nxp,kinetis-gpio";
+		gpio0:gpio@0 {
+			compatible = "nxp,lpc-gpio";
 			reg = <0x5008c000 0x2488>;
-			interrupts = <2 2>;
+			interrupts = <4 2>,<5 2>,<6 2>,<7 2>;
 			label = "GPIO_0";
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
 
-		gpio1: gpio@1 {
-			compatible = "nxp,kinetis-gpio";
+		gpio1:gpio@1 {
+			compatible = "nxp,lpc-gpio";
 			reg = <0x5008c000 0x2488>;
-			interrupts = <3 2>;
+			interrupts = <32 2>,<33 2>,<34 2>,<35 2>;
 			label = "GPIO_1";
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
+
+		gpio2:gpio@2 {
+			compatible = "nxp,lpc-gpio";
+			reg = <0x5008c000 0x2488>;
+			label = "GPIO_2";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpio3:gpio@3 {
+			compatible = "nxp,lpc-gpio";
+			reg = <0x5008c000 0x2488>;
+			label = "GPIO_3";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
 	};
 };
 
diff --git a/dts/arm/silabs/efr32mg.dtsi b/dts/arm/silabs/efr32mg.dtsi
index bfce45146825a..7824e91b814b6 100644
--- a/dts/arm/silabs/efr32mg.dtsi
+++ b/dts/arm/silabs/efr32mg.dtsi
@@ -162,18 +162,34 @@
 				#gpio-cells = <2>;
 			};
 
-			gpioe: gpio@4000a0c0 {
+			gpiof: gpio@4000a0f0 {
 				compatible = "silabs,efr32mg-gpio-port";
-				reg = <0x4000a0c0 0x30>;
-				label = "GPIO_E";
+				reg = <0x4000a0f0 0x30>;
+				label = "GPIO_F";
 				gpio-controller;
 				#gpio-cells = <2>;
 			};
 
-			gpiof: gpio@4000a0f0 {
+			gpioi: gpio@4000a180 {
 				compatible = "silabs,efr32mg-gpio-port";
-				reg = <0x4000a0f0 0x30>;
-				label = "GPIO_F";
+				reg = <0x4000a180 0x30>;
+				label = "GPIO_I";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpioj: gpio@4000a1b0 {
+				compatible = "silabs,efr32mg-gpio-port";
+				reg = <0x4000a1b0 0x30>;
+				label = "GPIO_J";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpiok: gpio@4000a1e0 {
+				compatible = "silabs,efr32mg-gpio-port";
+				reg = <0x4000a1e0 0x30>;
+				label = "GPIO_K";
 				gpio-controller;
 				#gpio-cells = <2>;
 			};
diff --git a/dts/bindings/gpio/nxp,lpc-gpio.yaml b/dts/bindings/gpio/nxp,lpc-gpio.yaml
new file mode 100644
index 0000000000000..8ae2c49c0c255
--- /dev/null
+++ b/dts/bindings/gpio/nxp,lpc-gpio.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2019, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+title: LPC GPIO
+
+description: |
+    This is a representation of the LPC GPIO nodes
+
+compatible: "nxp,lpc-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/soc/arm/nxp_lpc/lpc54xxx/soc.c b/soc/arm/nxp_lpc/lpc54xxx/soc.c
index 869a85f9ef5b5..a9273d7769d91 100644
--- a/soc/arm/nxp_lpc/lpc54xxx/soc.c
+++ b/soc/arm/nxp_lpc/lpc54xxx/soc.c
@@ -24,6 +24,7 @@
 #include <fsl_clock.h>
 #include <fsl_common.h>
 #include <fsl_device_registers.h>
+#include <fsl_pint.h>
 
 /**
  *
@@ -90,6 +91,11 @@ static int nxp_lpc54114_init(struct device *arg)
 	/* Initialize FRO/system clock to 48 MHz */
 	clock_init();
 
+#ifdef CONFIG_GPIO_MCUX_LPC
+	/* Turn on PINT device*/
+	PINT_Init(PINT);
+#endif
+
 	/*
 	 * install default handler that simply resets the CPU if configured in
 	 * the kernel, NOP otherwise
diff --git a/soc/arm/nxp_lpc/lpc54xxx/soc.h b/soc/arm/nxp_lpc/lpc54xxx/soc.h
index 91d7dd0744ed3..3372c51ab1057 100644
--- a/soc/arm/nxp_lpc/lpc54xxx/soc.h
+++ b/soc/arm/nxp_lpc/lpc54xxx/soc.h
@@ -34,5 +34,6 @@
 #define IOCON_PIO_OPENDRAIN_DI	0x00u
 #define IOCON_PIO_SLEW_STANDARD	0x00u
 #define IOCON_PIO_MODE_PULLUP	0x10u
+#define IOCON_PIO_MODE_PULLDOWN	0x08u
 
 #endif /* _SOC__H_ */
diff --git a/soc/arm/nxp_lpc/lpc55xxx/soc.c b/soc/arm/nxp_lpc/lpc55xxx/soc.c
index 8a7eb674f7651..29e25342185d8 100644
--- a/soc/arm/nxp_lpc/lpc55xxx/soc.c
+++ b/soc/arm/nxp_lpc/lpc55xxx/soc.c
@@ -24,6 +24,7 @@
 #include <fsl_clock.h>
 #include <fsl_common.h>
 #include <fsl_device_registers.h>
+#include <fsl_pint.h>
 
 /**
  *
@@ -84,9 +85,14 @@ static int nxp_lpc55s69_init(struct device *arg)
 
 	z_arm_clear_faults();
 
-	/* Initialize FRO/system clock to 48 MHz */
+	/* Initialize FRO/system clock to 96 MHz */
 	clock_init();
 
+#ifdef CONFIG_GPIO_MCUX_LPC
+	/* Turn on PINT device*/
+	PINT_Init(PINT);
+#endif
+
 	/*
 	 * install default handler that simply resets the CPU if configured in
 	 * the kernel, NOP otherwise
diff --git a/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h b/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h
index 8ff92e043782c..235521996f47d 100644
--- a/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h
+++ b/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h
@@ -25,7 +25,9 @@
 #define DT_GPIO_GECKO_PORTB_NAME	DT_SILABS_EFR32MG_GPIO_PORT_4000A030_LABEL
 #define DT_GPIO_GECKO_PORTC_NAME	DT_SILABS_EFR32MG_GPIO_PORT_4000A060_LABEL
 #define DT_GPIO_GECKO_PORTD_NAME	DT_SILABS_EFR32MG_GPIO_PORT_4000A090_LABEL
-#define DT_GPIO_GECKO_PORTE_NAME	DT_SILABS_EFR32MG_GPIO_PORT_4000A0C0_LABEL
 #define DT_GPIO_GECKO_PORTF_NAME	DT_SILABS_EFR32MG_GPIO_PORT_4000A0F0_LABEL
+#define DT_GPIO_GECKO_PORTI_NAME	DT_SILABS_EFR32MG_GPIO_PORT_4000A180_LABEL
+#define DT_GPIO_GECKO_PORTJ_NAME	DT_SILABS_EFR32MG_GPIO_PORT_4000A1B0_LABEL
+#define DT_GPIO_GECKO_PORTK_NAME	DT_SILABS_EFR32MG_GPIO_PORT_4000A1E0_LABEL
 
 /* End of SoC Level DTS fixup file */