diff --git a/boards/arm/cc1352r1_launchxl/cc1352r1_launchxl.dts b/boards/arm/cc1352r1_launchxl/cc1352r1_launchxl.dts index c66460528c370..0e905b5011049 100644 --- a/boards/arm/cc1352r1_launchxl/cc1352r1_launchxl.dts +++ b/boards/arm/cc1352r1_launchxl/cc1352r1_launchxl.dts @@ -8,7 +8,7 @@ #include -#define BTN_GPIO_FLAGS (GPIO_INT_ACTIVE_LOW | GPIO_PUD_PULL_UP) +#define BTN_GPIO_FLAGS (GPIO_ACTIVE_LOW | GPIO_PULL_UP) / { model = "TI CC1352R1 LaunchXL"; @@ -31,11 +31,11 @@ leds { compatible = "gpio-leds"; led0: led_0 { - gpios = <&gpio0 7 0>; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; label = "Green LED"; }; led1: led_1 { - gpios = <&gpio0 6 0>; + gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; label = "Red LED"; }; }; diff --git a/boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl.dts b/boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl.dts index 52829ba240563..abdd6fa22c4a8 100644 --- a/boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl.dts +++ b/boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl.dts @@ -8,7 +8,7 @@ #include -#define BTN_GPIO_FLAGS (GPIO_INT_ACTIVE_LOW | GPIO_PUD_PULL_UP) +#define BTN_GPIO_FLAGS (GPIO_ACTIVE_LOW | GPIO_PULL_UP) / { model = "TI CC26x2R1 LaunchXL"; @@ -31,11 +31,11 @@ leds { compatible = "gpio-leds"; led0: led_0 { - gpios = <&gpio0 7 0>; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; label = "Green LED"; }; led1: led_1 { - gpios = <&gpio0 6 0>; + gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; label = "Red LED"; }; }; diff --git a/boards/arm/cc3220sf_launchxl/cc3220sf_launchxl.dts b/boards/arm/cc3220sf_launchxl/cc3220sf_launchxl.dts index c42de92d8eb28..757fa963c740f 100644 --- a/boards/arm/cc3220sf_launchxl/cc3220sf_launchxl.dts +++ b/boards/arm/cc3220sf_launchxl/cc3220sf_launchxl.dts @@ -30,15 +30,15 @@ leds { compatible = "gpio-leds"; led0: led_0 { - gpios = <&gpioa1 3 0>; + gpios = <&gpioa1 3 GPIO_ACTIVE_HIGH>; label = "Green LED"; }; led1: led_1 { - gpios = <&gpioa1 2 0>; + gpios = <&gpioa1 2 GPIO_ACTIVE_HIGH>; label = "Yellow LED"; }; led2: led_2 { - gpios = <&gpioa1 1 0>; + gpios = <&gpioa1 1 GPIO_ACTIVE_HIGH>; label = "Red LED"; }; }; @@ -47,12 +47,12 @@ /* Push button 2 */ compatible = "gpio-keys"; sw2: button_0 { - gpios = <&gpioa2 6 GPIO_INT_ACTIVE_LOW>; + gpios = <&gpioa2 6 GPIO_ACTIVE_HIGH>; label = "Push button switch 2"; }; /* Push button 3 */ sw3: button_1 { - gpios = <&gpioa1 5 GPIO_INT_ACTIVE_LOW>; + gpios = <&gpioa1 5 GPIO_ACTIVE_HIGH>; label = "Push button switch 3"; }; }; diff --git a/boards/arm/cc3235sf_launchxl/cc3235sf_launchxl.dts b/boards/arm/cc3235sf_launchxl/cc3235sf_launchxl.dts index 3c2b6f635fc46..d171cdea78e42 100644 --- a/boards/arm/cc3235sf_launchxl/cc3235sf_launchxl.dts +++ b/boards/arm/cc3235sf_launchxl/cc3235sf_launchxl.dts @@ -34,15 +34,15 @@ leds { compatible = "gpio-leds"; led0: led_0 { - gpios = <&gpioa1 3 0>; + gpios = <&gpioa1 3 GPIO_ACTIVE_HIGH>; label = "Green LED"; }; led1: led_1 { - gpios = <&gpioa1 2 0>; + gpios = <&gpioa1 2 GPIO_ACTIVE_HIGH>; label = "Yellow LED"; }; led2: led_2 { - gpios = <&gpioa1 1 0>; + gpios = <&gpioa1 1 GPIO_ACTIVE_HIGH>; label = "Red LED"; }; }; @@ -51,12 +51,12 @@ /* Push button 2 */ compatible = "gpio-keys"; sw2: button_0 { - gpios = <&gpioa2 6 GPIO_INT_ACTIVE_LOW>; + gpios = <&gpioa2 6 GPIO_ACTIVE_HIGH>; label = "Push button switch 2"; }; /* Push button 3 */ sw3: button_1 { - gpios = <&gpioa1 5 GPIO_INT_ACTIVE_LOW>; + gpios = <&gpioa1 5 GPIO_ACTIVE_HIGH>; label = "Push button switch 3"; }; }; diff --git a/drivers/gpio/gpio_cc13xx_cc26xx.c b/drivers/gpio/gpio_cc13xx_cc26xx.c index 63656e3cda2f1..7a40642e90c91 100644 --- a/drivers/gpio/gpio_cc13xx_cc26xx.c +++ b/drivers/gpio/gpio_cc13xx_cc26xx.c @@ -17,6 +17,12 @@ #include "gpio_utils.h" +/* bits 16-18 in iocfg registers correspond to interrupt settings */ +#define IOCFG_INT_MASK 0x00070000 + +/* the rest are for general (non-interrupt) config */ +#define IOCFG_GEN_MASK (~IOCFG_INT_MASK) + struct gpio_cc13xx_cc26xx_data { /* gpio_driver_data needs to be first */ struct gpio_driver_data common; @@ -26,10 +32,15 @@ struct gpio_cc13xx_cc26xx_data { static struct gpio_cc13xx_cc26xx_data gpio_cc13xx_cc26xx_data_0; +static int gpio_cc13xx_cc26xx_port_set_bits_raw(struct device *port, + u32_t mask); +static int gpio_cc13xx_cc26xx_port_clear_bits_raw(struct device *port, + u32_t mask); + static int gpio_cc13xx_cc26xx_config(struct device *port, int access_op, u32_t pin, int flags) { - u32_t config; + u32_t config = 0; if (access_op != GPIO_ACCESS_BY_PIN) { return -ENOTSUP; @@ -37,37 +48,26 @@ static int gpio_cc13xx_cc26xx_config(struct device *port, int access_op, __ASSERT_NO_MSG(pin < NUM_IO_MAX); - config = IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_SLEW_DISABLE | - IOC_NO_WAKE_UP; - - if (flags & GPIO_INT) { - __ASSERT_NO_MSG((flags & GPIO_DIR_MASK) == GPIO_DIR_IN); - - config |= IOC_INT_ENABLE | IOC_INPUT_ENABLE; + switch (flags & (GPIO_INPUT | GPIO_OUTPUT)) { + case GPIO_INPUT: + config = IOC_INPUT_ENABLE; + break; + case GPIO_OUTPUT: + config = IOC_INPUT_DISABLE; + break; + case 0: /* disconnected */ + IOCPortConfigureSet(pin, IOC_PORT_GPIO, IOC_NO_IOPULL); + GPIO_setOutputEnableDio(pin, GPIO_OUTPUT_DISABLE); + return 0; + default: + return -ENOTSUP; + } - if (flags & GPIO_INT_EDGE) { - if (flags & GPIO_INT_DOUBLE_EDGE) { - config |= IOC_BOTH_EDGES; - } else if (flags & GPIO_INT_ACTIVE_HIGH) { - config |= IOC_RISING_EDGE; - } else { /* GPIO_INT_ACTIVE_LOW */ - config |= IOC_FALLING_EDGE; - } - } else { - return -ENOTSUP; - } + config |= IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_SLEW_DISABLE | + IOC_NO_WAKE_UP; - config |= (flags & GPIO_INT_DEBOUNCE) ? IOC_HYST_ENABLE : + config |= (flags & GPIO_INT_DEBOUNCE) ? IOC_HYST_ENABLE : IOC_HYST_DISABLE; - } else { - config |= IOC_INT_DISABLE | IOC_NO_EDGE | IOC_HYST_DISABLE; - config |= (flags & GPIO_DIR_MASK) == GPIO_DIR_IN ? - IOC_INPUT_ENABLE : - IOC_INPUT_DISABLE; - } - - config |= (flags & GPIO_POL_MASK) == GPIO_POL_INV ? IOC_IOMODE_INV : - IOC_IOMODE_NORMAL; switch (flags & GPIO_PUD_MASK) { case GPIO_PUD_NORMAL: @@ -83,12 +83,18 @@ static int gpio_cc13xx_cc26xx_config(struct device *port, int access_op, return -EINVAL; } + config |= IOCPortConfigureGet(pin) & IOCFG_INT_MASK; IOCPortConfigureSet(pin, IOC_PORT_GPIO, config); - if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) { - GPIO_setOutputEnableDio(pin, GPIO_OUTPUT_DISABLE); - } else { + if ((flags & GPIO_OUTPUT) != 0) { + if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) { + gpio_cc13xx_cc26xx_port_set_bits_raw(port, BIT(pin)); + } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) { + gpio_cc13xx_cc26xx_port_clear_bits_raw(port, BIT(pin)); + } GPIO_setOutputEnableDio(pin, GPIO_OUTPUT_ENABLE); + } else { + GPIO_setOutputEnableDio(pin, GPIO_OUTPUT_DISABLE); } return 0; @@ -140,6 +146,80 @@ static int gpio_cc13xx_cc26xx_read(struct device *port, int access_op, return 0; } +static int gpio_cc13xx_cc26xx_port_get_raw(struct device *port, u32_t *value) +{ + __ASSERT_NO_MSG(value != NULL); + + *value = GPIO_readMultiDio(GPIO_DIO_ALL_MASK); + + return 0; +} + +static int gpio_cc13xx_cc26xx_port_set_masked_raw(struct device *port, + u32_t mask, u32_t value) +{ + GPIO_setMultiDio(mask & value); + GPIO_clearMultiDio(mask & ~value); + + return 0; +} + +static int gpio_cc13xx_cc26xx_port_set_bits_raw(struct device *port, u32_t mask) +{ + GPIO_setMultiDio(mask); + + return 0; +} + +static int gpio_cc13xx_cc26xx_port_clear_bits_raw(struct device *port, + u32_t mask) +{ + GPIO_clearMultiDio(mask); + + return 0; +} + +static int gpio_cc13xx_cc26xx_port_toggle_bits(struct device *port, u32_t mask) +{ + GPIO_toggleMultiDio(mask); + + return 0; +} + +static int gpio_cc13xx_cc26xx_pin_interrupt_configure(struct device *port, + unsigned int pin, enum gpio_int_mode mode, + enum gpio_int_trig trig) +{ + struct gpio_cc13xx_cc26xx_data *data = port->driver_data; + u32_t config = 0; + + if (mode != GPIO_INT_MODE_DISABLED) { + if (mode == GPIO_INT_MODE_EDGE) { + if (trig == GPIO_INT_TRIG_BOTH) { + config |= IOC_BOTH_EDGES; + } else if (trig == GPIO_INT_TRIG_HIGH) { + config |= IOC_RISING_EDGE; + } else { /* GPIO_INT_TRIG_LOW */ + config |= IOC_FALLING_EDGE; + } + } else { + return -ENOTSUP; + } + + config |= IOC_INT_ENABLE; + } else { + config |= IOC_INT_DISABLE | IOC_NO_EDGE; + } + + config |= IOCPortConfigureGet(pin) & IOCFG_GEN_MASK; + IOCPortConfigureSet(pin, IOC_PORT_GPIO, config); + + WRITE_BIT(data->pin_callback_enables, pin, + mode != GPIO_INT_MODE_DISABLED); + + return 0; +} + static int gpio_cc13xx_cc26xx_manage_callback(struct device *port, struct gpio_callback *callback, bool set) @@ -247,6 +327,12 @@ static const struct gpio_driver_api gpio_cc13xx_cc26xx_driver_api = { .config = gpio_cc13xx_cc26xx_config, .write = gpio_cc13xx_cc26xx_write, .read = gpio_cc13xx_cc26xx_read, + .port_get_raw = gpio_cc13xx_cc26xx_port_get_raw, + .port_set_masked_raw = gpio_cc13xx_cc26xx_port_set_masked_raw, + .port_set_bits_raw = gpio_cc13xx_cc26xx_port_set_bits_raw, + .port_clear_bits_raw = gpio_cc13xx_cc26xx_port_clear_bits_raw, + .port_toggle_bits = gpio_cc13xx_cc26xx_port_toggle_bits, + .pin_interrupt_configure = gpio_cc13xx_cc26xx_pin_interrupt_configure, .manage_callback = gpio_cc13xx_cc26xx_manage_callback, .enable_callback = gpio_cc13xx_cc26xx_enable_callback, .disable_callback = gpio_cc13xx_cc26xx_disable_callback, diff --git a/drivers/gpio/gpio_cc32xx.c b/drivers/gpio/gpio_cc32xx.c index 740987b6213a2..b0de3f763963d 100644 --- a/drivers/gpio/gpio_cc32xx.c +++ b/drivers/gpio/gpio_cc32xx.c @@ -25,11 +25,29 @@ #include "gpio_utils.h" +/* Reserved */ +#define PIN_XX 0xFF + +static const u8_t pinTable[] = { + /* 00 01 02 03 04 05 06 07 */ + PIN_50, PIN_55, PIN_57, PIN_58, PIN_59, PIN_60, PIN_61, PIN_62, + /* 08 09 10 11 12 13 14 15 */ + PIN_63, PIN_64, PIN_01, PIN_02, PIN_03, PIN_04, PIN_05, PIN_06, + /* 16 17 18 19 20 21 22 23 */ + PIN_07, PIN_08, PIN_XX, PIN_XX, PIN_XX, PIN_XX, PIN_15, PIN_16, + /* 24 25 26 27 28 29 30 31 */ + PIN_17, PIN_21, PIN_29, PIN_30, PIN_18, PIN_20, PIN_53, PIN_45, + /* 32 */ + PIN_52 +}; + struct gpio_cc32xx_config { /* base address of GPIO port */ unsigned long port_base; /* GPIO IRQ number */ unsigned long irq_num; + /* GPIO port number */ + u8_t port_num; }; struct gpio_cc32xx_data { @@ -46,42 +64,42 @@ struct gpio_cc32xx_data { #define DEV_DATA(dev) \ ((struct gpio_cc32xx_data *)(dev)->driver_data) +static int gpio_cc32xx_port_set_bits_raw(struct device *port, u32_t mask); +static int gpio_cc32xx_port_clear_bits_raw(struct device *port, u32_t mask); + static inline int gpio_cc32xx_config(struct device *port, int access_op, u32_t pin, int flags) { const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port); unsigned long port_base = gpio_config->port_base; - unsigned long int_type; - /* - * See pinmux_initialize(): which leverages TI's recommended - * method of using the PinMux utility for most pin configuration. - */ + if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) { + return -ENOTSUP; + } - if (access_op == GPIO_ACCESS_BY_PIN) { - /* Just handle runtime interrupt type config here: */ - if (flags & GPIO_INT) { - if (flags & GPIO_INT_EDGE) { - if (flags & GPIO_INT_ACTIVE_HIGH) { - int_type = GPIO_RISING_EDGE; - } else if (flags & GPIO_INT_DOUBLE_EDGE) { - int_type = GPIO_BOTH_EDGES; - } else { - int_type = GPIO_FALLING_EDGE; - } - } else { /* GPIO_INT_LEVEL */ - if (flags & GPIO_INT_ACTIVE_HIGH) { - int_type = GPIO_HIGH_LEVEL; - } else { - int_type = GPIO_LOW_LEVEL; - } - } - MAP_GPIOIntTypeSet(port_base, (1 << pin), int_type); - MAP_GPIOIntClear(port_base, (1 << pin)); - MAP_GPIOIntEnable(port_base, (1 << pin)); + if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == 0) { + return -ENOTSUP; + } + + if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) { + return -ENOTSUP; + } + + if (access_op != GPIO_ACCESS_BY_PIN) { + return -ENOTSUP; + } + + MAP_PinTypeGPIO(pinTable[gpio_config->port_num * 8 + pin], + PIN_MODE_0, false); + if (flags & GPIO_OUTPUT) { + MAP_GPIODirModeSet(port_base, (1 << pin), GPIO_DIR_MODE_OUT); + if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) { + gpio_cc32xx_port_set_bits_raw(port, BIT(pin)); + } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) { + gpio_cc32xx_port_clear_bits_raw(port, BIT(pin)); } } else { - return -ENOTSUP; + MAP_GPIODirModeSet(port_base, (1 << pin), GPIO_DIR_MODE_IN); } return 0; @@ -93,12 +111,15 @@ static inline int gpio_cc32xx_write(struct device *port, const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port); unsigned long port_base = gpio_config->port_base; + __ASSERT(pin < 8, "Invalid pin number - only 8 pins per port"); + if (access_op == GPIO_ACCESS_BY_PIN) { value = value << pin; /* Bitpack external GPIO pin number for GPIOPinWrite API: */ pin = 1 << pin; - MAP_GPIOPinWrite(port_base, (unsigned char)pin, value); + MAP_GPIOPinWrite(port_base, (unsigned char)pin, + (unsigned char)value); } else { return -ENOTSUP; } @@ -114,6 +135,8 @@ static inline int gpio_cc32xx_read(struct device *port, long status; unsigned char pin_packed; + __ASSERT(pin < 8, "Invalid pin number - only 8 pins per port"); + if (access_op == GPIO_ACCESS_BY_PIN) { /* Bitpack external GPIO pin number for GPIOPinRead API: */ pin_packed = 1 << pin; @@ -126,6 +149,102 @@ static inline int gpio_cc32xx_read(struct device *port, return 0; } +static int gpio_cc32xx_port_get_raw(struct device *port, u32_t *value) +{ + const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port); + unsigned long port_base = gpio_config->port_base; + unsigned char pin_packed = 0xFF; + + *value = MAP_GPIOPinRead(port_base, pin_packed); + + return 0; +} + +static int gpio_cc32xx_port_set_masked_raw(struct device *port, u32_t mask, + u32_t value) +{ + const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port); + unsigned long port_base = gpio_config->port_base; + + MAP_GPIOPinWrite(port_base, (unsigned char)mask, (unsigned char)value); + + return 0; +} + +static int gpio_cc32xx_port_set_bits_raw(struct device *port, u32_t mask) +{ + const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port); + unsigned long port_base = gpio_config->port_base; + + MAP_GPIOPinWrite(port_base, (unsigned char)mask, (unsigned char)mask); + + return 0; +} + +static int gpio_cc32xx_port_clear_bits_raw(struct device *port, u32_t mask) +{ + const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port); + unsigned long port_base = gpio_config->port_base; + + MAP_GPIOPinWrite(port_base, (unsigned char)mask, (unsigned char)~mask); + + return 0; +} + +static int gpio_cc32xx_port_toggle_bits(struct device *port, u32_t mask) +{ + const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port); + unsigned long port_base = gpio_config->port_base; + long value; + + value = MAP_GPIOPinRead(port_base, mask); + + MAP_GPIOPinWrite(port_base, (unsigned char)mask, + (unsigned char)~value); + + return 0; +} + +static int gpio_cc32xx_pin_interrupt_configure(struct device *port, + unsigned int pin, enum gpio_int_mode mode, + enum gpio_int_trig trig) +{ + const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port); + struct gpio_cc32xx_data *data = DEV_DATA(port); + unsigned long port_base = gpio_config->port_base; + unsigned long int_type; + + __ASSERT(pin < 8, "Invalid pin number - only 8 pins per port"); + + if (mode != GPIO_INT_MODE_DISABLED) { + if (mode == GPIO_INT_MODE_EDGE) { + if (trig == GPIO_INT_TRIG_BOTH) { + int_type = GPIO_BOTH_EDGES; + } else if (trig == GPIO_INT_TRIG_HIGH) { + int_type = GPIO_RISING_EDGE; + } else { + int_type = GPIO_FALLING_EDGE; + } + } else { /* GPIO_INT_LEVEL */ + if (trig == GPIO_INT_TRIG_HIGH) { + int_type = GPIO_HIGH_LEVEL; + } else { + int_type = GPIO_LOW_LEVEL; + } + } + MAP_GPIOIntTypeSet(port_base, (1 << pin), int_type); + MAP_GPIOIntClear(port_base, (1 << pin)); + MAP_GPIOIntEnable(port_base, (1 << pin)); + + WRITE_BIT(data->pin_callback_enables, pin, + mode != GPIO_INT_MODE_DISABLED); + } else { + MAP_GPIOIntDisable(port_base, (1 << pin)); + } + + return 0; +} + static int gpio_cc32xx_manage_callback(struct device *dev, struct gpio_callback *callback, bool set) { @@ -140,6 +259,8 @@ static int gpio_cc32xx_enable_callback(struct device *dev, { struct gpio_cc32xx_data *data = DEV_DATA(dev); + __ASSERT(pin < 8, "Invalid pin number - only 8 pins per port"); + if (access_op == GPIO_ACCESS_BY_PIN) { data->pin_callback_enables |= (1 << pin); } else { @@ -155,6 +276,8 @@ static int gpio_cc32xx_disable_callback(struct device *dev, { struct gpio_cc32xx_data *data = DEV_DATA(dev); + __ASSERT(pin < 8, "Invalid pin number - only 8 pins per port"); + if (access_op == GPIO_ACCESS_BY_PIN) { data->pin_callback_enables &= ~(1 << pin); } else { @@ -192,6 +315,12 @@ static const struct gpio_driver_api api_funcs = { .config = gpio_cc32xx_config, .write = gpio_cc32xx_write, .read = gpio_cc32xx_read, + .port_get_raw = gpio_cc32xx_port_get_raw, + .port_set_masked_raw = gpio_cc32xx_port_set_masked_raw, + .port_set_bits_raw = gpio_cc32xx_port_set_bits_raw, + .port_clear_bits_raw = gpio_cc32xx_port_clear_bits_raw, + .port_toggle_bits = gpio_cc32xx_port_toggle_bits, + .pin_interrupt_configure = gpio_cc32xx_pin_interrupt_configure, .manage_callback = gpio_cc32xx_manage_callback, .enable_callback = gpio_cc32xx_enable_callback, .disable_callback = gpio_cc32xx_disable_callback, @@ -202,6 +331,7 @@ static const struct gpio_driver_api api_funcs = { static const struct gpio_cc32xx_config gpio_cc32xx_a0_config = { .port_base = DT_GPIO_CC32XX_A0_BASE_ADDRESS, .irq_num = DT_GPIO_CC32XX_A0_IRQ+16, + .port_num = 0 }; static struct device DEVICE_NAME_GET(gpio_cc32xx_a0); @@ -232,6 +362,7 @@ DEVICE_AND_API_INIT(gpio_cc32xx_a0, DT_GPIO_CC32XX_A0_NAME, static const struct gpio_cc32xx_config gpio_cc32xx_a1_config = { .port_base = DT_GPIO_CC32XX_A1_BASE_ADDRESS, .irq_num = DT_GPIO_CC32XX_A1_IRQ+16, + .port_num = 1 }; static struct device DEVICE_NAME_GET(gpio_cc32xx_a1); @@ -262,6 +393,7 @@ DEVICE_AND_API_INIT(gpio_cc32xx_a1, DT_GPIO_CC32XX_A1_NAME, static const struct gpio_cc32xx_config gpio_cc32xx_a2_config = { .port_base = DT_GPIO_CC32XX_A2_BASE_ADDRESS, .irq_num = DT_GPIO_CC32XX_A2_IRQ+16, + .port_num = 2 }; static struct device DEVICE_NAME_GET(gpio_cc32xx_a2); @@ -292,6 +424,7 @@ DEVICE_AND_API_INIT(gpio_cc32xx_a2, DT_GPIO_CC32XX_A2_NAME, static const struct gpio_cc32xx_config gpio_cc32xx_a3_config = { .port_base = DT_GPIO_CC32XX_A3_BASE_ADDRESS, .irq_num = DT_GPIO_CC32XX_A3_IRQ+16, + .port_num = 3 }; static struct device DEVICE_NAME_GET(gpio_cc32xx_a3); diff --git a/tests/drivers/gpio/gpio_basic_api/boards/cc1352r1_launchxl.overlay b/tests/drivers/gpio/gpio_basic_api/boards/cc1352r1_launchxl.overlay new file mode 100644 index 0000000000000..62e4fa2b2cd45 --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/cc1352r1_launchxl.overlay @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2019 Linaro Limited. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Connect DIO21 to DIO22 to run this test */ + +/ { + resources { + compatible = "test,gpio_basic_api"; + out-gpios = <&gpio0 22 0>; + in-gpios = <&gpio0 21 0>; + }; +}; + diff --git a/tests/drivers/gpio/gpio_basic_api/boards/cc3220sf_launchxl.overlay b/tests/drivers/gpio/gpio_basic_api/boards/cc3220sf_launchxl.overlay new file mode 100644 index 0000000000000..4151dd75c8c52 --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/cc3220sf_launchxl.overlay @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2019 Linaro Limited. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Connect P07 to P08 to run this test */ + +/ { + resources { + compatible = "test,gpio_basic_api"; + out-gpios = <&gpioa2 1 0>; + in-gpios = <&gpioa2 0 0>; + }; +}; + diff --git a/tests/drivers/gpio/gpio_basic_api/boards/cc3235sf_launchxl.overlay b/tests/drivers/gpio/gpio_basic_api/boards/cc3235sf_launchxl.overlay new file mode 100644 index 0000000000000..4151dd75c8c52 --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/cc3235sf_launchxl.overlay @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2019 Linaro Limited. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Connect P07 to P08 to run this test */ + +/ { + resources { + compatible = "test,gpio_basic_api"; + out-gpios = <&gpioa2 1 0>; + in-gpios = <&gpioa2 0 0>; + }; +}; +