diff --git a/boards/arm/96b_meerkat96/96b_meerkat96.dts b/boards/arm/96b_meerkat96/96b_meerkat96.dts index 23ed272d547f5..127d697920a3e 100644 --- a/boards/arm/96b_meerkat96/96b_meerkat96.dts +++ b/boards/arm/96b_meerkat96/96b_meerkat96.dts @@ -21,19 +21,19 @@ leds { compatible = "gpio-leds"; green_led_0: led_0 { - gpios = <&gpio1 4 GPIO_INT_ACTIVE_LOW>; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; label = "User LED1"; }; green_led_1: led_1 { - gpios = <&gpio1 5 GPIO_INT_ACTIVE_LOW>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; label = "User LED2"; }; green_led_2: led_2 { - gpios = <&gpio1 6 GPIO_INT_ACTIVE_LOW>; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; label = "User LED3"; }; green_led_3: led_3 { - gpios = <&gpio1 7 GPIO_INT_ACTIVE_LOW>; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; label = "User LED4"; }; }; diff --git a/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.dts b/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.dts index 9fb700632e266..5f404ad577f32 100644 --- a/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.dts +++ b/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, NXP + * Copyright (c) 2017,2019 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -33,7 +33,7 @@ leds { compatible = "gpio-leds"; green_led: led_0 { - gpios = <&gpio1 2 GPIO_INT_ACTIVE_LOW>; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; label = "User LED1"; }; }; @@ -41,7 +41,7 @@ gpio_keys { compatible = "gpio-keys"; user_switch_1: user_sw_1 { - gpios = <&gpio2 26 GPIO_INT_ACTIVE_LOW>; + gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; label = "User SW1"; }; }; diff --git a/boards/arm/warp7_m4/warp7_m4.dts b/boards/arm/warp7_m4/warp7_m4.dts index d93109414fb98..b47179650af49 100644 --- a/boards/arm/warp7_m4/warp7_m4.dts +++ b/boards/arm/warp7_m4/warp7_m4.dts @@ -31,7 +31,7 @@ gpio_keys { compatible = "gpio-keys"; user_switch_1: user_sw_1 { - gpios = <&gpio7 1 GPIO_INT_ACTIVE_LOW>; + gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; label = "User SW1"; }; }; diff --git a/drivers/gpio/gpio_imx.c b/drivers/gpio/gpio_imx.c index d8413bf220c96..bd5e3e95679e8 100644 --- a/drivers/gpio/gpio_imx.c +++ b/drivers/gpio/gpio_imx.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, NXP + * Copyright (c) 2018-2019, NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "gpio_utils.h" @@ -25,62 +26,52 @@ struct imx_gpio_data { u32_t pin_callback_enables; }; -static int imx_gpio_configure(struct device *dev, - int access_op, u32_t pin, int flags) +static int imx_gpio_configure(struct device *port, int access_op, u32_t pin, + int flags) { - const struct imx_gpio_config *config = dev->config->config_info; - gpio_init_config_t pin_config; - bool double_edge = false; - u32_t i; + const struct imx_gpio_config *config = port->config->config_info; + GPIO_Type *base = config->base; - /* Check for an invalid pin configuration */ - if ((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) { - return -EINVAL; + if (access_op != GPIO_ACCESS_BY_PIN) { + return -ENOTSUP; } - pin_config.direction = ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) - ? gpioDigitalInput : gpioDigitalOutput; - - if (flags & GPIO_INT) { - if (flags & GPIO_INT_EDGE) { - if (flags & GPIO_INT_ACTIVE_HIGH) { - pin_config.interruptMode = gpioIntRisingEdge; - } else if (flags & GPIO_INT_DOUBLE_EDGE) { - pin_config.interruptMode = gpioNoIntmode; - double_edge = true; - } else { - pin_config.interruptMode = gpioIntFallingEdge; - } - } else { /* GPIO_INT_LEVEL */ - if (flags & GPIO_INT_ACTIVE_HIGH) { - pin_config.interruptMode = gpioIntHighLevel; - } else { - pin_config.interruptMode = gpioIntLowLevel; - } - } - } else { - pin_config.interruptMode = gpioNoIntmode; + if (((flags & GPIO_INPUT) != 0U) && ((flags & GPIO_OUTPUT) != 0U)) { + return -ENOTSUP; } - if (access_op == GPIO_ACCESS_BY_PIN) { - pin_config.pin = pin; - GPIO_Init(config->base, &pin_config); - GPIO_SetIntEdgeSelect(config->base, pin, double_edge); - } else { /* GPIO_ACCESS_BY_PORT */ - for (i = 0U; i < 32; i++) { - pin_config.pin = i; - GPIO_Init(config->base, &pin_config); - GPIO_SetIntEdgeSelect(config->base, i, double_edge); + if ((flags & (GPIO_SINGLE_ENDED + | GPIO_PULL_UP + | GPIO_PULL_DOWN)) != 0U) { + return -ENOTSUP; + } + + /* Disable interrupts for pin */ + GPIO_SetPinIntMode(base, pin, false); + GPIO_SetIntEdgeSelect(base, pin, false); + + if ((flags & GPIO_OUTPUT) != 0U) { + /* Set output pin initial value */ + if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) { + GPIO_WritePinOutput(base, pin, gpioPinClear); + } else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) { + GPIO_WritePinOutput(base, pin, gpioPinSet); } + + /* Set pin as output */ + WRITE_BIT(base->GDIR, pin, 1U); + } else { + /* Set pin as input */ + WRITE_BIT(base->GDIR, pin, 0U); } return 0; } -static int imx_gpio_write(struct device *dev, - int access_op, u32_t pin, u32_t value) +static int imx_gpio_write(struct device *port, + int access_op, u32_t pin, u32_t value) { - const struct imx_gpio_config *config = dev->config->config_info; + const struct imx_gpio_config *config = port->config->config_info; if (access_op == GPIO_ACCESS_BY_PIN) { GPIO_WritePinOutput(config->base, pin, @@ -92,10 +83,10 @@ static int imx_gpio_write(struct device *dev, return 0; } -static int imx_gpio_read(struct device *dev, - int access_op, u32_t pin, u32_t *value) +static int imx_gpio_read(struct device *port, + int access_op, u32_t pin, u32_t *value) { - const struct imx_gpio_config *config = dev->config->config_info; + const struct imx_gpio_config *config = port->config->config_info; if (access_op == GPIO_ACCESS_BY_PIN) { *value = GPIO_ReadPinInput(config->base, pin); @@ -106,27 +97,138 @@ static int imx_gpio_read(struct device *dev, return 0; } -static int imx_gpio_manage_callback(struct device *dev, - struct gpio_callback *callback, bool set) +static int imx_gpio_port_get_raw(struct device *port, u32_t *value) +{ + const struct imx_gpio_config *config = port->config->config_info; + GPIO_Type *base = config->base; + + *value = GPIO_ReadPortInput(base); + + return 0; +} + +static int imx_gpio_port_set_masked_raw(struct device *port, + gpio_port_pins_t mask, + gpio_port_value_t value) +{ + const struct imx_gpio_config *config = port->config->config_info; + GPIO_Type *base = config->base; + + GPIO_WritePortOutput(base, + (GPIO_ReadPortInput(base) & ~mask) | (value & mask)); + + return 0; +} + +static int imx_gpio_port_set_bits_raw(struct device *port, + gpio_port_pins_t pins) +{ + const struct imx_gpio_config *config = port->config->config_info; + GPIO_Type *base = config->base; + + GPIO_WritePortOutput(base, GPIO_ReadPortInput(base) | pins); + + return 0; +} + +static int imx_gpio_port_clear_bits_raw(struct device *port, + gpio_port_pins_t pins) +{ + const struct imx_gpio_config *config = port->config->config_info; + GPIO_Type *base = config->base; + + GPIO_WritePortOutput(base, GPIO_ReadPortInput(base) & ~pins); + + return 0; +} + +static int imx_gpio_port_toggle_bits(struct device *port, gpio_port_pins_t pins) +{ + const struct imx_gpio_config *config = port->config->config_info; + GPIO_Type *base = config->base; + + GPIO_WritePortOutput(base, GPIO_ReadPortInput(base) ^ pins); + + return 0; +} + +static int imx_gpio_pin_interrupt_configure(struct device *port, + unsigned int pin, + enum gpio_int_mode mode, + enum gpio_int_trig trig) +{ + const struct imx_gpio_config *config = port->config->config_info; + struct imx_gpio_data *data = port->driver_data; + GPIO_Type *base = config->base; + volatile u32_t *icr_reg; + unsigned int key; + u32_t icr_val; + u8_t shift; + + if (((base->GDIR & BIT(pin)) != 0U) + && (mode != GPIO_INT_MODE_DISABLED)) { + /* Interrupt on output pin not supported */ + return -ENOTSUP; + } + + if ((mode == GPIO_INT_MODE_EDGE) && (trig == GPIO_INT_TRIG_LOW)) { + icr_val = 3U; + } else if ((mode == GPIO_INT_MODE_EDGE) && + (trig == GPIO_INT_TRIG_HIGH)) { + icr_val = 2U; + } else if ((mode == GPIO_INT_MODE_LEVEL) && + (trig == GPIO_INT_TRIG_HIGH)) { + icr_val = 1U; + } else { + icr_val = 0U; + } + + if (pin < 16U) { + shift = 2U * pin; + icr_reg = &(base->ICR1); + } else if (pin < 32U) { + shift = 2U * (pin - 16U); + icr_reg = &(base->ICR2); + } else { + return -EINVAL; + } + + key = irq_lock(); + + *icr_reg = (*icr_reg & ~(3U << shift)) | (icr_val << shift); + + WRITE_BIT(base->EDGE_SEL, pin, trig == GPIO_INT_TRIG_BOTH); + WRITE_BIT(base->ISR, pin, mode != GPIO_INT_MODE_DISABLED); + WRITE_BIT(base->IMR, pin, mode != GPIO_INT_MODE_DISABLED); + WRITE_BIT(data->pin_callback_enables, pin, + mode != GPIO_INT_MODE_DISABLED); + + irq_unlock(key); + + return 0; +} + +static int imx_gpio_manage_callback(struct device *port, + struct gpio_callback *cb, bool set) { - struct imx_gpio_data *data = dev->driver_data; + struct imx_gpio_data *data = port->driver_data; - return gpio_manage_callback(&data->callbacks, callback, set); + return gpio_manage_callback(&data->callbacks, cb, set); } -static int imx_gpio_enable_callback(struct device *dev, - int access_op, u32_t pin) +static int imx_gpio_enable_callback(struct device *port, int access_op, + u32_t pin) { - const struct imx_gpio_config *config = dev->config->config_info; - struct imx_gpio_data *data = dev->driver_data; + const struct imx_gpio_config *config = port->config->config_info; + struct imx_gpio_data *data = port->driver_data; u32_t i; if (access_op == GPIO_ACCESS_BY_PIN) { data->pin_callback_enables |= BIT(pin); GPIO_SetPinIntMode(config->base, pin, true); } else { - data->pin_callback_enables = 0xFFFFFFFF; - for (i = 0U; i < 32; i++) { + data->pin_callback_enables = 0xFFFFFFFFU; + for (i = 0U; i < 32U; i++) { GPIO_SetPinIntMode(config->base, i, true); } } @@ -134,18 +236,18 @@ static int imx_gpio_enable_callback(struct device *dev, return 0; } -static int imx_gpio_disable_callback(struct device *dev, - int access_op, u32_t pin) +static int imx_gpio_disable_callback(struct device *port, int access_op, + u32_t pin) { - const struct imx_gpio_config *config = dev->config->config_info; - struct imx_gpio_data *data = dev->driver_data; + const struct imx_gpio_config *config = port->config->config_info; + struct imx_gpio_data *data = port->driver_data; u32_t i; if (access_op == GPIO_ACCESS_BY_PIN) { GPIO_SetPinIntMode(config->base, pin, false); data->pin_callback_enables &= ~BIT(pin); } else { - for (i = 0U; i < 32; i++) { + for (i = 0U; i < 32U; i++) { GPIO_SetPinIntMode(config->base, i, false); } data->pin_callback_enables = 0U; @@ -156,31 +258,34 @@ static int imx_gpio_disable_callback(struct device *dev, static void imx_gpio_port_isr(void *arg) { - struct device *dev = (struct device *)arg; - const struct imx_gpio_config *config = dev->config->config_info; - struct imx_gpio_data *data = dev->driver_data; + struct device *port = (struct device *)arg; + const struct imx_gpio_config *config = port->config->config_info; + struct imx_gpio_data *data = port->driver_data; u32_t enabled_int; - u32_t int_flags; - - int_flags = GPIO_ISR_REG(config->base); - enabled_int = int_flags & data->pin_callback_enables; - gpio_fire_callbacks(&data->callbacks, dev, enabled_int); + enabled_int = config->base->ISR & data->pin_callback_enables; + config->base->ISR = enabled_int; - GPIO_ISR_REG(config->base) = enabled_int; + gpio_fire_callbacks(&data->callbacks, port, enabled_int); } static const struct gpio_driver_api imx_gpio_driver_api = { .config = imx_gpio_configure, .write = imx_gpio_write, .read = imx_gpio_read, + .port_get_raw = imx_gpio_port_get_raw, + .port_set_masked_raw = imx_gpio_port_set_masked_raw, + .port_set_bits_raw = imx_gpio_port_set_bits_raw, + .port_clear_bits_raw = imx_gpio_port_clear_bits_raw, + .port_toggle_bits = imx_gpio_port_toggle_bits, + .pin_interrupt_configure = imx_gpio_pin_interrupt_configure, .manage_callback = imx_gpio_manage_callback, .enable_callback = imx_gpio_enable_callback, .disable_callback = imx_gpio_disable_callback, }; #ifdef CONFIG_GPIO_IMX_PORT_1 -static int imx_gpio_1_init(struct device *dev); +static int imx_gpio_1_init(struct device *port); static const struct imx_gpio_config imx_gpio_1_config = { .base = (GPIO_Type *)DT_GPIO_IMX_PORT_1_BASE_ADDRESS, @@ -194,7 +299,7 @@ DEVICE_AND_API_INIT(imx_gpio_1, DT_GPIO_IMX_PORT_1_NAME, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &imx_gpio_driver_api); -static int imx_gpio_1_init(struct device *dev) +static int imx_gpio_1_init(struct device *port) { IRQ_CONNECT(DT_GPIO_IMX_PORT_1_IRQ_0, DT_GPIO_IMX_PORT_1_IRQ_0_PRI, @@ -213,7 +318,7 @@ static int imx_gpio_1_init(struct device *dev) #endif /* CONFIG_GPIO_IMX_PORT_1 */ #ifdef CONFIG_GPIO_IMX_PORT_2 -static int imx_gpio_2_init(struct device *dev); +static int imx_gpio_2_init(struct device *port); static const struct imx_gpio_config imx_gpio_2_config = { .base = (GPIO_Type *)DT_GPIO_IMX_PORT_2_BASE_ADDRESS, @@ -227,7 +332,7 @@ DEVICE_AND_API_INIT(imx_gpio_2, DT_GPIO_IMX_PORT_2_NAME, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &imx_gpio_driver_api); -static int imx_gpio_2_init(struct device *dev) +static int imx_gpio_2_init(struct device *port) { IRQ_CONNECT(DT_GPIO_IMX_PORT_2_IRQ_0, DT_GPIO_IMX_PORT_2_IRQ_0_PRI, @@ -246,7 +351,7 @@ static int imx_gpio_2_init(struct device *dev) #endif /* CONFIG_GPIO_IMX_PORT_2 */ #ifdef CONFIG_GPIO_IMX_PORT_3 -static int imx_gpio_3_init(struct device *dev); +static int imx_gpio_3_init(struct device *port); static const struct imx_gpio_config imx_gpio_3_config = { .base = (GPIO_Type *)DT_GPIO_IMX_PORT_3_BASE_ADDRESS, @@ -260,7 +365,7 @@ DEVICE_AND_API_INIT(imx_gpio_3, DT_GPIO_IMX_PORT_3_NAME, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &imx_gpio_driver_api); -static int imx_gpio_3_init(struct device *dev) +static int imx_gpio_3_init(struct device *port) { IRQ_CONNECT(DT_GPIO_IMX_PORT_3_IRQ_0, DT_GPIO_IMX_PORT_3_IRQ_0_PRI, @@ -279,7 +384,7 @@ static int imx_gpio_3_init(struct device *dev) #endif /* CONFIG_GPIO_IMX_PORT_3 */ #ifdef CONFIG_GPIO_IMX_PORT_4 -static int imx_gpio_4_init(struct device *dev); +static int imx_gpio_4_init(struct device *port); static const struct imx_gpio_config imx_gpio_4_config = { .base = (GPIO_Type *)DT_GPIO_IMX_PORT_4_BASE_ADDRESS, @@ -293,7 +398,7 @@ DEVICE_AND_API_INIT(imx_gpio_4, DT_GPIO_IMX_PORT_4_NAME, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &imx_gpio_driver_api); -static int imx_gpio_4_init(struct device *dev) +static int imx_gpio_4_init(struct device *port) { IRQ_CONNECT(DT_GPIO_IMX_PORT_4_IRQ_0, DT_GPIO_IMX_PORT_4_IRQ_0_PRI, @@ -312,7 +417,7 @@ static int imx_gpio_4_init(struct device *dev) #endif /* CONFIG_GPIO_IMX_PORT_4 */ #ifdef CONFIG_GPIO_IMX_PORT_5 -static int imx_gpio_5_init(struct device *dev); +static int imx_gpio_5_init(struct device *port); static const struct imx_gpio_config imx_gpio_5_config = { .base = (GPIO_Type *)DT_GPIO_IMX_PORT_5_BASE_ADDRESS, @@ -326,7 +431,7 @@ DEVICE_AND_API_INIT(imx_gpio_5, DT_GPIO_IMX_PORT_5_NAME, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &imx_gpio_driver_api); -static int imx_gpio_5_init(struct device *dev) +static int imx_gpio_5_init(struct device *port) { IRQ_CONNECT(DT_GPIO_IMX_PORT_5_IRQ_0, DT_GPIO_IMX_PORT_5_IRQ_0_PRI, @@ -345,7 +450,7 @@ static int imx_gpio_5_init(struct device *dev) #endif /* CONFIG_GPIO_IMX_PORT_5 */ #ifdef CONFIG_GPIO_IMX_PORT_6 -static int imx_gpio_6_init(struct device *dev); +static int imx_gpio_6_init(struct device *port); static const struct imx_gpio_config imx_gpio_6_config = { .base = (GPIO_Type *)DT_GPIO_IMX_PORT_6_BASE_ADDRESS, @@ -359,7 +464,7 @@ DEVICE_AND_API_INIT(imx_gpio_6, DT_GPIO_IMX_PORT_6_NAME, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &imx_gpio_driver_api); -static int imx_gpio_6_init(struct device *dev) +static int imx_gpio_6_init(struct device *port) { IRQ_CONNECT(DT_GPIO_IMX_PORT_6_IRQ_0, DT_GPIO_IMX_PORT_6_IRQ_0_PRI, @@ -378,7 +483,7 @@ static int imx_gpio_6_init(struct device *dev) #endif /* CONFIG_GPIO_IMX_PORT_6 */ #ifdef CONFIG_GPIO_IMX_PORT_7 -static int imx_gpio_7_init(struct device *dev); +static int imx_gpio_7_init(struct device *port); static const struct imx_gpio_config imx_gpio_7_config = { .base = (GPIO_Type *)DT_GPIO_IMX_PORT_7_BASE_ADDRESS, @@ -392,7 +497,7 @@ DEVICE_AND_API_INIT(imx_gpio_7, DT_GPIO_IMX_PORT_7_NAME, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &imx_gpio_driver_api); -static int imx_gpio_7_init(struct device *dev) +static int imx_gpio_7_init(struct device *port) { IRQ_CONNECT(DT_GPIO_IMX_PORT_7_IRQ_0, DT_GPIO_IMX_PORT_7_IRQ_0_PRI, diff --git a/dts/arm/nxp/nxp_imx6sx_m4.dtsi b/dts/arm/nxp/nxp_imx6sx_m4.dtsi index b40e35bb1e3e7..f6c124660156d 100644 --- a/dts/arm/nxp/nxp_imx6sx_m4.dtsi +++ b/dts/arm/nxp/nxp_imx6sx_m4.dtsi @@ -201,7 +201,7 @@ gpio5:gpio@420ac000 { compatible = "nxp,imx-gpio"; reg = <0x420ac000 0x4000>; - interrupts = <74 0>, <74 0>; + interrupts = <74 0>, <75 0>; rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ RDC_DOMAIN_PERM_RW)|\ RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ diff --git a/tests/drivers/gpio/gpio_basic_api/boards/udoo_neo_full_m4.conf b/tests/drivers/gpio/gpio_basic_api/boards/udoo_neo_full_m4.conf new file mode 100644 index 0000000000000..c98d1787ece7f --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/udoo_neo_full_m4.conf @@ -0,0 +1 @@ +CONFIG_GPIO_IMX_PORT_5=y diff --git a/tests/drivers/gpio/gpio_basic_api/boards/udoo_neo_full_m4.overlay b/tests/drivers/gpio/gpio_basic_api/boards/udoo_neo_full_m4.overlay new file mode 100644 index 0000000000000..2472f98c4e92c --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/udoo_neo_full_m4.overlay @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2019 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + resources { + compatible = "test,gpio_basic_api"; + out-gpios = <&gpio5 14 0>; /* J4 pin 4 */ + in-gpios = <&gpio5 15 0>; /* J4 pin 3 */ + }; +}; diff --git a/tests/drivers/gpio/gpio_basic_api/src/main.c b/tests/drivers/gpio/gpio_basic_api/src/main.c index 8930f5a3b531f..ba499651784e0 100644 --- a/tests/drivers/gpio/gpio_basic_api/src/main.c +++ b/tests/drivers/gpio/gpio_basic_api/src/main.c @@ -11,6 +11,8 @@ #ifdef CONFIG_BOARD_FRDM_K64F #include #include +#elif defined(CONFIG_BOARD_UDOO_NEO_FULL_M4) +#include "device_imx.h" #endif static void board_setup(void) @@ -33,6 +35,48 @@ static void board_setup(void) pinmux_pin_set(pmx, PIN_OUT, PORT_PCR_MUX(kPORT_MuxAsGpio)); pinmux_pin_set(pmx, PIN_IN, PORT_PCR_MUX(kPORT_MuxAsGpio)); +#elif defined(CONFIG_BOARD_UDOO_NEO_FULL_M4) + /* + * Configure pin mux. + * The following code needs to configure the same GPIOs which were + * selected as test pins in device tree. + */ + + if (strcmp(DEV_NAME, "GPIO_5") != 0) { + printk("FATAL: controller set in DTS %s != controller %s\n", + DEV_NAME, "GPIO_5"); + k_panic(); + } + + if (PIN_IN != 15) { + printk("FATAL: input pin set in DTS %d != %d\n", PIN_IN, 15); + k_panic(); + } + + if (PIN_OUT != 14) { + printk("FATAL: output pin set in DTS %d != %d\n", PIN_OUT, 14); + k_panic(); + } + + /* Configure pin RGMII2_RD2 as GPIO5_IO14. */ + IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2 = + IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_MUX_MODE(5); + /* Select pull enabled, speed 100 MHz, drive strength 43 ohm */ + IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2 = + IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_DSE(6); + + /* Configure pin RGMII2_RD3 as GPIO5_IO15. */ + IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3 = + IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_MUX_MODE(5); + /* Select pull enabled, speed 100 MHz, drive strength 43 ohm */ + IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3 = + IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PKE_MASK | + IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_SPEED(2) | + IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_DSE(6); #endif }