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dts: arm: st: h7: Add support for STM32H742
Adds base Devicetree files for H742Xi/g variants Signed-off-by: Adam Mitchell <[email protected]>
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‎dts/arm/st/h7/stm32h742.dtsi‎

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/*
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* Copyright (c) 2025 Brill Power
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/h7/stm32h7.dtsi>
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#include <zephyr/dt-bindings/display/panel.h>
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/ {
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soc {
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compatible = "st,stm32h742", "st,stm32h7", "simple-bus";
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flash-controller@52002000 {
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flash0: flash@8000000 {
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compatible = "st,stm32-nv-flash", "soc-nv-flash";
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write-block-size = <32>;
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erase-block-size = <DT_SIZE_K(128)>;
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/* maximum erase time for a 128K sector */
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max-erase-time = <4000>;
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};
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};
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dmamux1: dmamux@40020800 {
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dma-requests= <107>;
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};
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dmamux2: dmamux@58025800 {
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dma-requests= <12>;
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};
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usbotg_fs: usb@40080000 {
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compatible = "st,stm32-otgfs";
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reg = <0x40080000 0x40000>;
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interrupts = <101 0>, <98 0>, <99 0>;
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interrupt-names = "otgfs", "ep1_out", "ep1_in";
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num-bidir-endpoints = <9>;
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ram-size = <4096>;
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maximum-speed = "full-speed";
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clocks = <&rcc STM32_CLOCK(AHB1, 27)>,
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<&rcc STM32_SRC_HSI48 USB_SEL(3)>;
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phys = <&otghs_fs_phy>;
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status = "disabled";
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};
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ltdc: display-controller@50001000 {
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compatible = "st,stm32-ltdc";
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reg = <0x50001000 0x200>;
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interrupts = <88 0>, <89 0>;
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interrupt-names = "ltdc", "ltdc_er";
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clocks = <&rcc STM32_CLOCK(APB3, 3)>;
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resets = <&rctl STM32_RESET(APB3, 3)>;
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status = "disabled";
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};
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rtc@58004000 {
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bbram: backup_regs {
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compatible = "st,stm32-bbram";
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st,backup-regs = <32>;
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status = "disabled";
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};
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};
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};
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/* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
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sram0: memory@24000000 {
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compatible = "mmio-sram";
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reg = <0x24000000 DT_SIZE_K(384)>;
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};
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/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
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sram1: memory@30000000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x30000000 DT_SIZE_K(32)>;
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zephyr,memory-region = "SRAM1";
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};
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/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
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sram2: memory@30020000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x30020000 DT_SIZE_K(16)>;
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zephyr,memory-region = "SRAM2";
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};
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/* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
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sram4: memory@38000000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x38000000 DT_SIZE_K(64)>;
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zephyr,memory-region = "SRAM4";
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};
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dtcm: memory@20000000 {
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compatible = "zephyr,memory-region", "arm,dtcm";
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reg = <0x20000000 DT_SIZE_K(128)>;
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zephyr,memory-region = "DTCM";
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};
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itcm: memory@0 {
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compatible = "zephyr,memory-region", "arm,itcm";
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reg = <0x00000000 DT_SIZE_K(64)>;
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zephyr,memory-region = "ITCM";
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};
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otghs_fs_phy: otghs_fs_phy {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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};
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vref: vref {
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io-channels = <&adc3 19>;
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};
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vbat: vbat {
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io-channels = <&adc3 17>;
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};
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};

‎dts/arm/st/h7/stm32h742Xg.dtsi‎

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/*
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* Copyright (c) 2025 Brill Power
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/h7/stm32h742.dtsi>
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/ {
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soc {
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flash-controller@52002000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(1024)>;
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};
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};
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};
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};

‎dts/arm/st/h7/stm32h742Xi.dtsi‎

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/*
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* Copyright (c) 2025 Brill Power
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/h7/stm32h742.dtsi>
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/ {
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soc {
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flash-controller@52002000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(2048)>;
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};
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};
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};
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};

‎dts/arm/st/h7/stm32h743.dtsi‎

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/*
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* Copyright (c) 2020 Teslabs Engineering S.L.
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* Copyright (c) 2025 Brill Power
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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7-
#include <st/h7/stm32h7.dtsi>
8-
#include <zephyr/dt-bindings/display/panel.h>
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#include <st/h7/stm32h742.dtsi>
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/ {
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soc {
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compatible = "st,stm32h743", "st,stm32h7", "simple-bus";
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flash-controller@52002000 {
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flash0: flash@8000000 {
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compatible = "st,stm32-nv-flash", "soc-nv-flash";
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write-block-size = <32>;
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erase-block-size = <DT_SIZE_K(128)>;
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/* maximum erase time for a 128K sector */
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max-erase-time = <4000>;
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};
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};
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dmamux1: dmamux@40020800 {
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dma-requests= <107>;
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};
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dmamux2: dmamux@58025800 {
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dma-requests= <12>;
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};
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usbotg_fs: usb@40080000 {
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compatible = "st,stm32-otgfs";
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reg = <0x40080000 0x40000>;
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interrupts = <98 0>, <99 0>, <100 0>, <101 0>;
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interrupt-names = "ep1_out", "ep1_in", "wkup", "otgfs";
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num-bidir-endpoints = <9>;
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ram-size = <4096>;
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maximum-speed = "full-speed";
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clocks = <&rcc STM32_CLOCK(AHB1, 27U)>,
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<&rcc STM32_SRC_HSI48 USB_SEL(3)>;
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phys = <&otghs_fs_phy>;
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status = "disabled";
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};
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ltdc: display-controller@50001000 {
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compatible = "st,stm32-ltdc";
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reg = <0x50001000 0x200>;
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interrupts = <88 0>, <89 0>;
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interrupt-names = "ltdc", "ltdc_er";
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clocks = <&rcc STM32_CLOCK(APB3, 3U)>;
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resets = <&rctl STM32_RESET(APB3, 3U)>;
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status = "disabled";
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};
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rtc@58004000 {
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bbram: backup_regs {
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compatible = "st,stm32-bbram";
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st,backup-regs = <32>;
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status = "disabled";
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};
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};
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};
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/* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
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sram0: memory@24000000 {
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reg = <0x24000000 DT_SIZE_K(512)>;
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compatible = "mmio-sram";
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};
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/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
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sram1: memory@30000000 {
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reg = <0x30000000 DT_SIZE_K(128)>;
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compatible = "zephyr,memory-region", "mmio-sram";
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zephyr,memory-region = "SRAM1";
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};
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/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
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sram2: memory@30020000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x30020000 DT_SIZE_K(128)>;
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zephyr,memory-region = "SRAM2";
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};
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/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
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reg = <0x30040000 DT_SIZE_K(32)>;
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zephyr,memory-region = "SRAM3";
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};
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/* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
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sram4: memory@38000000 {
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reg = <0x38000000 DT_SIZE_K(64)>;
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compatible = "zephyr,memory-region", "mmio-sram";
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zephyr,memory-region = "SRAM4";
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};
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dtcm: memory@20000000 {
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compatible = "zephyr,memory-region", "arm,dtcm";
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reg = <0x20000000 DT_SIZE_K(128)>;
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zephyr,memory-region = "DTCM";
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};
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itcm: memory@0 {
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compatible = "zephyr,memory-region", "arm,itcm";
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reg = <0x00000000 DT_SIZE_K(64)>;
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zephyr,memory-region = "ITCM";
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};
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otghs_fs_phy: otghs_fs_phy {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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};
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vref: vref {
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io-channels = <&adc3 19>;
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};
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vbat: vbat {
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io-channels = <&adc3 17>;
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};
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};

‎soc/st/stm32/stm32h7x/Kconfig‎

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# ST Microelectronics STM32H7 MCU series
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# Copyright (c) 2019 Linaro Limited
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# Copyright (c) 2025 Brill Power
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_STM32H7X
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config SOC_STM32H735XX
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select CPU_CORTEX_M7
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config SOC_STM32H742XX
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select CPU_CORTEX_M7
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config SOC_STM32H743XX
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select CPU_CORTEX_M7
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‎soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h742xx‎

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# ST STM32H742X MCU configuration options
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# Copyright (c) 2025 Brill Power
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# SPDX-License-Identifier: Apache-2.0
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if SOC_STM32H742XX
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config NUM_IRQS
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default 150
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endif # SOC_STM32H742XX

‎soc/st/stm32/stm32h7x/Kconfig.soc‎

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# Copyright (c) 2019 Linaro Limited
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# Copyright (c) 2020 Teslabs Engineering S.L.
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# Copyright (c) 2021 Electrolance Solutions
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# Copyright (c) 2025 Brill Power
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_STM32H7X
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bool
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select SOC_SERIES_STM32H7X
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config SOC_STM32H742XX
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bool
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select SOC_SERIES_STM32H7X
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config SOC_STM32H743XX
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bool
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select SOC_SERIES_STM32H7X
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default "stm32h730xx" if SOC_STM32H730XX
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default "stm32h730xxq" if SOC_STM32H730XXQ
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default "stm32h735xx" if SOC_STM32H735XX
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default "stm32h742xx" if SOC_STM32H742XX
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default "stm32h743xx" if SOC_STM32H743XX
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default "stm32h745xx" if SOC_STM32H745XX_M7 || SOC_STM32H745XX_M4
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default "stm32h747xx" if SOC_STM32H747XX_M7 || SOC_STM32H747XX_M4

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