|
550 | 550 | status = "disabled"; |
551 | 551 | }; |
552 | 552 |
|
553 | | - |
554 | 553 | gpdma1: dma@40020000 { |
555 | 554 | compatible = "st,stm32u5-dma"; |
556 | 555 | #dma-cells = <3>; |
|
583 | 582 | clocks = <&rcc STM32_CLOCK(APB2, 12)>, |
584 | 583 | <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>; |
585 | 584 | dmas = <&gpdma1 0 7 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | |
586 | | - STM32_DMA_PRIORITY_HIGH)>, |
| 585 | + STM32_DMA_PRIORITY_HIGH)>, |
587 | 586 | <&gpdma1 1 6 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | |
588 | | - STM32_DMA_PRIORITY_HIGH)>; |
| 587 | + STM32_DMA_PRIORITY_HIGH)>; |
589 | 588 | dma-names = "tx", "rx"; |
590 | 589 | interrupts = <55 3>; |
591 | 590 | status = "disabled"; |
|
599 | 598 | clocks = <&rcc STM32_CLOCK(APB1, 14)>, |
600 | 599 | <&rcc STM32_SRC_PLL1_Q SPI2_SEL(0)>; |
601 | 600 | dmas = <&gpdma1 2 9 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | |
602 | | - STM32_DMA_PRIORITY_HIGH)>, |
| 601 | + STM32_DMA_PRIORITY_HIGH)>, |
603 | 602 | <&gpdma1 3 8 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | |
604 | | - STM32_DMA_PRIORITY_HIGH)>; |
| 603 | + STM32_DMA_PRIORITY_HIGH)>; |
605 | 604 | dma-names = "tx", "rx"; |
606 | 605 | interrupts = <56 3>; |
607 | 606 | status = "disabled"; |
|
615 | 614 | clocks = <&rcc STM32_CLOCK(APB1, 15)>, |
616 | 615 | <&rcc STM32_SRC_PLL1_Q SPI3_SEL(0)>; |
617 | 616 | dmas = <&gpdma1 4 11 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | |
618 | | - STM32_DMA_PRIORITY_HIGH)>, |
| 617 | + STM32_DMA_PRIORITY_HIGH)>, |
619 | 618 | <&gpdma1 5 10 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | |
620 | | - STM32_DMA_PRIORITY_HIGH)>; |
| 619 | + STM32_DMA_PRIORITY_HIGH)>; |
621 | 620 | dma-names = "tx", "rx"; |
622 | 621 | interrupts = <57 3>; |
623 | 622 | status = "disabled"; |
|
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