@@ -56,9 +56,6 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
5656
5757static const struct device * eth_stm32_phy_dev = DEVICE_DT_GET (DT_INST_PHANDLE (0 , phy_handle ));
5858
59- #define ETH_STM32_AUTO_NEGOTIATION_ENABLE \
60- UTIL_NOT(DT_NODE_HAS_PROP(DT_INST_PHANDLE(0, phy_handle), fixed_link))
61-
6259#if DT_HAS_COMPAT_STATUS_OKAY (st_stm32h7_ethernet )
6360#define IS_ETH_DMATXDESC_OWN (dma_tx_desc ) (dma_tx_desc->DESC3 & \
6461 ETH_DMATXNDESCRF_OWN)
@@ -845,6 +842,65 @@ static void RISAF_Config(void)
845842}
846843#endif
847844
845+ #if defined(CONFIG_ETH_STM32_HAL_API_V1 )
846+ #define ETH_TIMEOUT_SWRESET 500000U
847+
848+ static int eth_stm32_init_v1_api (const struct device * dev )
849+ {
850+ struct eth_stm32_hal_dev_data * dev_data = dev -> data ;
851+ ETH_HandleTypeDef * heth = & dev_data -> heth ;
852+ uint32_t tmpreg1 = 0U ;
853+
854+ if (heth -> State == HAL_ETH_STATE_RESET ) {
855+ /* Allocate lock resource and initialize it */
856+ heth -> Lock = HAL_UNLOCKED ;
857+ }
858+
859+ /* Select MII or RMII Mode*/
860+ #ifdef SOC_SERIES_STM32F1X
861+ AFIO -> MAPR &= ~(AFIO_MAPR_MII_RMII_SEL );
862+ AFIO -> MAPR |= (uint32_t )heth -> Init .MediaInterface ;
863+ #else
864+ /* Enable SYSCFG Clock */
865+ __HAL_RCC_SYSCFG_CLK_ENABLE ();
866+
867+ /* Select MII or RMII Mode*/
868+ SYSCFG -> PMC &= ~(SYSCFG_PMC_MII_RMII_SEL );
869+ SYSCFG -> PMC |= (uint32_t )heth -> Init .MediaInterface ;
870+ #endif /* SOC_SERIES_STM32F1X */
871+
872+ /* Get the ETHERNET MACMIIAR value, this is responsible for mdio, so save it to restore it
873+ * later
874+ */
875+ tmpreg1 = (heth -> Instance )-> MACMIIAR ;
876+
877+ /* Ethernet Software reset */
878+ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
879+ /* After reset all the registers holds their respective reset values */
880+ (heth -> Instance )-> DMABMR |= ETH_DMABMR_SR ;
881+
882+ /* Wait for software reset */
883+ if (WAIT_FOR ((((heth -> Instance )-> DMABMR & ETH_DMABMR_SR ) == (uint32_t )RESET ),
884+ ETH_TIMEOUT_SWRESET , NULL ) == false) {
885+ heth -> State = HAL_ETH_STATE_TIMEOUT ;
886+ /* Process Unlocked */
887+ __HAL_UNLOCK (heth );
888+
889+ return - ETIMEDOUT ;
890+ }
891+
892+ (heth -> Instance )-> MACMIIAR = (uint32_t )tmpreg1 ;
893+
894+ /* Config MAC and DMA */
895+ ETH_MACDMAConfig (heth , ETH_SUCCESS );
896+
897+ /* Set ETH HAL State to Ready */
898+ heth -> State = HAL_ETH_STATE_READY ;
899+
900+ return HAL_OK ;
901+ }
902+ #endif /* CONFIG_ETH_STM32_HAL_API_V1 */
903+
848904static int eth_initialize (const struct device * dev )
849905{
850906 struct eth_stm32_hal_dev_data * dev_data = dev -> data ;
@@ -891,28 +947,10 @@ static int eth_initialize(const struct device *dev)
891947 heth -> Init .MACAddr = dev_data -> mac_addr ;
892948
893949#if defined(CONFIG_ETH_STM32_HAL_API_V1 )
894- HAL_StatusTypeDef hal_ret = HAL_OK ;
895-
896- if (!ETH_STM32_AUTO_NEGOTIATION_ENABLE ) {
897- struct phy_link_state state ;
898-
899- phy_get_link_state (eth_stm32_phy_dev , & state );
900-
901- heth -> Init .DuplexMode = PHY_LINK_IS_FULL_DUPLEX (state .speed ) ? ETH_MODE_FULLDUPLEX
902- : ETH_MODE_HALFDUPLEX ;
903- heth -> Init .Speed =
904- PHY_LINK_IS_SPEED_100M (state .speed ) ? ETH_SPEED_100M : ETH_SPEED_10M ;
905- }
906-
907- hal_ret = HAL_ETH_Init (heth );
908- if (hal_ret == HAL_TIMEOUT ) {
909- /* HAL Init time out. This could be linked to */
910- /* a recoverable error. Log the issue and continue */
911- /* driver initialisation */
912- LOG_WRN ("HAL_ETH_Init timed out (cable not connected?)" );
913- } else if (hal_ret != HAL_OK ) {
914- LOG_ERR ("HAL_ETH_Init failed: %d" , hal_ret );
915- return - EINVAL ;
950+ ret = eth_stm32_init_v1_api (dev );
951+ if (ret < 0 ) {
952+ LOG_ERR ("eth_init_v1_api failed: %d" , ret );
953+ return - EIO ;
916954 }
917955
918956 /* Initialize semaphores */
@@ -1395,9 +1433,6 @@ static struct eth_stm32_hal_dev_data eth0_data = {
13951433 .Instance = (ETH_TypeDef * )DT_REG_ADDR (DT_INST_PARENT (0 )),
13961434 .Init = {
13971435#if defined(CONFIG_ETH_STM32_HAL_API_V1 )
1398- .AutoNegotiation = ETH_STM32_AUTO_NEGOTIATION_ENABLE ?
1399- ETH_AUTONEGOTIATION_ENABLE : ETH_AUTONEGOTIATION_DISABLE ,
1400- .PhyAddress = DT_REG_ADDR (DT_INST_PHANDLE (0 , phy_handle )),
14011436 .RxMode = ETH_RXINTERRUPT_MODE ,
14021437 .ChecksumMode = IS_ENABLED (CONFIG_ETH_STM32_HW_CHECKSUM ) ?
14031438 ETH_CHECKSUM_BY_HARDWARE : ETH_CHECKSUM_BY_SOFTWARE ,
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