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dts: arm: st: mp13: stm32mp13 new series with cortex A7
Put the flash in DDR 0xC0000000 Put the SRAM in DDR 0xD0000000 Signed-off-by: Julien Racki <[email protected]>
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‎dts/arm/st/mp13/stm32mp13.dtsi‎

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/*
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* Copyright (c) 2025 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-a.dtsi>
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#include <freq.h>
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#include <mem.h>
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#include <zephyr/dt-bindings/clock/stm32mp13_clock.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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#include <zephyr/dt-bindings/reset/stm32mp13_reset.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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};
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soc {
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interrupt-parent = <&gic>;
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sysram: memory@2ffe0000 {
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compatible = "mmio-sram";
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reg = <0x2FFE0000 DT_SIZE_K(128)>;
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};
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uart4: serial@40010000 {
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compatible = "st,stm32-uart";
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reg = <0x40010000 0x400>;
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clocks = <&rcc STM32_CLOCK(APB1, 16)>;
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resets = <&rctl STM32_RESET(APB1, 16)>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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rcc: rcc@50000000 {
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compatible = "st,stm32-rcc";
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reg = <0x50000000 0x1000>;
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#clock-cells = <2>;
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rctl: reset-controller {
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compatible = "st,stm32-rcc-rctl";
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#reset-cells = <1>;
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set-bit-to-deassert;
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};
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};
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pinctrl: pin-controller@50002000 {
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compatible = "st,stm32-pinctrl";
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reg = <0x50002000 0x9000>;
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#address-cells = <1>;
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#size-cells = <1>;
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gpioa: gpio@50002000 {
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compatible = "st,stm32-gpio";
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reg = <0x50002000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK(AHB4, 0)>;
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};
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gpiob: gpio@50003000 {
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compatible = "st,stm32-gpio";
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reg = <0x50003000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK(AHB4, 1)>;
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};
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gpioc: gpio@50004000 {
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compatible = "st,stm32-gpio";
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reg = <0x50004000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK(AHB4, 2)>;
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};
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gpiod: gpio@50005000 {
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compatible = "st,stm32-gpio";
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reg = <0x50005000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK(AHB4, 3)>;
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};
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gpioe: gpio@50006000 {
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compatible = "st,stm32-gpio";
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reg = <0x50006000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK(AHB4, 4)>;
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};
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gpiof: gpio@50007000 {
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compatible = "st,stm32-gpio";
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reg = <0x50007000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK(AHB4, 5)>;
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};
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gpiog: gpio@50008000 {
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compatible = "st,stm32-gpio";
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reg = <0x50008000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK(AHB4, 6)>;
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};
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gpioh: gpio@50009000 {
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compatible = "st,stm32-gpio";
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reg = <0x50009000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK(AHB4, 7)>;
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};
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gpioi: gpio@5000a000 {
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compatible = "st,stm32-gpio";
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reg = <0x5000a000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK(AHB4, 8)>;
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};
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};
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exti: interrupt-controller@5000d000 {
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compatible = "st,stm32g0-exti","st,stm32-exti";
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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reg = <0x5000D000 0x400>;
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num-lines = <16>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 24 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 65 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 66 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 68 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 78 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "line0", "line1", "line2", "line3",
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"line4", "line5", "line6", "line7",
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"line8", "line9", "line10", "line11",
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"line12", "line13", "line14", "line15";
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line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
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<4 1>, <5 1>, <6 1>, <7 1>,
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<8 1>, <9 1>, <10 1>, <11 1>,
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<12 1>, <13 1>, <14 1>, <15 1>;
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};
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};
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gic: gic@A0021000 {
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compatible = "arm,gic-v2", "arm,gic";
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reg = <0xA0021000 0x1000>,
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<0xA0022000 0x2000>;
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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};
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ddr_code: memory@C0000000 {
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compatible = "mmio-sram";
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reg = <0xC0000000 0x10000000>;
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};
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ddr_data: memory@D0000000 {
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compatible = "mmio-sram";
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reg = <0xD0000000 0x10000000>;
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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status = "disabled";
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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status = "disabled";
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};
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cpusw: cpusw {
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#clock-cells = <0>;
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compatible = "st,stm32mp13-cpu-clock-mux";
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status = "disabled";
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};
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pll1: pll: pll {
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#clock-cells = <0>;
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compatible = "st,stm32mp13-pll-clock";
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status = "disabled";
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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};
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};

‎dts/arm/st/mp13/stm32mp135.dtsi‎

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/*
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* Copyright (c) 2025 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/mp13/stm32mp13.dtsi>
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/ {
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soc {
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compatible = "st,stm32mp135", "st,stm32mp13", "simple-bus";
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};
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};

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