@@ -431,60 +431,59 @@ static const struct ov2640_reg default_regs[] = {
431431};
432432
433433static const struct ov2640_reg uxga_regs [] = {
434- { BANK_SEL , BANK_SEL_SENSOR },
434+ {BANK_SEL , BANK_SEL_SENSOR },
435435 /* DSP input image resolution and window size control */
436- { COM7 , COM7_RES_UXGA },
437- { COM1 , 0x0F }, /* UXGA=0x0F, SVGA=0x0A, CIF=0x06 */
438- { REG32 , REG32_UXGA }, /* UXGA=0x36, SVGA/CIF=0x09 */
439-
440- { HSTART , 0x11 }, /* UXGA=0x11, SVGA/CIF=0x11 */
441- { HSTOP , 0x75 }, /* UXGA=0x75, SVGA/CIF=0x43 */
442-
443- { VSTART , 0x01 }, /* UXGA=0x01, SVGA/CIF=0x00 */
444- { VSTOP , 0x97 }, /* UXGA=0x97, SVGA/CIF=0x4b */
445- { 0x3d , 0x34 }, /* UXGA=0x34, SVGA/CIF=0x38 */
446-
447- { 0x35 , 0x88 },
448- { 0x22 , 0x0a },
449- { 0x37 , 0x40 },
450- { 0x34 , 0xa0 },
451- { 0x06 , 0x02 },
452- { 0x0d , 0xb7 },
453- { 0x0e , 0x01 },
454- { 0x42 , 0x83 },
436+ {COM7 , COM7_RES_UXGA },
437+ {COM1 , 0x0F }, /* UXGA=0x0F, SVGA=0x0A, CIF=0x06 */
438+ {REG32 , REG32_UXGA }, /* UXGA=0x36, SVGA/CIF=0x09 */
439+
440+ {HSTART , 0x11 }, /* UXGA=0x11, SVGA/CIF=0x11 */
441+ {HSTOP , 0x75 }, /* UXGA=0x75, SVGA/CIF=0x43 */
442+
443+ {VSTART , 0x01 }, /* UXGA=0x01, SVGA/CIF=0x00 */
444+ {VSTOP , 0x97 }, /* UXGA=0x97, SVGA/CIF=0x4b */
445+ {0x3d , 0x34 }, /* UXGA=0x34, SVGA/CIF=0x38 */
446+
447+ {0x35 , 0x88 },
448+ {0x22 , 0x0a },
449+ {0x37 , 0x40 },
450+ {0x34 , 0xa0 },
451+ {0x06 , 0x02 },
452+ {0x0d , 0xb7 },
453+ {0x0e , 0x01 },
454+ {0x42 , 0x83 },
455455
456456 /*
457457 * Set DSP input image size and offset.
458458 * The sensor output image can be scaled with OUTW/OUTH
459459 */
460- { BANK_SEL , BANK_SEL_DSP },
461- { R_BYPASS , R_BYPASS_DSP_BYPAS },
460+ {BANK_SEL , BANK_SEL_DSP },
461+ {R_BYPASS , R_BYPASS_DSP_BYPAS },
462462
463- { RESET , RESET_DVP },
463+ {RESET , RESET_DVP },
464464 {HSIZE8 , (UXGA_WIDTH >> 3 )}, /* Image Horizontal Size HSIZE[10:3] */
465465 {VSIZE8 , (UXGA_HEIGHT >> 3 )}, /* Image Vertical Size VSIZE[10:3] */
466466
467467 /* {HSIZE[11], HSIZE[2:0], VSIZE[2:0]} */
468468 {SIZEL , ((UXGA_WIDTH >> 6 ) & 0x40 ) | ((UXGA_WIDTH & 0x7 ) << 3 ) | (UXGA_HEIGHT & 0x7 )},
469469
470- { XOFFL , 0x00 }, /* OFFSET_X[7:0] */
471- { YOFFL , 0x00 }, /* OFFSET_Y[7:0] */
470+ {XOFFL , 0x00 }, /* OFFSET_X[7:0] */
471+ {YOFFL , 0x00 }, /* OFFSET_Y[7:0] */
472472 {HSIZE , ((UXGA_WIDTH >> 2 ) & 0xFF )}, /* H_SIZE[7:0] real/4 */
473473 {VSIZE , ((UXGA_HEIGHT >> 2 ) & 0xFF )}, /* V_SIZE[7:0] real/4 */
474474
475475 /* V_SIZE[8]/OFFSET_Y[10:8]/H_SIZE[8]/OFFSET_X[10:8] */
476476 {VHYX , ((UXGA_HEIGHT >> 3 ) & 0x80 ) | ((UXGA_WIDTH >> 7 ) & 0x08 )},
477477 {TEST , (UXGA_WIDTH >> 4 ) & 0x80 }, /* H_SIZE[9] */
478478
479- { CTRL2 , CTRL2_DCW_EN | CTRL2_SDE_EN |
480- CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN },
479+ {CTRL2 , CTRL2_DCW_EN | CTRL2_SDE_EN | CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN },
481480
482481 /* H_DIVIDER/V_DIVIDER */
483- { CTRLI , CTRLI_LP_DP | 0x00 },
482+ {CTRLI , CTRLI_LP_DP | 0x00 },
484483 /* DVP prescaler */
485- { R_DVP_SP , R_DVP_SP_AUTO_MODE | 0x04 },
484+ {R_DVP_SP , R_DVP_SP_AUTO_MODE | 0x04 },
486485
487- { R_BYPASS , R_BYPASS_DSP_EN },
486+ {R_BYPASS , R_BYPASS_DSP_EN },
488487 {0 , 0 },
489488};
490489
@@ -872,8 +871,7 @@ static const struct ov2640_win_size *ov2640_select_win(uint32_t width, uint32_t
872871 return NULL ;
873872}
874873
875- static int ov2640_set_resolution (const struct device * dev ,
876- uint16_t img_width , uint16_t img_height )
874+ static int ov2640_set_resolution (const struct device * dev , uint16_t img_width , uint16_t img_height )
877875{
878876 int ret = 0 ;
879877 const struct ov2640_config * cfg = dev -> config ;
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