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slpp95prashanthnashif
slpp95prashanth
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nashif
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drivers: timer: Add TI DM TIMER support
TI Dual-Mode timer is used as the arch timer for systick on J721E R5 cores. Add DM Timer for systick timer support. Signed-off-by: Prashanth S <[email protected]> Signed-off-by: Andrew Davis <[email protected]>
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‎drivers/timer/CMakeLists.txt‎

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@@ -32,6 +32,7 @@ zephyr_library_sources_ifdef(CONFIG_RISCV_MACHINE_TIMER riscv_machine_timer.c)
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zephyr_library_sources_ifdef(CONFIG_RV32M1_LPTMR_TIMER rv32m1_lptmr_timer.c)
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zephyr_library_sources_ifdef(CONFIG_SAM0_RTC_TIMER sam0_rtc_timer.c)
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zephyr_library_sources_ifdef(CONFIG_STM32_LPTIM_TIMER stm32_lptim_timer.c)
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zephyr_library_sources_ifdef(CONFIG_TI_DM_TIMER ti_dmtimer.c)
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zephyr_library_sources_ifdef(CONFIG_XLNX_PSTTC_TIMER xlnx_psttc_timer.c)
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zephyr_library_sources_ifdef(CONFIG_XTENSA_TIMER xtensa_sys_timer.c)
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zephyr_library_sources_ifdef(CONFIG_SMARTBOND_TIMER smartbond_timer.c)

‎drivers/timer/Kconfig‎

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@@ -92,6 +92,7 @@ source "drivers/timer/Kconfig.rv32m1_lptmr"
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source "drivers/timer/Kconfig.sam0_rtc"
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source "drivers/timer/Kconfig.smartbond"
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source "drivers/timer/Kconfig.stm32_lptim"
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source "drivers/timer/Kconfig.ti_dm_timer"
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source "drivers/timer/Kconfig.xlnx_psttc"
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source "drivers/timer/Kconfig.xtensa"
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source "drivers/timer/Kconfig.mtk_adsp"

‎drivers/timer/Kconfig.ti_dm_timer‎

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# Copyright (C) 2023 BeagleBoard.org Foundation
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# Copyright (C) 2023 S Prashanth
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#
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# SPDX-License-Identifier: Apache-2.0
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config TI_DM_TIMER
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bool "TI Dual-Mode Timer"
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default y
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depends on DT_HAS_TI_AM654_TIMER_ENABLED
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select TICKLESS_CAPABLE
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help
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This module implements a kernel device driver for TI Dual-Mode timer. This
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driver provides system tick interface.

‎drivers/timer/ti_dmtimer.c‎

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/* Copyright (C) 2023 BeagleBoard.org Foundation
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* Copyright (C) 2023 S Prashanth
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* Copyright (c) 2024 Texas Instruments Incorporated
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* Andrew Davis <[email protected]>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/device.h>
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#include <zephyr/drivers/timer/system_timer.h>
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#include <zephyr/irq.h>
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#include <zephyr/sys_clock.h>
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#include <zephyr/kernel.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/drivers/timer/ti_dmtimer.h>
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#define DT_DRV_COMPAT ti_am654_timer
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#define TIMER_BASE_ADDR DT_INST_REG_ADDR(0)
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#define TIMER_IRQ_NUM DT_INST_IRQN(0)
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#define TIMER_IRQ_PRIO DT_INST_IRQ(0, priority)
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#define TIMER_IRQ_FLAGS DT_INST_IRQ(0, flags)
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#define CYC_PER_TICK ((uint32_t)(sys_clock_hw_cycles_per_sec() \
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/ CONFIG_SYS_CLOCK_TICKS_PER_SEC))
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#define MAX_TICKS ((k_ticks_t)(UINT32_MAX / CYC_PER_TICK) - 1)
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static struct k_spinlock lock;
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static uint32_t last_cycle;
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#define TI_DM_TIMER_READ(reg) sys_read32(TIMER_BASE_ADDR + TI_DM_TIMER_ ## reg)
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#define TI_DM_TIMER_MASK(reg) TI_DM_TIMER_ ## reg ## _MASK
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#define TI_DM_TIMER_SHIFT(reg) TI_DM_TIMER_ ## reg ## _SHIFT
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#define TI_DM_TIMER_WRITE(data, reg, bits) \
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ti_dm_timer_write_masks(data, \
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TIMER_BASE_ADDR + TI_DM_TIMER_ ## reg, \
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TI_DM_TIMER_MASK(reg ## _ ## bits), \
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TI_DM_TIMER_SHIFT(reg ## _ ## bits))
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static void ti_dm_timer_write_masks(uint32_t data, uint32_t reg, uint32_t mask, uint32_t shift)
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{
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uint32_t reg_val;
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reg_val = sys_read32(reg);
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reg_val = (reg_val & ~(mask)) | (data << shift);
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sys_write32(reg_val, reg);
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}
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static void ti_dmtimer_isr(void *data)
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{
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/* If no pending event */
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if (!TI_DM_TIMER_READ(IRQSTATUS))
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return;
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint32_t curr_cycle = TI_DM_TIMER_READ(TCRR);
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uint32_t delta_cycles = curr_cycle - last_cycle;
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uint32_t delta_ticks = delta_cycles / CYC_PER_TICK;
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last_cycle = curr_cycle;
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/* ACK match interrupt */
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TI_DM_TIMER_WRITE(1, IRQSTATUS, MAT_IT_FLAG);
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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/* Setup next match time */
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uint64_t next_cycle = curr_cycle + CYC_PER_TICK;
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TI_DM_TIMER_WRITE(next_cycle, TMAR, COMPARE_VALUE);
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}
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k_spin_unlock(&lock, key);
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sys_clock_announce(delta_ticks);
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}
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void sys_clock_set_timeout(int32_t ticks, bool idle)
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{
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ARG_UNUSED(idle);
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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/* Not supported on tickful kernels */
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return;
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}
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ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
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ticks = CLAMP(ticks, 1, (int32_t)MAX_TICKS);
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k_spinlock_key_t key = k_spin_lock(&lock);
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/* Setup next match time */
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uint32_t curr_cycle = TI_DM_TIMER_READ(TCRR);
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uint32_t next_cycle = curr_cycle + (ticks * CYC_PER_TICK);
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TI_DM_TIMER_WRITE(next_cycle, TMAR, COMPARE_VALUE);
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k_spin_unlock(&lock, key);
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}
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uint32_t sys_clock_cycle_get_32(void)
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{
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint32_t curr_cycle = TI_DM_TIMER_READ(TCRR);
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k_spin_unlock(&lock, key);
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return curr_cycle;
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}
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unsigned int sys_clock_elapsed(void)
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{
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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/* Always return 0 for tickful kernel system */
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return 0;
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}
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint32_t curr_cycle = TI_DM_TIMER_READ(TCRR);
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uint32_t delta_cycles = curr_cycle - last_cycle;
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uint32_t delta_ticks = delta_cycles / CYC_PER_TICK;
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k_spin_unlock(&lock, key);
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return delta_ticks;
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}
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static int sys_clock_driver_init(void)
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{
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last_cycle = 0;
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IRQ_CONNECT(TIMER_IRQ_NUM, TIMER_IRQ_PRIO, ti_dmtimer_isr, NULL, TIMER_IRQ_FLAGS);
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/* Select autoreload mode */
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TI_DM_TIMER_WRITE(1, TCLR, AR);
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/* Enable match interrupt */
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TI_DM_TIMER_WRITE(1, IRQENABLE_SET, MAT_EN_FLAG);
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/* Load timer counter value */
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TI_DM_TIMER_WRITE(0, TCRR, TIMER_COUNTER);
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/* Load timer load value */
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TI_DM_TIMER_WRITE(0, TLDR, LOAD_VALUE);
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/* Load timer compare value */
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TI_DM_TIMER_WRITE(CYC_PER_TICK, TMAR, COMPARE_VALUE);
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/* Enable compare mode */
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TI_DM_TIMER_WRITE(1, TCLR, CE);
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/* Start the timer */
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TI_DM_TIMER_WRITE(1, TCLR, ST);
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irq_enable(TIMER_IRQ_NUM);
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return 0;
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}
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SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
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CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);

‎dts/bindings/timer/ti,am654-dmtimer.yaml‎

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# Copyright (C) 2023 BeagleBoard.org Foundation
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# Copyright (C) 2023 S Prashanth
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# SPDX-License-Identifier: Apache-2.0
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description: TI Dual-Mode Timer
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compatible: "ti,am654-timer"
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include: base.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true

‎include/zephyr/drivers/timer/ti_dmtimer.h‎

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/* Copyright (C) 2023 BeagleBoard.org Foundation
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* Copyright (C) 2023 S Prashanth
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_TIMERS_TI_DMTIMER_H_
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#define ZEPHYR_DRIVERS_TIMERS_TI_DMTIMER_H_
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#include <zephyr/devicetree.h>
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#define TI_DM_TIMER_TIDR (0x00)
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#define TI_DM_TIMER_TIOCP_CFG (0x10)
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#define TI_DM_TIMER_IRQ_EOI (0x20)
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#define TI_DM_TIMER_IRQSTATUS_RAW (0x24)
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#define TI_DM_TIMER_IRQSTATUS (0x28) /* Interrupt status register */
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#define TI_DM_TIMER_IRQENABLE_SET (0x2c) /* Interrupt enable register */
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#define TI_DM_TIMER_IRQENABLE_CLR (0x30) /* Interrupt disable register */
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#define TI_DM_TIMER_IRQWAKEEN (0x34)
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#define TI_DM_TIMER_TCLR (0x38) /* Control register */
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#define TI_DM_TIMER_TCRR (0x3c) /* Counter register */
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#define TI_DM_TIMER_TLDR (0x40) /* Load register */
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#define TI_DM_TIMER_TTGR (0x44)
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#define TI_DM_TIMER_TWPS (0x48)
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#define TI_DM_TIMER_TMAR (0x4c) /* Match register */
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#define TI_DM_TIMER_TCAR1 (0x50)
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#define TI_DM_TIMER_TSICR (0x54)
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#define TI_DM_TIMER_TCAR2 (0x58)
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#define TI_DM_TIMER_TPIR (0x5c)
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#define TI_DM_TIMER_TNIR (0x60)
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#define TI_DM_TIMER_TCVR (0x64)
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#define TI_DM_TIMER_TOCR (0x68)
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#define TI_DM_TIMER_TOWR (0x6c)
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#define TI_DM_TIMER_IRQSTATUS_MAT_IT_FLAG_SHIFT (0)
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#define TI_DM_TIMER_IRQSTATUS_MAT_IT_FLAG_MASK (0x00000001)
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#define TI_DM_TIMER_IRQSTATUS_OVF_IT_FLAG_SHIFT (1)
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#define TI_DM_TIMER_IRQSTATUS_OVF_IT_FLAG_MASK (0x00000002)
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#define TI_DM_TIMER_IRQSTATUS_TCAR_IT_FLAG_SHIFT (2)
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#define TI_DM_TIMER_IRQSTATUS_TCAR_IT_FLAG_MASK (0x00000004)
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#define TI_DM_TIMER_IRQENABLE_SET_MAT_EN_FLAG_SHIFT (0)
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#define TI_DM_TIMER_IRQENABLE_SET_MAT_EN_FLAG_MASK (0x00000001)
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#define TI_DM_TIMER_IRQENABLE_SET_OVF_EN_FLAG_SHIFT (1)
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#define TI_DM_TIMER_IRQENABLE_SET_OVF_EN_FLAG_MASK (0x00000002)
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#define TI_DM_TIMER_IRQENABLE_SET_TCAR_EN_FLAG_SHIFT (2)
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#define TI_DM_TIMER_IRQENABLE_SET_TCAR_EN_FLAG_MASK (0x00000004)
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#define TI_DM_TIMER_IRQENABLE_CLR_MAT_EN_FLAG_SHIFT (0)
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#define TI_DM_TIMER_IRQENABLE_CLR_MAT_EN_FLAG_MASK (0x00000001)
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#define TI_DM_TIMER_IRQENABLE_CLR_OVF_EN_FLAG_SHIFT (1)
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#define TI_DM_TIMER_IRQENABLE_CLR_OVF_EN_FLAG_MASK (0x00000002)
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#define TI_DM_TIMER_IRQENABLE_CLR_TCAR_EN_FLAG_SHIFT (2)
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#define TI_DM_TIMER_IRQENABLE_CLR_TCAR_EN_FLAG_MASK (0x00000004)
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#define TI_DM_TIMER_TCLR_ST_SHIFT (0)
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#define TI_DM_TIMER_TCLR_ST_MASK (0x00000001)
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#define TI_DM_TIMER_TCLR_AR_SHIFT (1)
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#define TI_DM_TIMER_TCLR_AR_MASK (0x00000002)
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#define TI_DM_TIMER_TCLR_PTV_SHIFT (2)
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#define TI_DM_TIMER_TCLR_PTV_MASK (0x0000001c)
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#define TI_DM_TIMER_TCLR_PRE_SHIFT (5)
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#define TI_DM_TIMER_TCLR_PRE_MASK (0x00000020)
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#define TI_DM_TIMER_TCLR_CE_SHIFT (6)
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#define TI_DM_TIMER_TCLR_CE_MASK (0x00000040)
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#define TI_DM_TIMER_TCLR_SCPWM_SHIFT (7)
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#define TI_DM_TIMER_TCLR_SCPWM_MASK (0x00000080)
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#define TI_DM_TIMER_TCLR_TCM_SHIFT (8)
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#define TI_DM_TIMER_TCLR_TCM_MASK (0x00000300)
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#define TI_DM_TIMER_TCLR_TRG_SHIFT (10)
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#define TI_DM_TIMER_TCLR_TRG_MASK (0x00000c00)
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#define TI_DM_TIMER_TCLR_PT_SHIFT (12)
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#define TI_DM_TIMER_TCLR_PT_MASK (0x00001000)
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#define TI_DM_TIMER_TCLR_CAPT_MODE_SHIFT (13)
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#define TI_DM_TIMER_TCLR_CAPT_MODE_MASK (0x00002000)
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#define TI_DM_TIMER_TCLR_GPO_CFG_SHIFT (14)
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#define TI_DM_TIMER_TCLR_GPO_CFG_MASK (0x00004000)
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#define TI_DM_TIMER_TCRR_TIMER_COUNTER_SHIFT (0)
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#define TI_DM_TIMER_TCRR_TIMER_COUNTER_MASK (0xffffffff)
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#define TI_DM_TIMER_TLDR_LOAD_VALUE_SHIFT (0)
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#define TI_DM_TIMER_TLDR_LOAD_VALUE_MASK (0xffffffff)
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#define TI_DM_TIMER_TMAR_COMPARE_VALUE_SHIFT (0)
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#define TI_DM_TIMER_TMAR_COMPARE_VALUE_MASK (0xffffffff)
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#endif /* ZEPHYR_DRIVERS_TIMERS_TI_DMTIMER_H_ */

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