tests: riscv: Add uint test for PMP memattr configuration

fsammoura1980 · fsammoura1980 · commit 278fa1550cc8 · 2025-10-22T20:24:53.000Z
Introduce a new test suite to validate the RISC-V Physical Memory
Protection (PMP) settings configured via the Zephyr Device Tree
'zephyr,memory-attr' property.

The test case `test_pmp_devicetree_memattr_config` reads the actual
PMP configuration (pmpcfg) and address (pmpaddr) Control and Status
Registers (CSRs) using the helper functions `z_riscv_pmp_read_config`
and `z_riscv_pmp_read_addr`.

It then compares the first three PMP entries against a set of
hardcoded expected values. These expected values are derived from
the memory regions defined with `zephyr,memory-attr` in the Device
Tree for the specific board or test setup. This ensures that the
PMP hardware is programmed correctly based on the Device Tree
definitions.

Signed-off-by: Firas Sammoura &lt;fsammoura@google.com&gt;
diff --git a/arch/riscv/core/pmp.c b/arch/riscv/core/pmp.c
@@ -113,7 +113,8 @@ static void print_pmp_entries(unsigned int pmp_start, unsigned int pmp_end,
  * @param pmp_cfg Pointer to the array where the CSR contents will be stored.
  * @param pmp_cfg_size The size of the pmp_cfg array, measured in unsigned long entries.
  */
-static inline void z_riscv_pmp_read_config(unsigned long *pmp_cfg, size_t pmp_cfg_size)
+IF_DISABLED(CONFIG_ZTEST, (static inline)) void z_riscv_pmp_read_config(unsigned long *pmp_cfg,
+								      size_t pmp_cfg_size)
 {
 	__ASSERT(pmp_cfg_size == (size_t)(CONFIG_PMP_SLOTS / PMPCFG_STRIDE),
 		 "Invalid PMP config array size");
@@ -179,7 +180,8 @@ static inline void z_riscv_pmp_write_config(unsigned long *pmp_cfg, size_t pmp_c
  * @param pmp_addr Pointer to the array where the CSR contents will be stored.
  * @param pmp_addr_size The size of the pmp_addr array, measured in unsigned long entries.
  */
-static inline void z_riscv_pmp_read_addr(unsigned long *pmp_addr, size_t pmp_addr_size)
+IF_DISABLED(CONFIG_ZTEST, (static inline)) void z_riscv_pmp_read_addr(unsigned long *pmp_addr,
+								    size_t pmp_addr_size)
 {
 	__ASSERT(pmp_addr_size == (size_t)(CONFIG_PMP_SLOTS), "PMP address array size mismatch");
 
diff --git a/tests/arch/riscv/pmp/mem-attr-entries/CMakeLists.txt b/tests/arch/riscv/pmp/mem-attr-entries/CMakeLists.txt
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(riscv_pmp)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
+
+target_include_directories(app PRIVATE
+  ${ZEPHYR_BASE}/kernel/include
+  ${ZEPHYR_BASE}/arch/${ARCH}/include
+  )
diff --git a/tests/arch/riscv/pmp/mem-attr-entries/memattr_mapping.overlay b/tests/arch/riscv/pmp/mem-attr-entries/memattr_mapping.overlay
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025 Google LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/memory-attr/memory-attr-riscv.h>
+
+/ {
+	memattr_region1: memattr_region1@80000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x80000000 0x20000>;
+		zephyr,memory-region = "MEMATTR_REGION1";
+		zephyr,memory-attr = <(DT_MEM_RISCV_TYPE_IO_R | \
+			DT_MEM_RISCV_TYPE_IO_W | DT_MEM_RISCV_TYPE_IO_X)>;
+	};
+
+	memattr_region2: memattr_region2@80000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x80000000 0x30000>;
+		zephyr,memory-region = "MEMATTR_REGION2";
+		zephyr,memory-attr = <(DT_MEM_RISCV_TYPE_IO_R | \
+			DT_MEM_RISCV_TYPE_IO_W | DT_MEM_RISCV_TYPE_IO_X)>;
+	};
+};
diff --git a/tests/arch/riscv/pmp/mem-attr-entries/prj.conf b/tests/arch/riscv/pmp/mem-attr-entries/prj.conf
@@ -0,0 +1,3 @@
+CONFIG_ZTEST=y
+CONFIG_MULTITHREADING=y
+CONFIG_MEM_ATTR=y
diff --git a/tests/arch/riscv/pmp/mem-attr-entries/src/main.c b/tests/arch/riscv/pmp/mem-attr-entries/src/main.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2025 Google LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <kernel_internal.h>
+#include <zephyr/mem_mgmt/mem_attr.h>
+#include <zephyr/tc_util.h>
+#include <zephyr/ztest.h>
+
+void z_riscv_pmp_read_config(unsigned long *pmp_cfg, size_t pmp_cfg_size);
+void z_riscv_pmp_read_addr(unsigned long *pmp_addr, size_t pmp_addr_size);
+
+/**
+ * @brief Verifies the RISC-V PMP entries configured via Device Tree (zephyr,memattr).
+ *
+ * @details Reads the PMP configuration (pmpcfg) and address (pmpaddr) registers
+ * and asserts that the entries programmed by the CONFIG_MEM_ATTR process match
+ * the expected values for the Device Tree-defined memory regions.
+ */
+ZTEST(riscv_pmp_memattr_entries, test_pmp_devicetree_memattr_config)
+{
+	const size_t num_pmpcfg_regs = CONFIG_PMP_SLOTS / sizeof(unsigned long);
+	const size_t num_pmpaddr_regs = CONFIG_PMP_SLOTS;
+
+	unsigned long current_pmpcfg_regs[num_pmpcfg_regs];
+	unsigned long current_pmpaddr_regs[num_pmpaddr_regs];
+
+	/* Read the current PMP configuration from the control registers */
+	z_riscv_pmp_read_config(current_pmpcfg_regs, num_pmpcfg_regs);
+	z_riscv_pmp_read_addr(current_pmpaddr_regs, num_pmpaddr_regs);
+
+	const uint8_t *const current_pmp_cfg_entries = (const uint8_t *)current_pmpcfg_regs;
+
+	const unsigned long expected_pmp_addr[3] = {0x20003fff, 0x20000000, 0x2000c000};
+	const uint8_t expected_pmp_cfg_entries[3] = {0x1f, 0x00, 0x0f};
+
+	size_t found_idx = -1;
+	bool found_sequence = false;
+	const size_t expected_len = ARRAY_SIZE(expected_pmp_addr);
+
+	for (size_t i = 0; i <= CONFIG_PMP_SLOTS - expected_len; ++i) {
+		if (memcmp(&current_pmpaddr_regs[i], expected_pmp_addr,
+			   expected_len * sizeof(unsigned long)) == 0) {
+
+			if (memcmp(&current_pmp_cfg_entries[i], expected_pmp_cfg_entries,
+				   expected_len * sizeof(uint8_t)) == 0) {
+				found_sequence = true;
+				found_idx = i;
+				break;
+			}
+		}
+	}
+
+	zassert_true(found_sequence,
+		     "Expected PMP sequence (Addrs: 0x%lx, Cfg: 0x%x, ...) was not found in any "
+		     "slot. Last checked slot: %zu",
+		     expected_pmp_addr[0], expected_pmp_cfg_entries[0], found_idx);
+}
+
+ZTEST(riscv_pmp_memattr_entries, test_dt_pmp_perm_conversion)
+{
+	uint8_t result;
+
+	result = DT_MEM_RISCV_TO_PMP_PERM(0);
+	zassert_equal(result, 0, "Expected 0, got 0x%x", result);
+
+	result = DT_MEM_RISCV_TO_PMP_PERM(DT_MEM_RISCV_TYPE_IO_R);
+	zassert_equal(result, PMP_R, "Expected PMP_R (0x%x), got 0x%x", PMP_R, result);
+
+	result = DT_MEM_RISCV_TO_PMP_PERM(DT_MEM_RISCV_TYPE_IO_W);
+	zassert_equal(result, PMP_W, "Expected PMP_W (0x%x), got 0x%x", PMP_W, result);
+
+	result = DT_MEM_RISCV_TO_PMP_PERM(DT_MEM_RISCV_TYPE_IO_X);
+	zassert_equal(result, PMP_X, "Expected PMP_X (0x%x), got 0x%x", PMP_X, result);
+
+	result = DT_MEM_RISCV_TO_PMP_PERM(DT_MEM_RISCV_TYPE_IO_R | DT_MEM_RISCV_TYPE_IO_W);
+	zassert_equal(result, PMP_R | PMP_W, "Expected R|W (0x%x), got 0x%x", PMP_R | PMP_W,
+		      result);
+
+	result = DT_MEM_RISCV_TO_PMP_PERM(DT_MEM_RISCV_TYPE_IO_R | DT_MEM_RISCV_TYPE_IO_W |
+					  DT_MEM_RISCV_TYPE_IO_X);
+	zassert_equal(result, PMP_R | PMP_W | PMP_X, "Expected R|W|X (0x%x), got 0x%x",
+		      PMP_R | PMP_W | PMP_X, result);
+}
+
+ZTEST_SUITE(riscv_pmp_memattr_entries, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/arch/riscv/pmp/mem-attr-entries/testcase.yaml b/tests/arch/riscv/pmp/mem-attr-entries/testcase.yaml
@@ -0,0 +1,11 @@
+common:
+  platform_allow:
+    - qemu_riscv32
+    - qemu_riscv32e
+    - qemu_riscv64
+  filter: CONFIG_RISCV_PMP
+
+tests:
+  arch.riscv.pmp.memattr.entries:
+    extra_args:
+      DTC_OVERLAY_FILE="memattr_mapping.overlay"

Original file line number	Diff line number	Diff line change
`@@ -0,0 +1,3 @@`
	`1`	`+CONFIG_ZTEST=y`
	`2`	`+CONFIG_MULTITHREADING=y`
	`3`	`+CONFIG_MEM_ATTR=y`