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Vincenzo Frascinogalak
Vincenzo Frascino
authored and
galak
committed
dts: mps2_an385: Initial device tree support
This patch adds the intial device tree support to V2M MPS2 AN385 platform. Signed-off-by: Vincenzo Frascino <[email protected]>
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6 files changed

+109
-21
lines changed

6 files changed

+109
-21
lines changed

‎arch/arm/soc/arm/mps2/Kconfig.defconfig.series‎

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -9,26 +9,10 @@ if SOC_SERIES_MPS2
99
config SOC_SERIES
1010
default mps2
1111

12-
config NUM_IRQ_PRIO_BITS
13-
int
14-
default 3
15-
1612
config SYS_CLOCK_HW_CYCLES_PER_SEC
1713
int
1814
default 25000000
1915

20-
config SRAM_BASE_ADDRESS
21-
default 0x20000000
22-
23-
config SRAM_SIZE
24-
default 4096
25-
26-
config FLASH_BASE_ADDRESS
27-
default 0x00000000
28-
29-
config FLASH_SIZE
30-
default 4096
31-
3216
source "arch/arm/soc/arm/mps2/Kconfig.defconfig.mps2*"
3317

3418
endif # SOC_SERIES_MPS2

‎arch/arm/soc/arm/mps2/soc_devices.h‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -25,20 +25,22 @@
2525
#if defined(CONFIG_UART_CMSDK_APB)
2626
/* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */
2727
#define CMSDK_APB_UART0 UART_0_BASE_ADDR
28+
#define CMSDK_APB_UART1 UART_1_BASE_ADDR
29+
#define CMSDK_APB_UART2 UART_2_BASE_ADDR
30+
#define CMSDK_APB_UART3 UART_3_BASE_ADDR
31+
#define CMSDK_APB_UART4 UART_4_BASE_ADDR
32+
#ifndef CONFIG_HAS_DTS
2833
#define CMSDK_APB_UART_0_IRQ_TX IRQ_UART_0_TX
2934
#define CMSDK_APB_UART_0_IRQ_RX IRQ_UART_0_RX
30-
#define CMSDK_APB_UART1 UART_1_BASE_ADDR
3135
#define CMSDK_APB_UART_1_IRQ_TX IRQ_UART_1_TX
3236
#define CMSDK_APB_UART_1_IRQ_RX IRQ_UART_1_RX
33-
#define CMSDK_APB_UART2 UART_2_BASE_ADDR
3437
#define CMSDK_APB_UART_2_IRQ_TX IRQ_UART_2_TX
3538
#define CMSDK_APB_UART_2_IRQ_RX IRQ_UART_2_RX
36-
#define CMSDK_APB_UART3 UART_3_BASE_ADDR
3739
#define CMSDK_APB_UART_3_IRQ_TX IRQ_UART_3_TX
3840
#define CMSDK_APB_UART_3_IRQ_RX IRQ_UART_3_RX
39-
#define CMSDK_APB_UART4 UART_4_BASE_ADDR
4041
#define CMSDK_APB_UART_4_IRQ_TX IRQ_UART_4_TX
4142
#define CMSDK_APB_UART_4_IRQ_RX IRQ_UART_4_RX
43+
#endif
4244
#endif /* CONFIG_UART_CMSDK_APB */
4345

4446
#if defined(CONFIG_WATCHDOG)

‎boards/arm/mps2_an385/mps2_an385_defconfig‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,9 @@ CONFIG_BOARD_MPS2_AN385=y
1212
CONFIG_CORTEX_M_SYSTICK=y
1313
CONFIG_RUNTIME_NMI=y
1414

15+
#DTS
16+
CONFIG_HAS_DTS=y
17+
1518
# GPIOs
1619
CONFIG_GPIO=y
1720

@@ -29,4 +32,4 @@ CONFIG_UART_CONSOLE_ON_DEV_NAME="UART_0"
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# Watchdog
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CONFIG_WATCHDOG=y
3134

32-
CONFIG_I2C=y
35+
CONFIG_I2C=y

‎dts/arm/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ dtb-$(CONFIG_BOARD_CC3220SF_LAUNCHXL) = cc3220sf_launchxl.dts_compiled
1010
dtb-$(CONFIG_BOARD_NUCLEO_L476RG) = nucleo_l476rg.dts_compiled
1111
dtb-$(CONFIG_BOARD_NUCLEO_L432KC) = nucleo_l432kc.dts_compiled
1212
dtb-$(CONFIG_BOARD_V2M_BEETLE) = v2m_beetle.dts_compiled
13+
dtb-$(CONFIG_BOARD_MPS2_AN385) = mps2_an385.dts_compiled
1314
dtb-$(CONFIG_BOARD_OLIMEXINO_STM32) = olimexino_stm32.dts_compiled
1415
dtb-$(CONFIG_BOARD_96B_CARBON) = 96b_carbon.dts_compiled
1516
dtb-$(CONFIG_BOARD_NUCLEO_F401RE) = nucleo_f401re.dts_compiled

‎dts/arm/mps2_an385.dts‎

Lines changed: 72 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,72 @@
1+
/dts-v1/;
2+
3+
#include <arm/armv7-m.dtsi>
4+
#include "arm/mps2/soc_irq.h"
5+
6+
/ {
7+
compatible = "arm,mps2";
8+
#address-cells = <1>;
9+
#size-cells = <1>;
10+
11+
chosen {
12+
zephyr,console = &uart0;
13+
zephyr,sram = &sram0;
14+
zephyr,flash = &flash0;
15+
};
16+
17+
cpus {
18+
cpu@0 {
19+
compatible = "arm,cortex-m3";
20+
};
21+
};
22+
23+
sram0: memory {
24+
compatible = "sram";
25+
reg = <0x20000000 0x400000>;
26+
};
27+
28+
flash0: flash {
29+
reg = <0 0x400000>;
30+
};
31+
32+
soc {
33+
uart0: uart@40004000 {
34+
compatible = "arm,cmsdk-uart";
35+
reg = <0x40004000 0x14>;
36+
interrupts = <IRQ_UART_0_TX 3 IRQ_UART_0_RX 3>;
37+
current-speed = <115200>;
38+
};
39+
40+
uart1: uart@40005000 {
41+
compatible = "arm,cmsdk-uart";
42+
reg = <0x40005000 0x14>;
43+
interrupts = <IRQ_UART_1_TX 3 IRQ_UART_1_RX 3>;
44+
current-speed = <115200>;
45+
};
46+
47+
uart2: uart@40006000 {
48+
compatible = "arm,cmsdk-uart";
49+
reg = <0x40006000 0x14>;
50+
interrupts = <IRQ_UART_2_TX 3 IRQ_UART_2_RX 3>;
51+
current-speed = <115200>;
52+
};
53+
54+
uart3: uart@40007000 {
55+
compatible = "arm,cmsdk-uart";
56+
reg = <0x40007000 0x14>;
57+
interrupts = <IRQ_UART_3_TX 3 IRQ_UART_3_RX 3>;
58+
current-speed = <115200>;
59+
};
60+
61+
uart4: uart@40009000 {
62+
compatible = "arm,cmsdk-uart";
63+
reg = <0x40009000 0x14>;
64+
interrupts = <IRQ_UART_4_TX 3 IRQ_UART_4_RX 3>;
65+
current-speed = <115200>;
66+
};
67+
};
68+
};
69+
70+
&nvic {
71+
arm,num-irq-priority-bits = <3>;
72+
};

‎dts/arm/mps2_an385.fixup‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
2+
3+
#define CMSDK_APB_UART_0_IRQ_TX ARM_CMSDK_UART_40004000_IRQ_0
4+
#define CMSDK_APB_UART_0_IRQ_RX ARM_CMSDK_UART_40004000_IRQ_1
5+
#define CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI ARM_CMSDK_UART_40004000_IRQ_0_PRIORITY
6+
#define CONFIG_UART_CMSDK_APB_PORT0_BAUD_RATE ARM_CMSDK_UART_40004000_CURRENT_SPEED
7+
8+
#define CMSDK_APB_UART_1_IRQ_TX ARM_CMSDK_UART_40005000_IRQ_0
9+
#define CMSDK_APB_UART_1_IRQ_RX ARM_CMSDK_UART_40005000_IRQ_1
10+
#define CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI ARM_CMSDK_UART_40005000_IRQ_0_PRIORITY
11+
#define CONFIG_UART_CMSDK_APB_PORT1_BAUD_RATE ARM_CMSDK_UART_40005000_CURRENT_SPEED
12+
13+
#define CMSDK_APB_UART_2_IRQ_TX ARM_CMSDK_UART_40006000_IRQ_0
14+
#define CMSDK_APB_UART_2_IRQ_RX ARM_CMSDK_UART_40006000_IRQ_1
15+
#define CONFIG_UART_CMSDK_APB_PORT2_IRQ_PRI ARM_CMSDK_UART_40006000_IRQ_0_PRIORITY
16+
#define CONFIG_UART_CMSDK_APB_PORT2_BAUD_RATE ARM_CMSDK_UART_40006000_CURRENT_SPEED
17+
18+
#define CMSDK_APB_UART_3_IRQ_TX ARM_CMSDK_UART_40007000_IRQ_0
19+
#define CMSDK_APB_UART_3_IRQ_RX ARM_CMSDK_UART_40007000_IRQ_1
20+
#define CONFIG_UART_CMSDK_APB_PORT3_IRQ_PRI ARM_CMSDK_UART_40007000_IRQ_0_PRIORITY
21+
#define CONFIG_UART_CMSDK_APB_PORT3_BAUD_RATE ARM_CMSDK_UART_40007000_CURRENT_SPEED
22+
23+
#define CMSDK_APB_UART_4_IRQ_TX ARM_CMSDK_UART_40009000_IRQ_0
24+
#define CMSDK_APB_UART_4_IRQ_RX ARM_CMSDK_UART_40009000_IRQ_1
25+
#define CONFIG_UART_CMSDK_APB_PORT4_IRQ_PRI ARM_CMSDK_UART_40009000_IRQ_0_PRIORITY
26+
#define CONFIG_UART_CMSDK_APB_PORT4_BAUD_RATE ARM_CMSDK_UART_40009000_CURRENT_SPEED

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