From c5c86778da0682c379d15780abab889de1054ac4 Mon Sep 17 00:00:00 2001
From: keeeeymann <keeeeymann@icloud.com>
Date: Mon, 15 Sep 2025 20:11:53 +0800
Subject: [PATCH 1/3] Update verilog_systemverilog.vim

---
 indent/verilog_systemverilog.vim | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/indent/verilog_systemverilog.vim b/indent/verilog_systemverilog.vim
index 4e8fd1f..ae251f5 100644
--- a/indent/verilog_systemverilog.vim
+++ b/indent/verilog_systemverilog.vim
@@ -329,7 +329,7 @@ function! s:GetContextIndent()
     endif
 
     if l:line =~ '\<endcase\>'
-      let l:lnum = s:SearchForBlockStart(s:vlog_case, '', '\<endcase\>', l:lnum, 1)
+      let l:lnum = s:SearchForBlockStart(s:vlog_case, '', '\<endcase\>', l:lnum, 0)
       let l:oneline_mode = 0
       let l:line = s:GetLineStripped(l:lnum)
     endif

From 6b35934718ececdfebc8f4a64ca83dd165d2231b Mon Sep 17 00:00:00 2001
From: keeeeymann <keeeeymann@icloud.com>
Date: Mon, 15 Sep 2025 20:51:20 +0800
Subject: [PATCH 2/3] add test for indent after endcase

---
 test/indent.sv | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/test/indent.sv b/test/indent.sv
index 612f329..54fba18 100644
--- a/test/indent.sv
+++ b/test/indent.sv
@@ -532,6 +532,27 @@ randcase
     3: value <= 2;
 endcase
 
+// indent after endcase
+// https://github.com/vhda/verilog_systemverilog.vim/issues/250
+begin
+    case (a)
+        1: value = 1;
+    endcase
+
+    begin
+    end
+end
+
+begin
+    randcase
+        1: value = 1;
+    endcase
+
+    begin
+    end
+end
+
+
 interface class base;
 
     pure virtual function void a(input int unsigned N, ref t Data);

From bc9b8ed01627b32eebe5797e9f2a93759524fe04 Mon Sep 17 00:00:00 2001
From: keeeeymann <keeeeymann@icloud.com>
Date: Mon, 15 Sep 2025 20:51:58 +0800
Subject: [PATCH 3/3] add test for indent after endcase

---
 test/indent_standalone.sv | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/test/indent_standalone.sv b/test/indent_standalone.sv
index f355f1a..5bca571 100644
--- a/test/indent_standalone.sv
+++ b/test/indent_standalone.sv
@@ -532,6 +532,26 @@ randcase
     3: value <= 2;
 endcase
 
+// indent after endcase
+// https://github.com/vhda/verilog_systemverilog.vim/issues/250
+begin
+    case (a)
+        1: value = 1;
+    endcase
+
+    begin
+    end
+end
+
+begin
+    randcase
+        1: value = 1;
+    endcase
+
+    begin
+    end
+end
+
 interface class base;
 
     pure virtual function void a(input int unsigned N, ref t Data);