From 6f9d0b7167cb03175239daeff23d64c1cba48527 Mon Sep 17 00:00:00 2001
From: jrudess <jordan.r.rudess@gmail.com>
Date: Wed, 1 Aug 2018 18:49:54 -0700
Subject: [PATCH] Add support for folding of OVM/UVM macros

---
 plugin/verilog_systemverilog.vim | 6 ++++++
 syntax/verilog_systemverilog.vim | 1 +
 2 files changed, 7 insertions(+)

diff --git a/plugin/verilog_systemverilog.vim b/plugin/verilog_systemverilog.vim
index b904e99..599fe53 100644
--- a/plugin/verilog_systemverilog.vim
+++ b/plugin/verilog_systemverilog.vim
@@ -169,6 +169,12 @@ let g:verilog_syntax = {
                         \ 'highlight'   : 'verilogStatement',
                         \ 'syn_argument': 'transparent keepend contains=ALLBUT,verilogInterface',
                         \ }],
+      \ 'ovm'         : [{
+                        \ 'match_start' : '`\<\(ovm\|uvm\)_\a\+_utils_begin\>',
+                        \ 'match_end'   : '`\<\(ovm\|uvm\)_\a\+_utils_end\>',
+                        \ 'highlight'   : 'verilogStatement',
+                        \ 'syn_argument': 'transparent keepend',
+                        \ }],
       \ 'property'    : [{
                         \ 'match_start' : '\<\(\(assert\|cover\)\s\+\)\@<!\<property\>',
                         \ 'match_end'   : '\<endproperty\>',
diff --git a/syntax/verilog_systemverilog.vim b/syntax/verilog_systemverilog.vim
index 3b81d0f..652e913 100644
--- a/syntax/verilog_systemverilog.vim
+++ b/syntax/verilog_systemverilog.vim
@@ -219,6 +219,7 @@ let s:verilog_syntax_order = [
             \ 'function',
             \ 'interface',
             \ 'module',
+            \ 'ovm',
             \ 'property',
             \ 'sequence',
             \ 'specify',