From 4b036ca81018c85566b4360542b1c607c2959183 Mon Sep 17 00:00:00 2001
From: jrudess <jordan.r.rudess@gmail.com>
Date: Wed, 1 Aug 2018 18:16:14 -0700
Subject: [PATCH] Add support for curly code folding

---
 plugin/verilog_systemverilog.vim |  7 +++++++
 syntax/verilog_systemverilog.vim | 11 ++++++++---
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/plugin/verilog_systemverilog.vim b/plugin/verilog_systemverilog.vim
index b904e99..8022389 100644
--- a/plugin/verilog_systemverilog.vim
+++ b/plugin/verilog_systemverilog.vim
@@ -128,6 +128,13 @@ let g:verilog_syntax = {
                         \ 'highlight'   : 'verilogStatement',
                         \ 'syn_argument': 'transparent keepend',
                         \ }],
+      \ 'curly'       : [{
+                        \ 'match_start' : '{',
+                        \ 'match_skip'  : '/[*/].*',
+                        \ 'match_end'   : '}',
+                        \ 'highlight'   : 'verilogOperator',
+                        \ 'syn_argument': 'transparent',
+                        \ }],
       \ 'define'      : [{
                         \ 'match_start' : '`ifn\?def\>',
                         \ 'match_mid'   : '`els\(e\|if\)\>',
diff --git a/syntax/verilog_systemverilog.vim b/syntax/verilog_systemverilog.vim
index 3b81d0f..c8d9706 100644
--- a/syntax/verilog_systemverilog.vim
+++ b/syntax/verilog_systemverilog.vim
@@ -173,9 +173,13 @@ function! s:SyntaxCreate(name, verilog_syntax)
                         let verilog_syn_region_cmd .= ' matchgroup='.entry["highlight"]
                     endif
 
-                    let verilog_syn_region_cmd .=
-                        \  ' start="'.region_start.'"'
-                        \ .' end="'.region_end.'"'
+                    let verilog_syn_region_cmd .= ' start="'.region_start.'"'
+
+                    if exists('entry["match_skip"]')
+                        let verilog_syn_region_cmd .= ' skip="'.entry["match_skip"].'"'
+                    endif
+
+                    let verilog_syn_region_cmd .= ' end="'.region_end.'"'
 
                     if exists('entry["syn_argument"]')
                         let verilog_syn_region_cmd .= ' '.entry["syn_argument"]
@@ -223,6 +227,7 @@ let s:verilog_syntax_order = [
             \ 'sequence',
             \ 'specify',
             \ 'task',
+            \ 'curly',
             \ ]
 
 " Generate syntax definitions for supported types