From cf4bb79a3897875fc655eac2d4c4ab3131035dc4 Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Thu, 18 Sep 2025 12:53:47 -0700 Subject: [PATCH] @FIR-972: Update 6.12.19 LTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ./run_platform_test.sh Check if tnApcMgr is running; if it is not, uncomment below line and execute the run_platform_test.sh script. /proj/sw/work/shirish/sdk-build/sdk/sdk/aot-tests/build-fpga/weights.safetensors exists Running on v0.1.1.tsv36_09_12_2025 [2018-03-09 12:36:07.007] [error] [llama.cpp:14] No expected result file specified, disabling validation. Usage: %s llama_reference.safetensors [2018-03-09 12:36:07.015] [info] Build: 2025-08-11 16:35:04 v0.3.5 (687d27e/HEAD) | Type: RelWithDebInfo | Device: FPGA [2018-03-09 12:36:08.097] [info] [llama.cpp:63] Execution time: 1034 ms [2018-03-09 12:36:08.097] [info] [llama.cpp:66] [LlamaForCausalLM_Random] No expected result file specified, skipping result validation. [2018-03-09 12:36:08.145798] 329:330 [error] :: Invalid request count (0), must be between 1 and 4096 Profiling Results (LlamaForCausalLM_Random): ------------------------------------------------------------------------------------------------------------------------ Calls Total(ms) T/call Self(ms) Function ------------------------------------------------------------------------------------------------------------------------ - 742.3070 0.0000 742.3070 [64.35%] [Thread] LlamaForCausalLM_Random 1235 344.2040 0.2787 0.0000 └─ [29.84%] tsi::runtime::TsavRT::awaitCommandListCompletion 1235 898.4952 0.7275 898.4952 └─ [77.89%] TXE 0 Idle 1024 387.1096 0.3780 387.1096 └─ [33.56%] [ txe_blob_6 ] 96 48.0055 0.5001 48.0055 └─ [ 4.16%] [ txe_blob_1 ] 8 20.8556 2.6069 20.8556 └─ [ 1.81%] [ txe_blob_11 ] 8 19.1245 2.3906 19.1245 └─ [ 1.66%] [ txe_blob_8 ] 8 18.7089 2.3386 18.7089 └─ [ 1.62%] [ txe_blob_9 ] 8 16.9034 2.1129 16.9034 └─ [ 1.47%] [ txe_blob_10 ] 16 8.5623 0.5351 8.5623 └─ [7.42e-01%] [ txe_blob_7 ] 16 2.9197 0.1825 2.9197 └─ [2.53e-01%] [ txe_blob_5 ] 16 2.9138 0.1821 2.9138 └─ [2.53e-01%] [ txe_blob_3 ] 16 2.8928 0.1808 2.8928 └─ [2.51e-01%] [ txe_blob_2 ] 16 2.8832 0.1802 2.8832 └─ [2.50e-01%] [ txe_blob_4 ] 3 0.9383 0.3128 0.9383 └─ [8.13e-02%] [ txe_blob_0 ] 26145 113.4490 0.0043 113.4490 └─ [ 9.83%] tsi::runtime::TsavRT::stridedCopy 60 89.1400 1.4857 0.6750 └─ [ 7.73%] tsi::runtime::TsavRT::getTensor 60 88.2730 1.4712 88.2730 └─ [ 7.65%] tsi::runtime::memory::SafeTensorsParser::loadTensors 120 0.1920 0.0016 0.1920 └─ [1.66e-02%] tsi::runtime::memory::SafeTensorsParser::getTensorBuffer 1 58.7510 58.7510 56.6850 └─ [ 5.09%] tsi::runtime::TsavRTFPGA::finalize 1 2.0660 2.0660 2.0660 └─ [1.79e-01%] tsi::runtime::TsavRTFPGA::releaseTxes 1 43.4040 43.4040 35.4850 └─ [ 3.76%] tsi::runtime::TsavRTFPGA::initialize 1 3.2840 3.2840 3.2840 └─ [2.85e-01%] tsi::runtime::TsavRTFPGA::initializeQueues 1 3.2270 3.2270 3.2270 └─ [2.80e-01%] tsi::runtime::TsavRT::initialize 1 1.4080 1.4080 1.3710 └─ [1.22e-01%] tsi::runtime::TsavRTFPGA::sendNOPTestCommand 2 0.0370 0.0185 0.0370 └─ [3.21e-03%] tsi::runtime::executeWithTimeout 1235 33.0450 0.0268 30.4520 └─ [ 2.86%] tsi::runtime::TsavRT::finalizeCommandList 1235 2.5930 0.0021 2.5930 └─ [2.25e-01%] tsi::runtime::executeWithTimeout 1235 28.5630 0.0231 28.5630 └─ [ 2.48%] tsi::runtime::TsavRT::addCommandToList 1 17.7130 17.7130 1.3300 └─ [ 1.54%] tsi::runtime::TsavRT::initTensorLoader 1 14.0300 14.0300 14.0300 └─ [ 1.22%] tsi::runtime::memory::SafeTensorsParser::parseJSONHeader 1 2.3530 2.3530 2.3530 └─ [2.04e-01%] tsi::runtime::memory::SafeTensorsParser::SafeTensorsParser 12 5.2460 0.4372 5.2460 └─ [4.55e-01%] tsi::runtime::TsavRTFPGA::loadBlob 767 3.5350 0.0046 3.5350 └─ [3.06e-01%] tsi::runtime::TsavRT::allocate 131 2.3430 0.0179 2.3430 └─ [2.03e-01%] tsi::runtime::TsavRT::copy 826 2.2750 0.0028 2.2750 └─ [1.97e-01%] tsi::runtime::TsavRT::deallocate 12 0.6390 0.0533 0.6390 └─ [5.54e-02%] tsi::runtime::TsavRTFPGA::unloadBlob ------------------------------------------------------------------------------------------------------------------------ [Thread] tsi::runtime::TsavRT::processResponses (cumulative over all threads) ------------------------------------------------------------------------------------------------------------------------ 1235 307.0510 0.2486 9.1620 [26.62%] [Thread] tsi::runtime::TsavRT::processResponses 1235 297.8890 0.2412 297.8890 └─ [25.82%] tsi::runtime::executeWithTimeout ======================================================================================================================== - 1153.5590 0.0000 1153.5590 [100.00%] TOTAL ======================================================================================================================== Counter Metrics: ------------------------------------------------------------------------------------------------------------------------ Metric Min Max Avg ------------------------------------------------------------------------------------------------------------------------ Queue_0_Occupancy 0.0000 1.0000 0.9984 ------------------------------------------------------------------------------------------------------------------------ my cat's name is Luna. llama_perf_sampler_print: sampling time = 110.77 ms / 11 runs ( 10.07 ms per token, 99.31 tokens per second) llama_perf_context_print: load time = 88830.83 ms llama_perf_context_print: prompt eval time = 43453.76 ms / 6 tokens ( 7242.29 ms per token, 0.14 tokens per second) llama_perf_context_print: eval time = 121525.86 ms / 4 runs (30381.46 ms per token, 0.03 tokens per second) llama_perf_context_print: total time = 210497.30 ms / 10 tokens === GGML Perf Summary === Op Runs Total us Avg us ADD 220 989557 4497.99 MUL 335 1355105 4045.09 RMS_NORM 734 55200 75.20 MUL_MAT 3465 417486527 120486.73 CPY 641 33326 51.99 CONT 271 3196 11.79 RESHAPE 935 10881 11.64 VIEW 717 1134 1.58 PERMUTE 716 1076 1.50 TRANSPOSE 175 486 2.78 GET_ROWS 46 23306 506.65 SOFT_MAX 301 58907 195.70 ROPE 770 67855 88.12 UNARY 110 502841 4571.28 -> SILU 110 502841 4571.28 [2018-03-09 12:39:41.428105] 329:330 [error] :: Invalid request count (0), must be between 1 and 4096 OPU Profiling Results: ------------------------------------------------------------------------------------------------------------------------ Calls Total(ms) T/call Self(ms) Function ------------------------------------------------------------------------------------------------------------------------ 1 152.0770 152.0770 34.6630 [9.04e-02%] [Thread] OPU 1 117.4140 117.4140 96.1060 └─ [6.98e-02%] tsi::runtime::TsavRTFPGA::initialize 1 9.2100 9.2100 9.2100 └─ [5.48e-03%] tsi::runtime::TsavRTFPGA::initializeQueues 1 8.7220 8.7220 8.7220 └─ [5.19e-03%] tsi::runtime::TsavRT::initialize 1 3.3760 3.3760 2.8580 └─ [2.01e-03%] tsi::runtime::TsavRTFPGA::sendNOPTestCommand 2 0.5180 0.2590 0.5180 └─ [3.08e-04%] tsi::runtime::executeWithTimeout ------------------------------------------------------------------------------------------------------------------------ [Thread] tsi::runtime::TsavRT::awaitCommandListCompletion (cumulative over all threads) ------------------------------------------------------------------------------------------------------------------------ 1195 1074.6440 0.8993 0.0000 [6.39e-01%] [Thread] tsi::runtime::TsavRT::awaitCommandListCompletion 1195 3.29e+05 275.1446 3.29e+05 └─ [195.50%] TXE 0 Idle 655 592.6633 0.9048 592.6633 └─ [3.52e-01%] [ txe_mult ] 110 320.6818 2.9153 320.6818 └─ [1.91e-01%] [ txe_silu ] 430 274.6878 0.6388 274.6878 └─ [1.63e-01%] [ txe_add ] ------------------------------------------------------------------------------------------------------------------------ [Thread] tsi::runtime::TsavRT::finalizeCommandList (cumulative over all threads) ------------------------------------------------------------------------------------------------------------------------ 1195 867.2310 0.7257 827.2830 [5.16e-01%] [Thread] tsi::runtime::TsavRT::finalizeCommandList 1195 39.9480 0.0334 39.9480 └─ [2.38e-02%] tsi::runtime::executeWithTimeout ------------------------------------------------------------------------------------------------------------------------ [Thread] tsi::runtime::TsavRT::processResponses (cumulative over all threads) ------------------------------------------------------------------------------------------------------------------------ 1195 1548.9540 1.2962 56.4450 [9.21e-01%] [Thread] tsi::runtime::TsavRT::processResponses 1195 1492.5090 1.2490 1492.5090 └─ [8.87e-01%] tsi::runtime::executeWithTimeout ------------------------------------------------------------------------------------------------------------------------ [Thread] tsi::runtime::TsavRTFPGA::finalize (cumulative over all threads) ------------------------------------------------------------------------------------------------------------------------ 1 70.2460 70.2460 60.8160 [4.18e-02%] [Thread] tsi::runtime::TsavRTFPGA::finalize 1 9.4300 9.4300 9.4300 └─ [5.61e-03%] tsi::runtime::TsavRTFPGA::releaseTxes ------------------------------------------------------------------------------------------------------------------------ [Thread] tsi::runtime::TsavRT::allocate (cumulative over all threads) ------------------------------------------------------------------------------------------------------------------------ 1196 75.3060 0.0630 75.3060 [4.48e-02%] [Thread] tsi::runtime::TsavRT::allocate ------------------------------------------------------------------------------------------------------------------------ [Thread] tsi::runtime::TsavRTFPGA::loadBlob (cumulative over all threads) ------------------------------------------------------------------------------------------------------------------------ 1195 415.2100 0.3475 415.2100 [2.47e-01%] [Thread] tsi::runtime::TsavRTFPGA::loadBlob ------------------------------------------------------------------------------------------------------------------------ [Thread] tsi::runtime::TsavRT::addCommandToList (cumulative over all threads) ------------------------------------------------------------------------------------------------------------------------ 1195 69.5420 0.0582 69.5420 [4.13e-02%] [Thread] tsi::runtime::TsavRT::addCommandToList ------------------------------------------------------------------------------------------------------------------------ [Thread] tsi::runtime::TsavRTFPGA::unloadBlob (cumulative over all threads) ------------------------------------------------------------------------------------------------------------------------ 1195 91.4560 0.0765 91.4560 [5.44e-02%] [Thread] tsi::runtime::TsavRTFPGA::unloadBlob ------------------------------------------------------------------------------------------------------------------------ [Thread] tsi::runtime::TsavRT::deallocate (cumulative over all threads) ------------------------------------------------------------------------------------------------------------------------ 1195 18.9050 0.0158 18.9050 [1.12e-02%] [Thread] tsi::runtime::TsavRT::deallocate ======================================================================================================================== - 1.68e+05 0.0000 1.68e+05 [100.00%] TOTAL ======================================================================================================================== Counter Metrics: ------------------------------------------------------------------------------------------------------------------------ Metric Min Max Avg ------------------------------------------------------------------------------------------------------------------------ Queue_0_Occupancy 0.0000 1.0000 0.6951 ------------------------------------------------------------------------------------------------------------------------ --- arch/arm64/boot/dts/intel/Makefile | 1 + .../dts/intel/fm87_ftile_10g_2port_ptp.dtsi | 206 +++++ .../dts/intel/socfpga_agilex_bittware.dts | 202 +++++ .../dts/intel/socfpga_agilex_bittware.dtsi | 709 ++++++++++++++++++ .../boot/dts/intel/socfpga_agilex_socdk.dts | 2 +- arch/arm64/configs/defconfig | 86 ++- drivers/nvme/host/pci.c | 4 +- drivers/tty/serial/Kconfig | 2 +- 8 files changed, 1205 insertions(+), 7 deletions(-) create mode 100644 arch/arm64/boot/dts/intel/fm87_ftile_10g_2port_ptp.dtsi create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dtsi diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index f20e994963c0..cf7102008072 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_atfboot.dtb \ socfpga_agilex_socdk_nand.dtb \ + socfpga_agilex_bittware.dtb \ socfpga_agilex3_socdk.dtb \ socfpga_agilex5_socdk.dtb \ socfpga_agilex_n6010.dtb \ diff --git a/arch/arm64/boot/dts/intel/fm87_ftile_10g_2port_ptp.dtsi b/arch/arm64/boot/dts/intel/fm87_ftile_10g_2port_ptp.dtsi new file mode 100644 index 000000000000..c835c331f07c --- /dev/null +++ b/arch/arm64/boot/dts/intel/fm87_ftile_10g_2port_ptp.dtsi @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(C) 2022, Intel Corporation + */ + +/* Add this piece of dtsi fragment as #include "fm87_ftile_25g_ptp.dtsi" + * in the file socfpga_fm87_ftile_25g_ptp.dts. Compile it in the kernel along with + * socfpga_agilex.dtsi + */ + +/{ + soc { + agilex_hps_bridges: bus@88000000 { + compatible = "simple-bus"; + reg = <0x80000000 0x60000000>, + <0xf9000000 0x00100000>; + reg-names = "axi_h2f", "axi_h2f_lw"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>, + <0x00000001 0x00000000 0x80000000 0x00040000>, + <0x00000001 0x04040050 0x84040050 0x00000010>, + <0x00000001 0x04040040 0x84040040 0x00000010>; + + + qsfp_eth0: qsfp-eth0 { + compatible = "sff,qsfp"; + i2c-bus = <&i2c0>; + qsfpdd_initmode-gpio = <&qsfpdd_ctrl_pio 1 GPIO_ACTIVE_HIGH>; + qsfpdd_modseln-gpio = <&qsfpdd_ctrl_pio 2 GPIO_ACTIVE_LOW>; + qsfpdd_modprsn-gpio = <&qsfpdd_status_pio 0 GPIO_ACTIVE_LOW>; + qsfpdd_resetn-gpio = <&qsfpdd_ctrl_pio 0 GPIO_ACTIVE_HIGH>; + qsfpdd_intn-gpio = <&qsfpdd_status_pio 1 GPIO_ACTIVE_LOW>; + agilex_hps_spim = <&qsfpdd_ctrl_pio 3 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <1000>; + status = "disable"; +/* status = "okay"; */ + }; + + qsfpdd_status_pio: gpio@4040050 { + compatible = "altr,pio-1.0"; + reg = <0x00000001 0x04040050 0x10>; + interrupt-parent = <&intc>; + interrupts = <0 22 4>; + altr,gpio-bank-width = <4>; + altr,interrupt-type = <2>; + + altr,interrupt_type = <2>; + #gpio-cells = <2>; + gpio-controller; + status = "okay"; + /*status = "disable";*/ + }; + + qsfpdd_ctrl_pio: gpio@4040040 { + compatible = "altr,pio-1.0"; + reg = <0x00000001 0x04040040 0x10>; + interrupt-parent = <&intc>; + interrupts = <0 23 4>; + altr,gpio-bank-width = <4>; + altr,interrupt-type = <2>; + altr,interrupt_type = <2>; + #gpio-cells = <2>; + gpio-controller; + status = "okay"; + /*status = "disable"; */ + }; + + }; + clocks { + tod_in_clock: tod_in_clock { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <156250000>; + clock-output-names = "tod_in_clock"; + }; + }; + + ptp_clockcleaner: ptp_clockcleaner { + compatible = "intel, freq-steering-zl-i2c"; + dpll-name = "zl30733"; + interface = "i2c"; + bus-num = <1>; + bus-address = <0x70>; + }; + + tod_0_clk: tod_0_clk { + compatible = "intel, tod"; + reg-names = "tod_ctrl", + "pps_ctrl"; + reg = <0x84040000 0x00000040>, + <0x84040100 0x00000040>; + interrupt-parent = <&intc>; + interrupt-names = "pps_irq"; + interrupts = <0 19 4>; + clocks = <&tod_in_clock>; + clock-names = "tod_clock"; + status = "okay"; + altr,has-ptp-clockcleaner; + clock-cleaner = <&ptp_clockcleaner>; + }; + + hssiss_0_hssiss: hssiss_0_hssiss { + compatible = "intel, hssiss-1.0"; + reg-names = "sscsr"; + reg = <0x88000000 0x04000000>; + reset-mode ="reg"; + }; + hssi_0_eth: hssi_0_eth@88000000 { + reg-names = "tx_pref" , + "tx_csr" , + "tx_fifo" , + "rx_pref" , + "rx_csr" , + "rx_fifo" ; + + reg = <0x8c480000 0x00000020>, + <0x8c480020 0x00000020>, + <0x8c480040 0x00000020>, + <0x8c480080 0x00000020>, + <0x8c4800A0 0x00000020>, + <0x8c4800C0 0x00000010>; + + compatible = "altr,hssi-ftile-1.0"; + tile_chan = <0x8>; + hssi_port = <0x8>; + phy-mode = "10gbase-r"; + tod = <&tod_0_clk>; + hssiss = <&hssiss_0_hssiss>; + pma_type = <0x0>; // FGT - 0x00, FHT = 0x1000 + altr,tx-pma-delay-ns = <0xD>; + altr,rx-pma-delay-ns = <0x8>; + altr,tx-pma-delay-fns = <0x24D>; + altr,rx-pma-delay-fns = <0x3E97>; + altr,tx-external-phy-delay-ns = <0x0>; + altr,rx-external-phy-delay-ns = <0x0>; + fec-cw-pos-rx = <0x0>; + fec-type="no-fec"; + interrupt-parent = <&intc>; + interrupt-names = "tx_irq", "rx_irq"; + interrupts = <0 24 4>, <0 25 4>; + qsfp-lane = <0x0>; + rx-fifo-depth = <0x4000>; + tx-fifo-depth = <0x1000>; + rx-fifo-almost-full = <0x2000>; + rx-fifo-almost-empty = <0x1000>; + altr,has-ptp; + ptp_accu_mode = "Advanced"; + ptp_tx_routing_adj = <0xDE9F>; //56,991 + ptp_rx_routing_adj = <0xD625>; //54,821 + status = "okay"; + fixed-link { + speed =<10000>; + full-duplex; + }; + }; + hssi_1_eth: hssi_1_eth@88000000 { + reg-names = "tx_pref" , + "tx_csr" , + "tx_fifo" , + "rx_pref" , + "rx_csr" , + "rx_fifo" ; + + reg = <0x8c4C0000 0x00000020>, + <0x8c4C0020 0x00000020>, + <0x8c4C0040 0x00000020>, + <0x8c4C0080 0x00000020>, + <0x8c4C00A0 0x00000020>, + <0x8c4C00C0 0x00000010>; + + compatible = "altr,hssi-ftile-1.0"; + tile_chan = <0x9>; + hssi_port = <0x9>; + phy-mode = "10gbase-r"; + tod = <&tod_0_clk>; + hssiss = <&hssiss_0_hssiss>; + pma_type = <0x0>; // FGT - 0x00, FHT = 0x1000 + altr,tx-pma-delay-ns = <0xD>; + altr,rx-pma-delay-ns = <0x8>; + altr,tx-pma-delay-fns = <0x24D>; + altr,rx-pma-delay-fns = <0x3E97>; + altr,tx-external-phy-delay-ns = <0x0>; + altr,rx-external-phy-delay-ns = <0x0>; + fec-cw-pos-rx = <0x0>; + fec-type="no-fec"; + interrupt-parent = <&intc>; + interrupt-names = "tx_irq", "rx_irq"; + interrupts = <0 26 4>, <0 27 4>; + qsfp-lane = <0x0>; + rx-fifo-depth = <0x4000>; + tx-fifo-depth = <0x1000>; + rx-fifo-almost-full = <0x2000>; + rx-fifo-almost-empty = <0x1000>; + altr,has-ptp; + ptp_accu_mode = "Advanced"; + ptp_tx_routing_adj = <0xDE3C>; //56,892 + ptp_rx_routing_adj = <0xD73F>; //55,103 + status = "okay"; + fixed-link { + speed =<10000>; + full-duplex; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts new file mode 100644 index 000000000000..e41c6be93043 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019, Intel Corporation + */ +#include "socfpga_agilex_bittware.dtsi" +#include "socfpga_agilex_pcie_root_port.dtsi" +#include "fm87_ftile_10g_2port_ptp.dtsi" + +/ { + model = "SoCFPGA Agilex BittWare"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + leds { + compatible = "gpio-leds"; + led0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + led1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + led2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac2 { + status = "okay"; + phy-mode = "gmii"; /* gmii from rgmii */ + phy-handle = <&phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <900>; /* 0ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&nand { + status = "okay"; + nand-bus-width = <8>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + nand-bus-width = <8>; + + partition@0 { + label = "u-boot"; + reg = <0 0x200000>; + }; + partition@200000 { + label = "root"; + reg = <0x200000 0x1fe00000>; + }; + }; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog0 { + status = "okay"; +}; + +&temp_volt { + voltage { + #address-cells = <1>; + #size-cells = <0>; + input@2 { + label = "0.8V VCC"; + reg = <2>; + }; + + input@3 { + label = "1.8V VCCIO_SDM"; + reg = <3>; + }; + + input@4 { + label = "1.8V VCCPT"; + reg = <4>; + }; + + input@5 { + label = "1.2V VCCCRCORE"; + reg = <5>; + }; + + input@6 { + label = "0.9V VCCH"; + reg = <6>; + }; + + input@7 { + label = "0.8V VCCL"; + reg = <7>; + }; + }; + + temperature { + #address-cells = <1>; + #size-cells = <0>; + + input@0 { + label = "Main Die SDM"; + reg = <0x0>; + }; + + input@10000 { + label = "Main Die corner bottom left max"; + reg = <0x10000>; + }; + + input@20000 { + label = "Main Die corner top left max"; + reg = <0x20000>; + }; + + input@30000 { + label = "Main Die corner bottom right max"; + reg = <0x30000>; + }; + + input@40000 { + label = "Main Die corner top right max"; + reg = <0x40000>; + }; + }; +}; + +&pcie_0_pcie_aglx { + status = "okay"; + compatible = "altr,pcie-root-port-3.0-f-tile"; +}; + +&gmac0 { + status = "okay"; + phy-mode = "gmii"; /* gmii from rgmii */ + //phy-handle = <&phy0>; /* added after tcpdump */ + + fixed-link { + speed = <1000>; + full-duplex; + pause; + asym-pause; + }; +}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dtsi new file mode 100644 index 000000000000..a353beef6454 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dtsi @@ -0,0 +1,709 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019, Intel Corporation + */ + +/dts-v1/; +#include +#include +#include +#include + +/ { + compatible = "intel,socfpga-agilex"; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + service_reserved: svcbuffer@0 { + compatible = "shared-dma-pool"; + reg = <0x0 0x0 0x0 0x2000000>; + alignment = <0x1000>; + no-map; + }; + service_reserved1: svcbuffer@1 { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 0x40000000 0x0 0x40000000>; + alignment = <0x1000>; + }; + service_reserved2: svcbuffer@2 { + compatible = "shared-dma-pool"; + no-map-fixup; + reg = <0x20 0x80000000 0x0 0x80000000>; + alignment = <0x1000>; + }; + }; + udmabuf@0 { + compatible = "ikwzm,u-dma-buf"; + device-name = "udmabuf0"; + size = <0x40000000>; // 1GiB + memory-region = <&service_reserved1>; + }; + + udmabuf@1 { + compatible = "ikwzm,u-dma-buf"; + device-name = "udmabuf1"; + size = <0x80000000>; // 2GiB + memory-region = <&service_reserved2>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x1>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x3>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + interrupt-parent = <&intc>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + intc: interrupt-controller@fffc1000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0xfffc1000 0x0 0x1000>, + <0x0 0xfffc2000 0x0 0x2000>, + <0x0 0xfffc4000 0x0 0x2000>, + <0x0 0xfffc6000 0x0 0x2000>; + }; + + clocks { + cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + cb_intosc_ls_clk: cb-intosc-ls-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_free_clk: f2s-free-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + qspi_clk: qspi-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + }; + + usbphy0: usbphy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + }; + + soc0: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges = <0 0 0 0xffffffff>; + + base_fpga_region { + #address-cells = <0x2>; + #size-cells = <0x2>; + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr>; + }; + + clkmgr: clock-controller@ffd10000 { + compatible = "intel,agilex-clkmgr"; + reg = <0xffd10000 0x1000>; + #clock-cells = <1>; + }; + + gmac0: ethernet@ff800000 { + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; + reg = <0xff800000 0x2000>; + interrupts = ; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names = "stmmaceth", "ahb"; + tx-fifo-depth = <16384>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <256>; + iommus = <&smmu 1>; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; + clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + status = "disabled"; + }; + + gmac1: ethernet@ff802000 { + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; + reg = <0xff802000 0x2000>; + interrupts = ; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names = "stmmaceth", "ahb"; + tx-fifo-depth = <16384>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <256>; + iommus = <&smmu 2>; + altr,sysmgr-syscon = <&sysmgr 0x48 0>; + clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + status = "disabled"; + }; + + gmac2: ethernet@ff804000 { + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; + reg = <0xff804000 0x2000>; + interrupts = ; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names = "stmmaceth", "ahb"; + tx-fifo-depth = <16384>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <256>; + iommus = <&smmu 3>; + altr,sysmgr-syscon = <&sysmgr 0x4c 0>; + clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + status = "disabled"; + }; + + gpio0: gpio@ffc03200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc03200 0x100>; + resets = <&rst GPIO0_RESET>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; + + gpio1: gpio@ffc03300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc03300 0x100>; + resets = <&rst GPIO1_RESET>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; + + i2c0: i2c@ffc02800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; + reg = <0xffc02800 0x100>; + interrupts = ; + resets = <&rst I2C0_RESET>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + status = "disabled"; + }; + + i2c1: i2c@ffc02900 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; + reg = <0xffc02900 0x100>; + interrupts = ; + resets = <&rst I2C1_RESET>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + status = "disabled"; + }; + + i2c2: i2c@ffc02a00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; + reg = <0xffc02a00 0x100>; + interrupts = ; + resets = <&rst I2C2_RESET>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + status = "disabled"; + }; + + i2c3: i2c@ffc02b00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; + reg = <0xffc02b00 0x100>; + interrupts = ; + resets = <&rst I2C3_RESET>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + status = "disabled"; + }; + + i2c4: i2c@ffc02c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,socfpga-i2c", "snps,designware-i2c"; + reg = <0xffc02c00 0x100>; + interrupts = ; + resets = <&rst I2C4_RESET>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + status = "disabled"; + }; + + mmc: mmc@ff808000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff808000 0x1000>; + interrupts = ; + fifo-depth = <0x400>; + resets = <&rst SDMMC_RESET>; + reset-names = "reset"; + clocks = <&clkmgr AGILEX_L4_MP_CLK>, + <&clkmgr AGILEX_SDMMC_CLK>; + clock-names = "biu", "ciu"; + iommus = <&smmu 5>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; + status = "disabled"; + }; + + nand: nand-controller@ffb90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-denali-nand"; + reg = <0xffb90000 0x10000>, + <0xffb80000 0x1000>; + reg-names = "nand_data", "denali_reg"; + interrupts = ; + clocks = <&clkmgr AGILEX_NAND_CLK>, + <&clkmgr AGILEX_NAND_X_CLK>, + <&clkmgr AGILEX_NAND_ECC_CLK>; + clock-names = "nand", "nand_x", "ecc"; + resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; + status = "disabled"; + }; + + ocram: sram@ffe00000 { + compatible = "mmio-sram"; + reg = <0xffe00000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xffe00000 0x40000>; + }; + + pdma: dma-controller@ffda0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffda0000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; + reset-names = "dma", "dma-ocp"; + clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; + clock-names = "apb_pclk"; + }; + + pinctrl0: pinctrl@ffd13000 { + compatible = "pinctrl-single"; + #pinctrl-cells = <1>; + reg = <0xffd13000 0xa0>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + }; + + pinctrl1: pinconf@ffd13100 { + compatible = "pinctrl-single"; + #pinctrl-cells = <1>; + reg = <0xffd13100 0x20>; + pinctrl-single,register-width = <32>; + }; + + rst: rstmgr@ffd11000 { + compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr"; + reg = <0xffd11000 0x100>; + #reset-cells = <1>; + }; + + smmu: iommu@fa000000 { + compatible = "arm,mmu-500", "arm,smmu-v2"; + reg = <0xfa000000 0x40000>; + #global-interrupts = <2>; + #iommu-cells = <1>; + interrupt-parent = <&intc>; + /* Global Secure Fault */ + interrupts = , + /* Global Non-secure Fault */ + , + /* Non-secure Context Interrupts (32) */ + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + stream-match-mask = <0x7ff0>; + clocks = <&clkmgr AGILEX_MPU_CCU_CLK>, + <&clkmgr AGILEX_L3_MAIN_FREE_CLK>, + <&clkmgr AGILEX_L4_MAIN_CLK>; + status = "disabled"; + }; + + spi0: spi@ffda4000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda4000 0x1000>; + interrupts = ; + resets = <&rst SPIM0_RESET>; + reset-names = "spi"; + reg-io-width = <4>; + num-cs = <4>; + clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; + status = "disabled"; + }; + + spi1: spi@ffda5000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda5000 0x1000>; + interrupts = ; + resets = <&rst SPIM1_RESET>; + reset-names = "spi"; + reg-io-width = <4>; + num-cs = <4>; + clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; + status = "disabled"; + }; + + sysmgr: sysmgr@ffd12000 { + compatible = "altr,sys-mgr-s10","altr,sys-mgr"; + reg = <0xffd12000 0x500>; + }; + + timer0: timer0@ffc03000 { + compatible = "snps,dw-apb-timer"; + interrupts = ; + reg = <0xffc03000 0x100>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clock-names = "timer"; + }; + + timer1: timer1@ffc03100 { + compatible = "snps,dw-apb-timer"; + interrupts = ; + reg = <0xffc03100 0x100>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clock-names = "timer"; + }; + + timer2: timer2@ffd00000 { + compatible = "snps,dw-apb-timer"; + interrupts = ; + reg = <0xffd00000 0x100>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clock-names = "timer"; + }; + + timer3: timer3@ffd00100 { + compatible = "snps,dw-apb-timer"; + interrupts = ; + reg = <0xffd00100 0x100>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + clock-names = "timer"; + }; + + uart0: serial@ffc02000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART0_RESET>; + status = "disabled"; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + }; + + uart1: serial@ffc02100 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02100 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART1_RESET>; + clocks = <&clkmgr AGILEX_L4_SP_CLK>; + status = "disabled"; + }; + + usb0: usb@ffb00000 { + compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; + reg = <0xffb00000 0x40000>; + interrupts = ; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; + reset-names = "dwc2", "dwc2-ecc"; + clocks = <&clkmgr AGILEX_USB_CLK>; + clock-names = "otg"; + iommus = <&smmu 6>; + status = "disabled"; + }; + + usb1: usb@ffb40000 { + compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; + reg = <0xffb40000 0x40000>; + interrupts = ; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; + reset-names = "dwc2", "dwc2-ecc"; + iommus = <&smmu 7>; + clocks = <&clkmgr AGILEX_USB_CLK>; + status = "disabled"; + }; + + watchdog0: watchdog@ffd00200 { + compatible = "snps,dw-wdt"; + reg = <0xffd00200 0x100>; + interrupts = ; + resets = <&rst WATCHDOG0_RESET>; + clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog1: watchdog@ffd00300 { + compatible = "snps,dw-wdt"; + reg = <0xffd00300 0x100>; + interrupts = ; + resets = <&rst WATCHDOG1_RESET>; + clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog2: watchdog@ffd00400 { + compatible = "snps,dw-wdt"; + reg = <0xffd00400 0x100>; + interrupts = ; + resets = <&rst WATCHDOG2_RESET>; + clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog3: watchdog@ffd00500 { + compatible = "snps,dw-wdt"; + reg = <0xffd00500 0x100>; + interrupts = ; + resets = <&rst WATCHDOG3_RESET>; + clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + sdr: sdr@f8011100 { + compatible = "altr,sdr-ctl", "syscon"; + reg = <0xf8011100 0xc0>; + }; + + eccmgr { + compatible = "altr,socfpga-s10-ecc-manager", + "altr,socfpga-a10-ecc-manager"; + altr,sysmgr-syscon = <&sysmgr>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + ranges; + + sdramedac { + compatible = "altr,sdram-edac-s10"; + altr,sdr-syscon = <&sdr>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + }; + + ocram-ecc@ff8cc000 { + compatible = "altr,socfpga-s10-ocram-ecc", + "altr,socfpga-a10-ocram-ecc"; + reg = <0xff8cc000 0x100>; + altr,ecc-parent = <&ocram>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + }; + + usb0-ecc@ff8c4000 { + compatible = "altr,socfpga-s10-usb-ecc", + "altr,socfpga-usb-ecc"; + reg = <0xff8c4000 0x100>; + altr,ecc-parent = <&usb0>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + }; + + emac0-rx-ecc@ff8c0000 { + compatible = "altr,socfpga-s10-eth-mac-ecc", + "altr,socfpga-eth-mac-ecc"; + reg = <0xff8c0000 0x100>; + altr,ecc-parent = <&gmac0>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + }; + + emac0-tx-ecc@ff8c0400 { + compatible = "altr,socfpga-s10-eth-mac-ecc", + "altr,socfpga-eth-mac-ecc"; + reg = <0xff8c0400 0x100>; + altr,ecc-parent = <&gmac0>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + }; + + sdmmca-ecc@ff8c8c00 { + compatible = "altr,socfpga-s10-sdmmc-ecc", + "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c8c00 0x100>; + altr,ecc-parent = <&mmc>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + qspi: spi@ff8d2000 { + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff8d2000 0x100>, + <0xff900000 0x100000>; + interrupts = ; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; + + status = "disabled"; + }; + + firmware { + svc { + compatible = "intel,agilex-svc"; + method = "smc"; + memory-region = <&service_reserved>; + + fpga_mgr: fpga-mgr { + compatible = "intel,agilex-soc-fpga-mgr"; + }; + + fcs: fcs { + compatible = "intel,agilex-soc-fcs"; + platform = "agilex"; + }; + + temp_volt: hwmon { + compatible = "intel,soc64-hwmon"; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index 416fde60b003..fc0a62678a2f 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -16,7 +16,7 @@ }; chosen { - stdout-path = "serial0:115200n8"; + stdout-path = "serial0:921600n8"; }; leds { diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 8b170c3ef1f5..be09e54877bd 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1248,8 +1248,8 @@ CONFIG_RENESAS_USB_DMAC=m CONFIG_RZ_DMAC=y CONFIG_TI_K3_UDMA=y CONFIG_TI_K3_UDMA_GLUE_LAYER=y -CONFIG_UIO=m -CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_UIO=y +CONFIG_UIO_PDRV_GENIRQ=y CONFIG_VFIO=m CONFIG_VFIO_PCI=m CONFIG_VIRTIO_PCI=y @@ -1713,7 +1713,7 @@ CONFIG_CRYPTO_DEV_HISI_HPRE=m CONFIG_CRYPTO_DEV_HISI_TRNG=m CONFIG_CRYPTO_DEV_SA2UL=m CONFIG_DMA_RESTRICTED_POOL=y -CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_CMA_SIZE_MBYTES=2 CONFIG_PRINTK_TIME=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y @@ -1734,3 +1734,83 @@ CONFIG_CORESIGHT_CTI=m CONFIG_MEMTEST=y CONFIG_SENSORS_SOC64=m CONFIG_ALTERA_SOCFPGA_CONFIG=m +CONFIG_STRICT_DEVMEM=n +CONFIG_IO_STRICT_DEVMEM=n +CONFIG_HUGETLB_PAGE=y +##MM includes +CONFIG_BLK_DEV_NVME=y +#CONFIG_NVME_MULTIPATH=y +#CONFIG_NVME_VERBOSE_ERRORS=y +#CONFIG_NVME_HWMON=y +#CONFIG_NVME_FC=y +CONFIG_DUMMY=m + +########################################## +# For Flannel enable config flags +# For NFT tables, STP, VXLAN and Wireguard +######################################### +CONFIG_CFS_BANDWIDTH=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_UDP_TUNNEL=m +CONFIG_NF_DUP_NETDEV=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_TABLES_BRIDGE=y +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_IPV4=y +CONFIG_NF_TABLES_IPV6=y +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NFT_CHAIN_NAT_IPV4=m +CONFIG_NFT_CHAIN_ROUTE_IPV4=m +CONFIG_NFT_CHAIN_ROUTE_IPV6=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CT=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_HASH=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_MASQ_IPV4=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_NAT=m +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REDIR_IPV4=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_REJECT_INET=m +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_REJECT_IPV6=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_STP=m +CONFIG_VXLAN=m +CONFIG_WIREGUARD=m +CONFIG_PHYLIB=y +CONFIG_FIXED_PHY=y +CONFIG_DWMAC_SOCFPGA=y +CONFIG_DWMAC_ETH_FLOW_CTRL=n +/*Ethernet */ +CONFIG_PTP_1588_CLOCK=n +CONFIG_NET_PTP_CLASSIFY=n +CONFIG_PTP_1588_CLOCK_API=n +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_INFO=y +CONFIG_STMMAC_DEBUG=y # if available +CONFIG_DWMAC_DEBUG=y # if available +CONFIG_NETDEV_DEBUG=y diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index e1329d4974fd..228daf004c41 100644 --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c @@ -1442,9 +1442,9 @@ static enum blk_eh_timer_return nvme_timeout(struct request *req) nvme_poll_irqdisable(nvmeq); if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) { - dev_warn(dev->ctrl.device, + /*dev_warn(dev->ctrl.device, "I/O tag %d (%04x) QID %d timeout, completion polled\n", - req->tag, nvme_cid(req), nvmeq->qid); + req->tag, nvme_cid(req), nvmeq->qid);*/ return BLK_EH_DONE; } diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 28e4beeabf8f..2da0a96bb456 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1134,7 +1134,7 @@ config SERIAL_ALTERA_UART_MAXPORTS config SERIAL_ALTERA_UART_BAUDRATE int "Default baudrate for Altera UART ports" depends on SERIAL_ALTERA_UART - default 115200 + default 921600 help This setting lets you define what the default baudrate is for the Altera UART ports. The usual default varies from board to board,