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Shaunak Saha
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@FIR-546: Update 6.6.51 LTS
Signed-off-by: Shaunak Saha <[email protected]> Update to 6.6.51 LTS and include the tsavorite specific patches: @FIR-507: Preliminary changes to test upto 3GB memory. Test results are as follows --------------------------- root@agilex7_dk_si_agf014ea:/usr/bin/tsi/v0.1.1.tsv22_02_03_2025/bin# ./run_platform_test.sh Check if tnApcMgr is running; if it is not, uncomment below line and execute the run_platform_test.sh script. Running on v0.1.1.tsv22_02_03_2025 [LlamaForCausalLM_Random v.1] Allocated DRAM arrays (host VAs): input0 = 0xffffa3a9d080 input1 = 0xffffa2e9d080 output0 = 0xffffa369d080 [LlamaForCausalLM_Random v.1] Model executed successfully. Validating result... [LlamaForCausalLM_Random v.1] PASS [relative err=0.000001] root@agilex7_dk_si_agf014ea:/usr/bin/tsi/v0.1.1.tsv22_02_03_2025/bin# cd aot-tests/ root@agilex7_dk_si_agf014ea:/usr/bin/tsi/v0.1.1.tsv22_02_03_2025/bin/aot-tests# root@agilex7_dk_si_agf014ea:/usr/bin/tsi/v0.1.1.tsv22_02_03_2025/bin/aot-tests# ./models/llama_sp/llama_sp.sh ./models/llama_sp/llama_sp.exe: error while loading shared libraries: libTsavRTFPGA.so.0.3.4: cannot open shared object file: No such file or directory root@agilex7_dk_si_agf014ea:/usr/bin/tsi/v0.1.1.tsv22_02_03_2025/bin/aot-tests# export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/usr/bin/tsi/v0.1.1.tsv22_02_03_2025/bin/aot-tests/lib/ root@agilex7_dk_si_agf014ea:/usr/bin/tsi/v0.1.1.tsv22_02_03_2025/bin/aot-tests# ./models/llama_sp/llama_sp.sh Environment variable TOKENIZER_MODEL_PATH is not set. Please set it to the path of the tokenizer model. root@agilex7_dk_si_agf014ea:/usr/bin/tsi/v0.1.1.tsv22_02_03_2025/bin/aot-tests# ls /tsi/ animesh anoop_dec15 atrivedi cdogra dinesh lost+found ross sponnambalam tsi-sw anoop aot-tests bnorris demo dmohapatra meera runtime test vgarg root@agilex7_dk_si_agf014ea:/usr/bin/tsi/v0.1.1.tsv22_02_03_2025/bin/aot-tests# ls /tsi/atrivedi/ _deps aot-all-tests.tz lib models rt_lib.txt rtlib_0.3.1.tz tokenizer.model tvu ullama ullama_bf16 usr_lib.txt root@agilex7_dk_si_agf014ea:/usr/bin/tsi/v0.1.1.tsv22_02_03_2025/bin/aot-tests# export TOKENIZER_MODEL_PATH=/tsi/atrivedi/tokenizer.model root@agilex7_dk_si_agf014ea:/usr/bin/tsi/v0.1.1.tsv22_02_03_2025/bin/aot-tests# ./models/llama_sp/llama_sp.sh Generating text... Generated token 4/26: " a " (ID: 260 ) - Time: 3.22 s Generated token 5/26: " sound " (ID: 2144 ) - Time: 3.18 s Generated token 6/26: " ' " (ID: 31876 ) - Time: 3.19 s Generated token 7/26: " s " (ID: 31829 ) - Time: 3.20 s Generated token 8/26: " coat " (ID: 13085 ) - Time: 3.15 s Generated token 9/26: " . " (ID: 31843 ) - Time: 3.15 s Generated token 10/26: " He " (ID: 636 ) - Time: 3.15 s Generated token 11/26: " says " (ID: 1329 ) - Time: 3.15 s Generated token 12/26: " , " (ID: 31844 ) - Time: 3.18 s Generated token 13/26: " " " (ID: 495 ) - Time: 3.18 s Generated token 14/26: " I " (ID: 31850 ) - Time: 3.18 s Generated token 15/26: " will " (ID: 482 ) - Time: 3.15 s Generated token 16/26: " try " (ID: 1489 ) - Time: 3.15 s Generated token 17/26: " !" " (ID: 6573 ) - Time: 3.18 s Generated token 18/26: " " (ID: 13 ) - Time: 3.15 s Generated token 19/26: " The " (ID: 1046 ) - Time: 3.19 s Generated token 20/26: " dog " (ID: 3924 ) - Time: 3.19 s Generated token 21/26: " looks " (ID: 3529 ) - Time: 3.15 s Generated token 22/26: " up " (ID: 550 ) - Time: 3.15 s Generated token 23/26: " and " (ID: 291 ) - Time: 3.15 s Generated token 24/26: " saw " (ID: 2815 ) - Time: 3.16 s Generated token 25/26: " the " (ID: 266 ) - Time: 3.15 s Generated text: My cat is a sound's coat. He says, "I will try!" The dog looks up and saw the
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‎arch/arm64/boot/dts/intel/Makefile‎

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@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
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socfpga_agilex_socdk.dtb \
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socfpga_agilex_socdk_atfboot.dtb \
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socfpga_agilex_socdk_nand.dtb \
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socfpga_agilex_bittware.dtb \
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socfpga_agilex5_socdk.dtb \
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socfpga_agilex_n6010.dtb \
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socfpga_agilex5_socdk.dtb \

‎arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019, Intel Corporation
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*/
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#include "socfpga_agilex_bittware.dtsi"
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#include "socfpga_agilex_pcie_root_port.dtsi"
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/ {
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model = "SoCFPGA Agilex BittWare";
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aliases {
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serial0 = &uart0;
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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ethernet2 = &gmac2;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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leds {
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compatible = "gpio-leds";
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led0 {
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label = "hps_led0";
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gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
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};
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led1 {
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label = "hps_led1";
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gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
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};
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led2 {
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label = "hps_led2";
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gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
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};
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};
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memory {
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device_type = "memory";
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/* We expect the bootloader to fill in the reg */
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reg = <0 0 0 0>;
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};
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};
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&gpio1 {
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status = "okay";
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};
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&gmac2 {
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status = "disabled";
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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max-frame-size = <9000>;
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mdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <4>;
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txd0-skew-ps = <0>; /* -420ps */
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txd1-skew-ps = <0>; /* -420ps */
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txd2-skew-ps = <0>; /* -420ps */
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txd3-skew-ps = <0>; /* -420ps */
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rxd0-skew-ps = <420>; /* 0ps */
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rxd1-skew-ps = <420>; /* 0ps */
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rxd2-skew-ps = <420>; /* 0ps */
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rxd3-skew-ps = <420>; /* 0ps */
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txen-skew-ps = <0>; /* -420ps */
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txc-skew-ps = <900>; /* 0ps */
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rxdv-skew-ps = <420>; /* 0ps */
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rxc-skew-ps = <1680>; /* 780ps */
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};
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};
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};
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&nand {
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status = "okay";
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nand-bus-width = <8>;
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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nand-bus-width = <8>;
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partition@0 {
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label = "u-boot";
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reg = <0 0x200000>;
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};
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partition@200000 {
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label = "root";
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reg = <0x200000 0x1fe00000>;
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};
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};
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};
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&osc1 {
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clock-frequency = <25000000>;
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};
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&uart0 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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disable-over-current;
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};
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&watchdog0 {
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status = "okay";
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};
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&temp_volt {
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voltage {
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#address-cells = <1>;
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#size-cells = <0>;
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input@2 {
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label = "0.8V VCC";
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reg = <2>;
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};
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input@3 {
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label = "1.8V VCCIO_SDM";
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reg = <3>;
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};
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input@4 {
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label = "1.8V VCCPT";
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reg = <4>;
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};
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input@5 {
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label = "1.2V VCCCRCORE";
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reg = <5>;
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};
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input@6 {
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label = "0.9V VCCH";
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reg = <6>;
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};
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input@7 {
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label = "0.8V VCCL";
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reg = <7>;
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};
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};
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temperature {
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#address-cells = <1>;
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#size-cells = <0>;
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input@0 {
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label = "Main Die SDM";
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reg = <0x0>;
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};
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input@10000 {
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label = "Main Die corner bottom left max";
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reg = <0x10000>;
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};
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input@20000 {
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label = "Main Die corner top left max";
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reg = <0x20000>;
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};
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input@30000 {
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label = "Main Die corner bottom right max";
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reg = <0x30000>;
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};
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input@40000 {
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label = "Main Die corner top right max";
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reg = <0x40000>;
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};
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};
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};
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&pcie_0_pcie_aglx {
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status = "okay";
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compatible = "altr,pcie-root-port-3.0-f-tile";
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};
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