chisel

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An RTL-level, Chipyard-compatible DRAM simulator model for high fidelity memory simulations.

memory chisel dram

Complete simulation environment for SiFive freedom RISCV CPU platforms

cpu chisel riscv verilog rocketchip

Test enviroment to connect jigsaw devices w/ Ibex core in CHISEL & compile the design w/ CIRCT IR to analyze the dumped SV

chisel chisel3 ibex

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