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xiaohan484xiaohan484
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20210107 decouple RISC-V Architecture Test, remove statistics.[ch]
1 parent 53798f1 commit 2bd06aa

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14 files changed

+3
-359
lines changed

14 files changed

+3
-359
lines changed

‎Makefile

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ CFLAGS += `sdl2-config --cflags`
1919
LDFLAGS += `sdl2-config --libs`
2020

2121
# Whether to enable computed goto in riscv.c
22-
ENABLE_COMPUTED_GOTO ?= 0
22+
ENABLE_COMPUTED_GOTO ?= 1
2323
ifeq ("$(ENABLE_COMPUTED_GOTO)", "1")
2424
ifneq ($(filter $(CC), gcc clang),)
2525
riscv.o: CFLAGS += -D ENABLE_COMPUTED_GOTO
@@ -56,8 +56,7 @@ OBJS = \
5656
elf.o \
5757
main.o \
5858
syscall.o \
59-
syscall_sdl.o \
60-
statistics.o
59+
syscall_sdl.o
6160

6261
deps := $(OBJS:%.o=%.o.d)
6362

‎main.c

Lines changed: 1 addition & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,6 @@
44

55
#include "elf.h"
66
#include "state.h"
7-
#include "statistics.h"
87

98
/* enable program trace mode */
109
static bool opt_trace = false;
@@ -108,9 +107,7 @@ static void print_usage(const char *filename)
108107
"Options:\n"
109108
" --trace : print executable trace\n"
110109
" --compliance [signature filename] : dump signature to the given "
111-
"file for compliance test\n"
112-
" --stats : statistics message of rv32emu: CPU cycles,jump "
113-
"counter, top 10 most frequency instruction\n",
110+
"file for compliance test\n",
114111
filename);
115112
}
116113

@@ -138,10 +135,6 @@ static bool parse_args(int argc, char **args)
138135
signature_out_file = args[++i];
139136
continue;
140137
}
141-
if (!strcmp(arg, "--stats")) {
142-
opt_stats = true;
143-
continue;
144-
}
145138
/* otherwise, error */
146139
fprintf(stderr, "Unknown argument '%s'\n", arg);
147140
return false;
@@ -235,8 +228,6 @@ int main(int argc, char **args)
235228
dump_test_signature(rv, elf);
236229
}
237230

238-
if (opt_stats)
239-
stats_information();
240231
/* finalize the RISC-V runtime */
241232
elf_delete(elf);
242233
rv_delete(rv);

‎riscv-arch-test

Lines changed: 0 additions & 1 deletion
This file was deleted.

‎riscv.c

Lines changed: 0 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,6 @@
55

66
#include "riscv.h"
77
#include "riscv_private.h"
8-
#include "statistics.h"
98

109
static void rv_except_inst_misaligned(struct riscv_t *rv, uint32_t old_pc)
1110
{
@@ -132,35 +131,30 @@ static bool op_load(struct riscv_t *rv, uint32_t inst UNUSED)
132131
switch (funct3) {
133132
case 0: // LB
134133
rv->X[rd] = sign_extend_b(rv->io.mem_read_b(rv, addr));
135-
instruction_count(LB);
136134
break;
137135
case 1: // LH
138136
if (addr & 1) {
139137
rv_except_load_misaligned(rv, addr);
140138
return false;
141139
}
142140
rv->X[rd] = sign_extend_h(rv->io.mem_read_s(rv, addr));
143-
instruction_count(LH);
144141
break;
145142
case 2: // LW
146143
if (addr & 3) {
147144
rv_except_load_misaligned(rv, addr);
148145
return false;
149146
}
150147
rv->X[rd] = rv->io.mem_read_w(rv, addr);
151-
instruction_count(LW);
152148
break;
153149
case 4: // LBU
154150
rv->X[rd] = rv->io.mem_read_b(rv, addr);
155-
instruction_count(LBU);
156151
break;
157152
case 5: // LHU
158153
if (addr & 1) {
159154
rv_except_load_misaligned(rv, addr);
160155
return false;
161156
}
162157
rv->X[rd] = rv->io.mem_read_s(rv, addr);
163-
instruction_count(LHU);
164158
break;
165159
default:
166160
rv_except_illegal_inst(rv, inst);
@@ -197,42 +191,33 @@ static bool op_op_imm(struct riscv_t *rv, uint32_t inst)
197191
switch (funct3) {
198192
case 0: // ADDI
199193
rv->X[rd] = (int32_t)(rv->X[rs1]) + imm;
200-
instruction_count(ADDI);
201194
break;
202195
case 1: // SLLI
203196
rv->X[rd] = rv->X[rs1] << (imm & 0x1f);
204-
instruction_count(SLLI);
205197
break;
206198
case 2: // SLTI
207199
rv->X[rd] = ((int32_t)(rv->X[rs1]) < imm) ? 1 : 0;
208-
instruction_count(SLTI);
209200
break;
210201
case 3: // SLTIU
211202
rv->X[rd] = (rv->X[rs1] < (uint32_t) imm) ? 1 : 0;
212-
instruction_count(SLTIU);
213203
break;
214204
case 4: // XORI
215205
rv->X[rd] = rv->X[rs1] ^ imm;
216-
instruction_count(XORI);
217206
break;
218207
case 5:
219208
if (imm & ~0x1f) {
220209
// SRAI
221210
rv->X[rd] = ((int32_t) rv->X[rs1]) >> (imm & 0x1f);
222-
instruction_count(SRAI);
223211
} else {
224212
// SRLI
225213
rv->X[rd] = rv->X[rs1] >> (imm & 0x1f);
226-
instruction_count(SRLI);
227214
}
228215
break;
229216
case 6: // ORI
230217
rv->X[rd] = rv->X[rs1] | imm;
231-
instruction_count(ORI);
232218
break;
233219
case 7: // ANDI
234220
rv->X[rd] = rv->X[rs1] & imm;
235-
instruction_count(ANDI);
236221
break;
237222
default:
238223
rv_except_illegal_inst(rv, inst);
@@ -263,7 +248,6 @@ static bool op_auipc(struct riscv_t *rv, uint32_t inst)
263248
if (rd == rv_reg_zero)
264249
rv->X[rv_reg_zero] = 0;
265250

266-
instruction_count(AUIPC);
267251
return true;
268252
}
269253

@@ -283,23 +267,20 @@ static bool op_store(struct riscv_t *rv, uint32_t inst)
283267
switch (funct3) {
284268
case 0: // SB
285269
rv->io.mem_write_b(rv, addr, data);
286-
instruction_count(SB);
287270
break;
288271
case 1: // SH
289272
if (addr & 1) {
290273
rv_except_store_misaligned(rv, addr);
291274
return false;
292275
}
293276
rv->io.mem_write_s(rv, addr, data);
294-
instruction_count(SH);
295277
break;
296278
case 2: // SW
297279
if (addr & 3) {
298280
rv_except_store_misaligned(rv, addr);
299281
return false;
300282
}
301283
rv->io.mem_write_w(rv, addr, data);
302-
instruction_count(SW);
303284
break;
304285
default:
305286
rv_except_illegal_inst(rv, inst);
@@ -327,35 +308,27 @@ static bool op_op(struct riscv_t *rv, uint32_t inst)
327308
switch (funct3) {
328309
case 0b000: // ADD
329310
rv->X[rd] = (int32_t)(rv->X[rs1]) + (int32_t)(rv->X[rs2]);
330-
instruction_count(ADD);
331311
break;
332312
case 0b001: // SLL
333313
rv->X[rd] = rv->X[rs1] << (rv->X[rs2] & 0x1f);
334-
instruction_count(SLL);
335314
break;
336315
case 0b010: // SLT
337316
rv->X[rd] = ((int32_t)(rv->X[rs1]) < (int32_t)(rv->X[rs2])) ? 1 : 0;
338-
instruction_count(SLT);
339317
break;
340318
case 0b011: // SLTU
341319
rv->X[rd] = (rv->X[rs1] < rv->X[rs2]) ? 1 : 0;
342-
instruction_count(SLTU);
343320
break;
344321
case 0b100: // XOR
345322
rv->X[rd] = rv->X[rs1] ^ rv->X[rs2];
346-
instruction_count(XOR);
347323
break;
348324
case 0b101: // SRL
349325
rv->X[rd] = rv->X[rs1] >> (rv->X[rs2] & 0x1f);
350-
instruction_count(SRL);
351326
break;
352327
case 0b110: // OR
353328
rv->X[rd] = rv->X[rs1] | rv->X[rs2];
354-
instruction_count(OR);
355329
break;
356330
case 0b111: // AND
357331
rv->X[rd] = rv->X[rs1] & rv->X[rs2];
358-
instruction_count(AND);
359332
break;
360333
default:
361334
rv_except_illegal_inst(rv, inst);
@@ -368,23 +341,19 @@ static bool op_op(struct riscv_t *rv, uint32_t inst)
368341
switch (funct3) {
369342
case 0b000: // MUL
370343
rv->X[rd] = (int32_t) rv->X[rs1] * (int32_t) rv->X[rs2];
371-
instruction_count(MUL);
372344
break;
373345
case 0b001: { // MULH
374346
const int64_t a = (int32_t) rv->X[rs1];
375347
const int64_t b = (int32_t) rv->X[rs2];
376348
rv->X[rd] = ((uint64_t)(a * b)) >> 32;
377-
instruction_count(MULH);
378349
} break;
379350
case 0b010: { // MULHSU
380351
const int64_t a = (int32_t) rv->X[rs1];
381352
const uint64_t b = rv->X[rs2];
382353
rv->X[rd] = ((uint64_t)(a * b)) >> 32;
383-
instruction_count(MULHSU);
384354
} break;
385355
case 0b011: // MULHU
386356
rv->X[rd] = ((uint64_t) rv->X[rs1] * (uint64_t) rv->X[rs2]) >> 32;
387-
instruction_count(MULHU);
388357
break;
389358
case 0b100: { // DIV
390359
const int32_t dividend = (int32_t) rv->X[rs1];
@@ -396,7 +365,6 @@ static bool op_op(struct riscv_t *rv, uint32_t inst)
396365
} else {
397366
rv->X[rd] = dividend / divisor;
398367
}
399-
instruction_count(DIV);
400368
} break;
401369
case 0b101: { // DIVU
402370
const uint32_t dividend = rv->X[rs1];
@@ -406,7 +374,6 @@ static bool op_op(struct riscv_t *rv, uint32_t inst)
406374
} else {
407375
rv->X[rd] = dividend / divisor;
408376
}
409-
instruction_count(DIVU);
410377
} break;
411378
case 0b110: { // REM
412379
const int32_t dividend = rv->X[rs1];
@@ -418,7 +385,6 @@ static bool op_op(struct riscv_t *rv, uint32_t inst)
418385
} else {
419386
rv->X[rd] = dividend % divisor;
420387
}
421-
instruction_count(REM);
422388
} break;
423389
case 0b111: { // REMU
424390
const uint32_t dividend = rv->X[rs1];
@@ -428,7 +394,6 @@ static bool op_op(struct riscv_t *rv, uint32_t inst)
428394
} else {
429395
rv->X[rd] = dividend % divisor;
430396
}
431-
instruction_count(REMU);
432397
} break;
433398
default:
434399
rv_except_illegal_inst(rv, inst);
@@ -440,11 +405,9 @@ static bool op_op(struct riscv_t *rv, uint32_t inst)
440405
switch (funct3) {
441406
case 0b000: // SUB
442407
rv->X[rd] = (int32_t)(rv->X[rs1]) - (int32_t)(rv->X[rs2]);
443-
instruction_count(SUB);
444408
break;
445409
case 0b101: // SRA
446410
rv->X[rd] = ((int32_t) rv->X[rs1]) >> (rv->X[rs2] & 0x1f);
447-
instruction_count(SRA);
448411
break;
449412
default:
450413
rv_except_illegal_inst(rv, inst);
@@ -476,7 +439,6 @@ static bool op_lui(struct riscv_t *rv, uint32_t inst)
476439
// enforce zero register
477440
if (rd == rv_reg_zero)
478441
rv->X[rv_reg_zero] = 0;
479-
instruction_count(LUI);
480442
return true;
481443
}
482444

@@ -488,7 +450,6 @@ static bool op_branch(struct riscv_t *rv, uint32_t inst)
488450
const int32_t imm = dec_btype_imm(inst);
489451
const uint32_t rs1 = dec_rs1(inst);
490452
const uint32_t rs2 = dec_rs2(inst);
491-
branch_count();
492453

493454

494455
// track if branch is taken or not
@@ -498,28 +459,22 @@ static bool op_branch(struct riscv_t *rv, uint32_t inst)
498459
switch (func3) {
499460
case 0: // BEQ
500461
taken = (rv->X[rs1] == rv->X[rs2]);
501-
instruction_count(BEQ);
502462

503463
break;
504464
case 1: // BNE
505465
taken = (rv->X[rs1] != rv->X[rs2]);
506-
instruction_count(BNE);
507466
break;
508467
case 4: // BLT
509468
taken = ((int32_t) rv->X[rs1] < (int32_t) rv->X[rs2]);
510-
instruction_count(BLT);
511469
break;
512470
case 5: // BGE
513471
taken = ((int32_t) rv->X[rs1] >= (int32_t) rv->X[rs2]);
514-
instruction_count(BGE);
515472
break;
516473
case 6: // BLTU
517474
taken = (rv->X[rs1] < rv->X[rs2]);
518-
instruction_count(BLTU);
519475
break;
520476
case 7: // BGEU
521477
taken = (rv->X[rs1] >= rv->X[rs2]);
522-
instruction_count(BGEU);
523478
break;
524479
default:
525480
rv_except_illegal_inst(rv, inst);
@@ -528,7 +483,6 @@ static bool op_branch(struct riscv_t *rv, uint32_t inst)
528483
// perform branch action
529484
if (taken) {
530485
rv->PC += imm;
531-
jump_count(imm);
532486
if (rv->PC & 0x3)
533487
rv_except_inst_misaligned(rv, pc);
534488
} else {
@@ -550,10 +504,8 @@ static bool op_jalr(struct riscv_t *rv, uint32_t inst)
550504

551505
// compute return address
552506
const uint32_t ra = rv->PC + rv->inst_len;
553-
branch_count();
554507

555508
// jump
556-
jalr_jump_count(rv->PC, (rv->X[rs1] + imm) & ~1u);
557509
rv->PC = (rv->X[rs1] + imm) & ~1u;
558510

559511
// link
@@ -571,7 +523,6 @@ static bool op_jalr(struct riscv_t *rv, uint32_t inst)
571523
}
572524
// can branch
573525

574-
instruction_count(JALR);
575526
return false;
576527
}
577528

@@ -585,7 +536,6 @@ static bool op_jal(struct riscv_t *rv, uint32_t inst)
585536
// compute return address
586537
const uint32_t ra = rv->PC + rv->inst_len;
587538
rv->PC += rel;
588-
jump_count(rel);
589539

590540
// link
591541
if (rd != rv_reg_zero)
@@ -601,7 +551,6 @@ static bool op_jal(struct riscv_t *rv, uint32_t inst)
601551
return false;
602552
}
603553
// can branch
604-
instruction_count(JAL);
605554
return false;
606555
}
607556

@@ -1354,7 +1303,6 @@ void rv_step(struct riscv_t *rv, int32_t cycles)
13541303
assert(rv);
13551304
const uint64_t cycles_target = rv->csr_cycle + cycles;
13561305
uint32_t inst = 0;
1357-
uint32_t buffer = 0;
13581306
// clang-format off
13591307
#define OP_UNIMP op_unimp
13601308
#ifdef ENABLE_COMPUTED_GOTO
@@ -1398,14 +1346,12 @@ void rv_step(struct riscv_t *rv, int32_t cycles)
13981346
if ((inst & 3) == 3) { \
13991347
uint32_t index = (inst & INST_6_2) >> 2; \
14001348
rv->inst_len = INST_32; \
1401-
cycle_count(); \
14021349
goto *jump_table[index]; \
14031350
} else { \
14041351
/* Compressed Extension Instruction */ \
14051352
inst &= 0x0000FFFF; \
14061353
int16_t c_index = (inst & FC_FUNC3) >> 11 | (inst & FC_OPCODE); \
14071354
rv->inst_len = INST_16; \
1408-
cycle_count(); \
14091355
goto *jump_tablec[c_index]; \
14101356
} \
14111357
}

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