[AArch64] Expand MI->getOperand(1).getImm() with 0 literal (llvm#154598)

tomershafir · tomershafir · commit e4e279cd0400 · 2025-11-11T10:12:12.000+02:00
`MI->getOperand(1).getImm()` has already been verified to be 0 entering the block. (cherry-pick 769d5c2)
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -2952,7 +2952,7 @@ void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) {
       MCInst TmpInst;
       TmpInst.setOpcode(AArch64::MOVIv16b_ns);
       TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
-      TmpInst.addOperand(MCOperand::createImm(MI->getOperand(1).getImm()));
+      TmpInst.addOperand(MCOperand::createImm(0));
       EmitToStreamer(*OutStreamer, TmpInst);
       return;
     }

Original file line number	Diff line number	Diff line change
`@@ -2952,7 +2952,7 @@ void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) {`
`2952`	`2952`	`MCInst TmpInst;`
`2953`	`2953`	`TmpInst.setOpcode(AArch64::MOVIv16b_ns);`
`2954`	`2954`	`TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));`
`2955`		`- TmpInst.addOperand(MCOperand::createImm(MI->getOperand(1).getImm()));`
	`2955`	`+ TmpInst.addOperand(MCOperand::createImm(0));`
`2956`	`2956`	`EmitToStreamer(*OutStreamer, TmpInst);`
`2957`	`2957`	`return;`
`2958`	`2958`	`}`