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nitinjohnrajnitinjohnraj
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[RISCV] Made division pseudoinstructions SEW-aware
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-57
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4 files changed

+322
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‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td‎

Lines changed: 83 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -2033,6 +2033,10 @@ multiclass VPseudoBinaryFV_VV<LMULInfo m, string Constraint = ""> {
20332033
defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
20342034
}
20352035

2036+
multiclass VPseudoBinaryFV_VV_E<LMULInfo m, int sew, string Constraint = ""> {
2037+
defm _VV : VPseudoBinary_E<m.vrclass, m.vrclass, m.vrclass, m, sew, Constraint>;
2038+
}
2039+
20362040
multiclass VPseudoVGTR_VV_EEW<int eew, string Constraint = ""> {
20372041
foreach m = MxList in {
20382042
defvar mx = m.MX;
@@ -2060,6 +2064,10 @@ multiclass VPseudoBinaryV_VX<LMULInfo m, string Constraint = ""> {
20602064
defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>;
20612065
}
20622066

2067+
multiclass VPseudoBinaryV_VX_E<LMULInfo m, int sew, string Constraint = ""> {
2068+
defm "_VX" : VPseudoBinary_E<m.vrclass, m.vrclass, GPR, m, sew, Constraint>;
2069+
}
2070+
20632071
multiclass VPseudoVSLD1_VX<string Constraint = ""> {
20642072
foreach m = MxList in {
20652073
defvar mx = m.MX;
@@ -2077,6 +2085,12 @@ multiclass VPseudoBinaryV_VF<LMULInfo m, FPR_Info f, string Constraint = ""> {
20772085
f.fprclass, m, Constraint>;
20782086
}
20792087

2088+
multiclass VPseudoBinaryV_VF_E<LMULInfo m, int sew, FPR_Info f,
2089+
string Constraint = ""> {
2090+
defm "_V" # f.FX : VPseudoBinary_E<m.vrclass, m.vrclass,
2091+
f.fprclass, m, sew, Constraint>;
2092+
}
2093+
20802094
multiclass VPseudoVSLD1_VF<string Constraint = ""> {
20812095
foreach f = FPList in {
20822096
foreach m = f.MxList in {
@@ -2621,15 +2635,18 @@ multiclass VPseudoVMUL_VV_VX {
26212635
multiclass VPseudoVDIV_VV_VX {
26222636
foreach m = MxList in {
26232637
defvar mx = m.MX;
2624-
defvar WriteVIDivV_MX = !cast<SchedWrite>("WriteVIDivV_" # mx);
2625-
defvar WriteVIDivX_MX = !cast<SchedWrite>("WriteVIDivX_" # mx);
2626-
defvar ReadVIDivV_MX = !cast<SchedRead>("ReadVIDivV_" # mx);
2627-
defvar ReadVIDivX_MX = !cast<SchedRead>("ReadVIDivX_" # mx);
2628-
2629-
defm "" : VPseudoBinaryV_VV<m>,
2630-
Sched<[WriteVIDivV_MX, ReadVIDivV_MX, ReadVIDivV_MX, ReadVMask]>;
2631-
defm "" : VPseudoBinaryV_VX<m>,
2632-
Sched<[WriteVIDivX_MX, ReadVIDivV_MX, ReadVIDivX_MX, ReadVMask]>;
2638+
defvar sews = SchedSEWSet<mx>.val;
2639+
foreach e = sews in {
2640+
defvar WriteVIDivV_MX_E = !cast<SchedWrite>("WriteVIDivV_" # mx # "_E" # e);
2641+
defvar WriteVIDivX_MX_E = !cast<SchedWrite>("WriteVIDivX_" # mx # "_E" # e);
2642+
defvar ReadVIDivV_MX_E = !cast<SchedRead>("ReadVIDivV_" # mx # "_E" # e);
2643+
defvar ReadVIDivX_MX_E = !cast<SchedRead>("ReadVIDivX_" # mx # "_E" # e);
2644+
2645+
defm "" : VPseudoBinaryV_VV_E<m, e>,
2646+
Sched<[WriteVIDivV_MX_E, ReadVIDivV_MX_E, ReadVIDivV_MX_E, ReadVMask]>;
2647+
defm "" : VPseudoBinaryV_VX_E<m, e>,
2648+
Sched<[WriteVIDivX_MX_E, ReadVIDivV_MX_E, ReadVIDivX_MX_E, ReadVMask]>;
2649+
}
26332650
}
26342651
}
26352652

@@ -2659,22 +2676,28 @@ multiclass VPseudoVFMUL_VV_VF {
26592676
multiclass VPseudoVFDIV_VV_VF {
26602677
foreach m = MxListF in {
26612678
defvar mx = m.MX;
2662-
defvar WriteVFDivV_MX = !cast<SchedWrite>("WriteVFDivV_" # mx);
2663-
defvar ReadVFDivV_MX = !cast<SchedRead>("ReadVFDivV_" # mx);
2679+
defvar sews = SchedSEWSet<mx>.val;
2680+
foreach e = sews in {
2681+
defvar WriteVFDivV_MX_E = !cast<SchedWrite>("WriteVFDivV_" # mx # "_E" # e);
2682+
defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
26642683

2665-
defm "" : VPseudoBinaryFV_VV<m>,
2666-
Sched<[WriteVFDivV_MX, ReadVFDivV_MX, ReadVFDivV_MX, ReadVMask]>;
2684+
defm "" : VPseudoBinaryFV_VV_E<m, e>,
2685+
Sched<[WriteVFDivV_MX_E, ReadVFDivV_MX_E, ReadVFDivV_MX_E, ReadVMask]>;
2686+
}
26672687
}
26682688

26692689
foreach f = FPList in {
26702690
foreach m = f.MxList in {
26712691
defvar mx = m.MX;
2672-
defvar WriteVFDivF_MX = !cast<SchedWrite>("WriteVFDivF_" # mx);
2673-
defvar ReadVFDivV_MX = !cast<SchedRead>("ReadVFDivV_" # mx);
2674-
defvar ReadVFDivF_MX = !cast<SchedRead>("ReadVFDivF_" # mx);
2692+
defvar sews = SchedSEWSet<mx>.val;
2693+
foreach e = sews in {
2694+
defvar WriteVFDivF_MX_E = !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # e);
2695+
defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
2696+
defvar ReadVFDivF_MX_E = !cast<SchedRead>("ReadVFDivF_" # mx # "_E" # e);
26752697

2676-
defm "" : VPseudoBinaryV_VF<m, f>,
2677-
Sched<[WriteVFDivF_MX, ReadVFDivV_MX, ReadVFDivF_MX, ReadVMask]>;
2698+
defm "" : VPseudoBinaryV_VF_E<m, e, f>,
2699+
Sched<[WriteVFDivF_MX_E, ReadVFDivV_MX_E, ReadVFDivF_MX_E, ReadVMask]>;
2700+
}
26782701
}
26792702
}
26802703
}
@@ -2683,11 +2706,15 @@ multiclass VPseudoVFRDIV_VF {
26832706
foreach f = FPList in {
26842707
foreach m = f.MxList in {
26852708
defvar mx = m.MX;
2686-
defvar WriteVFDivF_MX = !cast<SchedWrite>("WriteVFDivF_" # mx);
2687-
defvar ReadVFDivV_MX = !cast<SchedRead>("ReadVFDivV_" # mx);
2688-
defvar ReadVFDivF_MX = !cast<SchedRead>("ReadVFDivF_" # mx);
2689-
defm "" : VPseudoBinaryV_VF<m, f>,
2690-
Sched<[WriteVFDivF_MX, ReadVFDivV_MX, ReadVFDivF_MX, ReadVMask]>;
2709+
defvar sews = SchedSEWSet<mx>.val;
2710+
foreach e = sews in {
2711+
defvar WriteVFDivF_MX_E = !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # e);
2712+
defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
2713+
defvar ReadVFDivF_MX_E = !cast<SchedRead>("ReadVFDivF_" # mx # "_E" # e);
2714+
2715+
defm "" : VPseudoBinaryV_VF_E<m, e, f>,
2716+
Sched<[WriteVFDivF_MX_E, ReadVFDivV_MX_E, ReadVFDivF_MX_E, ReadVMask]>;
2717+
}
26912718
}
26922719
}
26932720
}
@@ -4503,6 +4530,16 @@ multiclass VPatBinaryV_VV<string intrinsic, string instruction,
45034530
vti.RegClass, vti.RegClass>;
45044531
}
45054532

4533+
multiclass VPatBinaryV_VV_E<string intrinsic, string instruction,
4534+
list<VTypeInfo> vtilist> {
4535+
foreach vti = vtilist in
4536+
defm : VPatBinaryTA<intrinsic,
4537+
instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW,
4538+
vti.Vector, vti.Vector, vti.Vector,vti.Mask,
4539+
vti.Log2SEW, vti.RegClass,
4540+
vti.RegClass, vti.RegClass>;
4541+
}
4542+
45064543
multiclass VPatBinaryV_VV_INT_E<string intrinsic, string instruction,
45074544
list<VTypeInfo> vtilist> {
45084545
foreach vti = vtilist in {
@@ -4545,6 +4582,18 @@ multiclass VPatBinaryV_VX<string intrinsic, string instruction,
45454582
}
45464583
}
45474584

4585+
multiclass VPatBinaryV_VX_E<string intrinsic, string instruction,
4586+
list<VTypeInfo> vtilist> {
4587+
foreach vti = vtilist in {
4588+
defvar kind = "V"#vti.ScalarSuffix;
4589+
defm : VPatBinaryTA<intrinsic,
4590+
instruction#"_"#kind#"_"#vti.LMul.MX#"_E"#vti.SEW,
4591+
vti.Vector, vti.Vector, vti.Scalar, vti.Mask,
4592+
vti.Log2SEW, vti.RegClass,
4593+
vti.RegClass, vti.ScalarRegClass>;
4594+
}
4595+
}
4596+
45484597
multiclass VPatBinaryV_VX_INT<string intrinsic, string instruction,
45494598
list<VTypeInfo> vtilist> {
45504599
foreach vti = vtilist in
@@ -4810,6 +4859,11 @@ multiclass VPatBinaryV_VV_VX<string intrinsic, string instruction,
48104859
: VPatBinaryV_VV<intrinsic, instruction, vtilist>,
48114860
VPatBinaryV_VX<intrinsic, instruction, vtilist>;
48124861

4862+
multiclass VPatBinaryV_VV_VX_E<string intrinsic, string instruction,
4863+
list<VTypeInfo> vtilist>
4864+
: VPatBinaryV_VV_E<intrinsic, instruction, vtilist>,
4865+
VPatBinaryV_VX_E<intrinsic, instruction, vtilist>;
4866+
48134867
multiclass VPatBinaryV_VX_VI<string intrinsic, string instruction,
48144868
list<VTypeInfo> vtilist>
48154869
: VPatBinaryV_VX<intrinsic, instruction, vtilist>,
@@ -6091,10 +6145,10 @@ defm : VPatBinaryV_VV_VX<"int_riscv_vmulhsu", "PseudoVMULHSU", AllIntegerVectors
60916145
//===----------------------------------------------------------------------===//
60926146
// 11.11. Vector Integer Divide Instructions
60936147
//===----------------------------------------------------------------------===//
6094-
defm : VPatBinaryV_VV_VX<"int_riscv_vdivu", "PseudoVDIVU", AllIntegerVectors>;
6095-
defm : VPatBinaryV_VV_VX<"int_riscv_vdiv", "PseudoVDIV", AllIntegerVectors>;
6096-
defm : VPatBinaryV_VV_VX<"int_riscv_vremu", "PseudoVREMU", AllIntegerVectors>;
6097-
defm : VPatBinaryV_VV_VX<"int_riscv_vrem", "PseudoVREM", AllIntegerVectors>;
6148+
defm : VPatBinaryV_VV_VX_E<"int_riscv_vdivu", "PseudoVDIVU", AllIntegerVectors>;
6149+
defm : VPatBinaryV_VV_VX_E<"int_riscv_vdiv", "PseudoVDIV", AllIntegerVectors>;
6150+
defm : VPatBinaryV_VV_VX_E<"int_riscv_vremu", "PseudoVREMU", AllIntegerVectors>;
6151+
defm : VPatBinaryV_VV_VX_E<"int_riscv_vrem", "PseudoVREM", AllIntegerVectors>;
60986152

60996153
//===----------------------------------------------------------------------===//
61006154
// 11.12. Vector Widening Integer Multiply Instructions
@@ -6207,8 +6261,8 @@ defm : VPatBinaryW_WV_WX<"int_riscv_vfwsub_w", "PseudoVFWSUB", AllWidenableFloat
62076261
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
62086262
//===----------------------------------------------------------------------===//
62096263
defm : VPatBinaryV_VV_VX<"int_riscv_vfmul", "PseudoVFMUL", AllFloatVectors>;
6210-
defm : VPatBinaryV_VV_VX<"int_riscv_vfdiv", "PseudoVFDIV", AllFloatVectors>;
6211-
defm : VPatBinaryV_VX<"int_riscv_vfrdiv", "PseudoVFRDIV", AllFloatVectors>;
6264+
defm : VPatBinaryV_VV_VX_E<"int_riscv_vfdiv", "PseudoVFDIV", AllFloatVectors>;
6265+
defm : VPatBinaryV_VX_E<"int_riscv_vfrdiv", "PseudoVFRDIV", AllFloatVectors>;
62126266

62136267
//===----------------------------------------------------------------------===//
62146268
// 13.5. Vector Widening Floating-Point Multiply

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td‎

Lines changed: 98 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,23 @@ class VPatBinarySDNode_VV<SDPatternOperator vop,
8888
op_reg_class:$rs2,
8989
avl, sew)>;
9090

91+
class VPatBinarySDNode_VV_E<SDPatternOperator vop,
92+
string instruction_name,
93+
ValueType result_type,
94+
ValueType op_type,
95+
int log2sew,
96+
LMULInfo vlmul,
97+
int sew,
98+
OutPatFrag avl,
99+
VReg op_reg_class> :
100+
Pat<(result_type (vop
101+
(op_type op_reg_class:$rs1),
102+
(op_type op_reg_class:$rs2))),
103+
(!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX#"_E"#sew)
104+
op_reg_class:$rs1,
105+
op_reg_class:$rs2,
106+
avl, log2sew)>;
107+
91108
class VPatBinarySDNode_XI<SDPatternOperator vop,
92109
string instruction_name,
93110
string suffix,
@@ -107,6 +124,26 @@ class VPatBinarySDNode_XI<SDPatternOperator vop,
107124
xop_kind:$rs2,
108125
avl, sew)>;
109126

127+
class VPatBinarySDNode_XI_E<SDPatternOperator vop,
128+
string instruction_name,
129+
string suffix,
130+
ValueType result_type,
131+
ValueType vop_type,
132+
int log2sew,
133+
LMULInfo vlmul,
134+
int sew,
135+
OutPatFrag avl,
136+
VReg vop_reg_class,
137+
ComplexPattern SplatPatKind,
138+
DAGOperand xop_kind> :
139+
Pat<(result_type (vop
140+
(vop_type vop_reg_class:$rs1),
141+
(vop_type (SplatPatKind xop_kind:$rs2)))),
142+
(!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX#"_E"#sew)
143+
vop_reg_class:$rs1,
144+
xop_kind:$rs2,
145+
avl, log2sew)>;
146+
110147
multiclass VPatBinarySDNode_VV_VX<SDPatternOperator vop, string instruction_name> {
111148
foreach vti = AllIntegerVectors in {
112149
def : VPatBinarySDNode_VV<vop, instruction_name,
@@ -119,6 +156,19 @@ multiclass VPatBinarySDNode_VV_VX<SDPatternOperator vop, string instruction_name
119156
}
120157
}
121158

159+
multiclass VPatBinarySDNode_VV_VX_E<SDPatternOperator vop,
160+
string instruction_name> {
161+
foreach vti = AllIntegerVectors in {
162+
def : VPatBinarySDNode_VV_E<vop, instruction_name,
163+
vti.Vector, vti.Vector, vti.Log2SEW,
164+
vti.LMul, vti.SEW, vti.AVL, vti.RegClass>;
165+
def : VPatBinarySDNode_XI_E<vop, instruction_name, "VX",
166+
vti.Vector, vti.Vector, vti.Log2SEW,
167+
vti.LMul, vti.SEW, vti.AVL, vti.RegClass,
168+
SplatPat, GPR>;
169+
}
170+
}
171+
122172
multiclass VPatBinarySDNode_VV_VX_VI<SDPatternOperator vop, string instruction_name,
123173
Operand ImmType = simm5>
124174
: VPatBinarySDNode_VV_VX<vop, instruction_name> {
@@ -148,6 +198,24 @@ class VPatBinarySDNode_VF<SDPatternOperator vop,
148198
(xop_type xop_kind:$rs2),
149199
avl, sew)>;
150200

201+
class VPatBinarySDNode_VF_E<SDPatternOperator vop,
202+
string instruction_name,
203+
ValueType result_type,
204+
ValueType vop_type,
205+
ValueType xop_type,
206+
int log2sew,
207+
LMULInfo vlmul,
208+
int sew,
209+
OutPatFrag avl,
210+
VReg vop_reg_class,
211+
DAGOperand xop_kind> :
212+
Pat<(result_type (vop (vop_type vop_reg_class:$rs1),
213+
(vop_type (SplatFPOp xop_kind:$rs2)))),
214+
(!cast<Instruction>(instruction_name#"_"#vlmul.MX#"_E"#sew)
215+
vop_reg_class:$rs1,
216+
(xop_type xop_kind:$rs2),
217+
avl, log2sew)>;
218+
151219
multiclass VPatBinaryFPSDNode_VV_VF<SDPatternOperator vop, string instruction_name> {
152220
foreach vti = AllFloatVectors in {
153221
def : VPatBinarySDNode_VV<vop, instruction_name,
@@ -160,6 +228,19 @@ multiclass VPatBinaryFPSDNode_VV_VF<SDPatternOperator vop, string instruction_na
160228
}
161229
}
162230

231+
multiclass VPatBinaryFPSDNode_VV_VF_E<SDPatternOperator vop,
232+
string instruction_name> {
233+
foreach vti = AllFloatVectors in {
234+
def : VPatBinarySDNode_VV_E<vop, instruction_name,
235+
vti.Vector, vti.Vector, vti.Log2SEW,
236+
vti.LMul, vti.SEW, vti.AVL, vti.RegClass>;
237+
def : VPatBinarySDNode_VF_E<vop, instruction_name#"_V"#vti.ScalarSuffix,
238+
vti.Vector, vti.Vector, vti.Scalar,
239+
vti.Log2SEW, vti.LMul, vti.SEW, vti.AVL,
240+
vti.RegClass, vti.ScalarRegClass>;
241+
}
242+
}
243+
163244
multiclass VPatBinaryFPSDNode_R_VF<SDPatternOperator vop, string instruction_name> {
164245
foreach fvti = AllFloatVectors in
165246
def : Pat<(fvti.Vector (vop (fvti.Vector (SplatFPOp fvti.Scalar:$rs2)),
@@ -170,6 +251,17 @@ multiclass VPatBinaryFPSDNode_R_VF<SDPatternOperator vop, string instruction_nam
170251
fvti.AVL, fvti.Log2SEW)>;
171252
}
172253

254+
multiclass VPatBinaryFPSDNode_R_VF_E<SDPatternOperator vop,
255+
string instruction_name> {
256+
foreach fvti = AllFloatVectors in
257+
def : Pat<(fvti.Vector (vop (fvti.Vector (SplatFPOp fvti.Scalar:$rs2)),
258+
(fvti.Vector fvti.RegClass:$rs1))),
259+
(!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW)
260+
fvti.RegClass:$rs1,
261+
(fvti.Scalar fvti.ScalarRegClass:$rs2),
262+
fvti.AVL, fvti.Log2SEW)>;
263+
}
264+
173265
multiclass VPatIntegerSetCCSDNode_VV<string instruction_name,
174266
CondCode cc> {
175267
foreach vti = AllIntegerVectors in {
@@ -723,10 +815,10 @@ defm : VPatBinarySDNode_VV_VX<mulhs, "PseudoVMULH">;
723815
defm : VPatBinarySDNode_VV_VX<mulhu, "PseudoVMULHU">;
724816

725817
// 11.11. Vector Integer Divide Instructions
726-
defm : VPatBinarySDNode_VV_VX<udiv, "PseudoVDIVU">;
727-
defm : VPatBinarySDNode_VV_VX<sdiv, "PseudoVDIV">;
728-
defm : VPatBinarySDNode_VV_VX<urem, "PseudoVREMU">;
729-
defm : VPatBinarySDNode_VV_VX<srem, "PseudoVREM">;
818+
defm : VPatBinarySDNode_VV_VX_E<udiv, "PseudoVDIVU">;
819+
defm : VPatBinarySDNode_VV_VX_E<sdiv, "PseudoVDIV">;
820+
defm : VPatBinarySDNode_VV_VX_E<urem, "PseudoVREMU">;
821+
defm : VPatBinarySDNode_VV_VX_E<srem, "PseudoVREM">;
730822

731823
// 11.12. Vector Widening Integer Multiply Instructions
732824
defm : VPatWidenBinarySDNode_VV_VX<mul, sext_oneuse, sext_oneuse,
@@ -836,8 +928,8 @@ defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF<fsub, "PseudoVFWSUB">;
836928

837929
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
838930
defm : VPatBinaryFPSDNode_VV_VF<any_fmul, "PseudoVFMUL">;
839-
defm : VPatBinaryFPSDNode_VV_VF<any_fdiv, "PseudoVFDIV">;
840-
defm : VPatBinaryFPSDNode_R_VF<any_fdiv, "PseudoVFRDIV">;
931+
defm : VPatBinaryFPSDNode_VV_VF_E<any_fdiv, "PseudoVFDIV">;
932+
defm : VPatBinaryFPSDNode_R_VF_E<any_fdiv, "PseudoVFRDIV">;
841933

842934
// 13.5. Vector Widening Floating-Point Multiply Instructions
843935
defm : VPatWidenBinaryFPSDNode_VV_VF<fmul, "PseudoVFWMUL">;

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