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ARM: move feature for Thumb2 pkhbt/pkhtb onto architectures.
There's not much functional change, but it really is an architectural feature (on v6T2, v7A, v7R and v7EM) rather than something each CPU implements individually. The main functional change is the default behaviour you get when specifying only "-triple". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276013 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/ARM/ARM.td‎

Lines changed: 14 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -295,7 +295,8 @@ def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
295295
FeatureV7Clrex]>;
296296
def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
297297
"Support ARM v8 instructions",
298-
[HasV7Ops, FeatureAcquireRelease]>;
298+
[HasV7Ops, FeatureAcquireRelease,
299+
FeatureT2XtPk]>;
299300
def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
300301
"Support ARM v8.1a instructions",
301302
[HasV8Ops]>;
@@ -388,7 +389,8 @@ def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>;
388389
def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>;
389390

390391
def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops,
391-
FeatureDSP]>;
392+
FeatureDSP,
393+
FeatureT2XtPk]>;
392394

393395
def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>;
394396

@@ -409,13 +411,15 @@ def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops,
409411
FeatureNEON,
410412
FeatureDB,
411413
FeatureDSP,
412-
FeatureAClass]>;
414+
FeatureAClass,
415+
FeatureT2XtPk]>;
413416

414417
def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
415418
FeatureDB,
416419
FeatureDSP,
417420
FeatureHWDiv,
418-
FeatureRClass]>;
421+
FeatureRClass,
422+
FeatureT2XtPk]>;
419423

420424
def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
421425
FeatureThumb2,
@@ -570,7 +574,6 @@ def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5,
570574
FeatureSlowFPBrcc,
571575
FeatureHasSlowFPVMLx,
572576
FeatureVMLxForwarding,
573-
FeatureT2XtPk,
574577
FeatureMP,
575578
FeatureVFP4]>;
576579

@@ -581,7 +584,6 @@ def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7,
581584
FeatureHasVMLxHazards,
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FeatureHasSlowFPVMLx,
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FeatureVMLxForwarding,
584-
FeatureT2XtPk,
585587
FeatureMP,
586588
FeatureVFP4,
587589
FeatureHWDiv,
@@ -595,15 +597,13 @@ def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8,
595597
FeatureSlowFPBrcc,
596598
FeatureHasVMLxHazards,
597599
FeatureHasSlowFPVMLx,
598-
FeatureVMLxForwarding,
599-
FeatureT2XtPk]>;
600+
FeatureVMLxForwarding]>;
600601

601602
def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,
602603
FeatureHasRetAddrStack,
603604
FeatureTrustZone,
604605
FeatureHasVMLxHazards,
605606
FeatureVMLxForwarding,
606-
FeatureT2XtPk,
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FeatureFP16,
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FeatureAvoidPartialCPSR,
609609
FeatureExpandMLx,
@@ -618,7 +618,6 @@ def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12,
618618
FeatureHasRetAddrStack,
619619
FeatureTrustZone,
620620
FeatureVMLxForwarding,
621-
FeatureT2XtPk,
622621
FeatureVFP4,
623622
FeatureHWDiv,
624623
FeatureHWDivARM,
@@ -632,7 +631,6 @@ def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15,
632631
FeatureHasRetAddrStack,
633632
FeatureMuxedUnits,
634633
FeatureTrustZone,
635-
FeatureT2XtPk,
636634
FeatureVFP4,
637635
FeatureMP,
638636
FeatureCheckVLDnAlign,
@@ -647,7 +645,6 @@ def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17,
647645
FeatureTrustZone,
648646
FeatureMP,
649647
FeatureVMLxForwarding,
650-
FeatureT2XtPk,
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FeatureVFP4,
652649
FeatureHWDiv,
653650
FeatureHWDivARM,
@@ -662,7 +659,6 @@ def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
662659
FeatureMuxedUnits,
663660
FeatureCheckVLDnAlign,
664661
FeatureVMLxForwarding,
665-
FeatureT2XtPk,
666662
FeatureFP16,
667663
FeatureAvoidPartialCPSR,
668664
FeatureVFP4,
@@ -672,7 +668,6 @@ def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
672668
def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
673669
FeatureHasRetAddrStack,
674670
FeatureNEONForFP,
675-
FeatureT2XtPk,
676671
FeatureVFP4,
677672
FeatureMP,
678673
FeatureHWDiv,
@@ -691,8 +686,7 @@ def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
691686
// FIXME: R4 has currently the same ProcessorModel as A8.
692687
def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
693688
FeatureHasRetAddrStack,
694-
FeatureAvoidPartialCPSR,
695-
FeatureT2XtPk]>;
689+
FeatureAvoidPartialCPSR]>;
696690

697691
// FIXME: R4F has currently the same ProcessorModel as A8.
698692
def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
@@ -701,8 +695,7 @@ def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
701695
FeatureHasSlowFPVMLx,
702696
FeatureVFP3,
703697
FeatureD16,
704-
FeatureAvoidPartialCPSR,
705-
FeatureT2XtPk]>;
698+
FeatureAvoidPartialCPSR]>;
706699

707700
// FIXME: R5 has currently the same ProcessorModel as A8.
708701
def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
@@ -712,8 +705,7 @@ def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
712705
FeatureSlowFPBrcc,
713706
FeatureHWDivARM,
714707
FeatureHasSlowFPVMLx,
715-
FeatureAvoidPartialCPSR,
716-
FeatureT2XtPk]>;
708+
FeatureAvoidPartialCPSR]>;
717709

718710
// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
719711
def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
@@ -725,8 +717,7 @@ def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
725717
FeatureSlowFPBrcc,
726718
FeatureHWDivARM,
727719
FeatureHasSlowFPVMLx,
728-
FeatureAvoidPartialCPSR,
729-
FeatureT2XtPk]>;
720+
FeatureAvoidPartialCPSR]>;
730721

731722
def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,
732723
FeatureHasRetAddrStack,
@@ -737,8 +728,7 @@ def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,
737728
FeatureSlowFPBrcc,
738729
FeatureHWDivARM,
739730
FeatureHasSlowFPVMLx,
740-
FeatureAvoidPartialCPSR,
741-
FeatureT2XtPk]>;
731+
FeatureAvoidPartialCPSR]>;
742732

743733
def : ProcNoItin<"cortex-m3", [ARMv7m, ProcM3]>;
744734
def : ProcNoItin<"sc300", [ARMv7m, ProcM3]>;
@@ -755,50 +745,43 @@ def : ProcNoItin<"cortex-m7", [ARMv7em,
755745
def : ProcNoItin<"cortex-a32", [ARMv8a,
756746
FeatureHWDiv,
757747
FeatureHWDivARM,
758-
FeatureT2XtPk,
759748
FeatureCrypto,
760749
FeatureCRC]>;
761750

762751
def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35,
763752
FeatureHWDiv,
764753
FeatureHWDivARM,
765-
FeatureT2XtPk,
766754
FeatureCrypto,
767755
FeatureCRC]>;
768756

769757
def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,
770758
FeatureHWDiv,
771759
FeatureHWDivARM,
772-
FeatureT2XtPk,
773760
FeatureCrypto,
774761
FeatureCRC]>;
775762

776763
def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57,
777764
FeatureHWDiv,
778765
FeatureHWDivARM,
779-
FeatureT2XtPk,
780766
FeatureCrypto,
781767
FeatureCRC]>;
782768

783769
def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
784770
FeatureHWDiv,
785771
FeatureHWDivARM,
786-
FeatureT2XtPk,
787772
FeatureCrypto,
788773
FeatureCRC]>;
789774

790775
def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73,
791776
FeatureHWDiv,
792777
FeatureHWDivARM,
793-
FeatureT2XtPk,
794778
FeatureCrypto,
795779
FeatureCRC]>;
796780

797781
// Cyclone is very similar to swift
798782
def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
799783
FeatureHasRetAddrStack,
800784
FeatureNEONForFP,
801-
FeatureT2XtPk,
802785
FeatureVFP4,
803786
FeatureMP,
804787
FeatureHWDiv,
@@ -812,7 +795,6 @@ def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
812795
def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1,
813796
FeatureHWDiv,
814797
FeatureHWDivARM,
815-
FeatureT2XtPk,
816798
FeatureCrypto,
817799
FeatureCRC]>;
818800

‎test/MC/ARM/pkhbt-archs.s‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
@ RUN: llvm-mc -triple thumbv7 %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-VALID
2+
@ RUN: llvm-mc -triple thumbv8 %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-VALID
3+
@ RUN: llvm-mc -triple thumbv7em %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-VALID
4+
@ RUN: llvm-mc -triple thumbv6t2 %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-VALID
5+
6+
@ RUN: not llvm-mc -triple thumbv6 %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
7+
@ RUN: not llvm-mc -triple thumbv7m %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
8+
@ RUN: not llvm-mc -triple thumbv8m.main %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
9+
@ RUN: not llvm-mc -triple thumbv8m.base %s -o - -show-encoding 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID
10+
11+
@ Instruction is "v6T2, v7" in ARMARM-AR, "v7em" in ARMARM-M. So it's
12+
@ valid on everything v6t2 upwards, except v7m. Also apparently not on
13+
@ v8m (going by present behaviour).
14+
pkhbt r1, r2, r3, lsl #24
15+
16+
@ CHECK-VALID: pkhbt r1, r2, r3, lsl #24 @ encoding: [0xc2,0xea,0x03,0x61]
17+
@ CHECK-INVALID: error:

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