1212 ******************************************************************************
1313 * @attention
1414 *
15- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
16- * All rights reserved.</center></h2>
15+ * Copyright (c) 2017 STMicroelectronics.
16+ * All rights reserved.
1717 *
18- * This software component is licensed by ST under BSD 3-Clause license,
19- * the "License"; You may not use this file except in compliance with the
20- * License. You may obtain a copy of the License at:
21- * opensource.org/licenses/BSD-3-Clause
18+ * This software is licensed under terms that can be found in the LICENSE file
19+ * in the root directory of this software component.
20+ * If no LICENSE file comes with this software, it is provided AS-IS.
2221 *
2322 ******************************************************************************
2423 */
@@ -13247,7 +13246,7 @@ typedef struct
1324713246/* Ethernet MMC Registers bits definition */
1324813247/******************************************************************************/
1324913248
13250- /* Bit definition for Ethernet MMC Contol Register */
13249+ /* Bit definition for Ethernet MMC Control Register */
1325113250#define ETH_MMCCR_MCFHP_Pos (5U)
1325213251#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
1325313252#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
@@ -13331,7 +13330,7 @@ typedef struct
1333113330#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
1333213331#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
1333313332
13334- /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
13333+ /* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
1333513334#define ETH_MMCRFAECR_RFAEC_Pos (0U)
1333613335#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
1333713336#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
@@ -13345,34 +13344,37 @@ typedef struct
1334513344/* Ethernet PTP Registers bits definition */
1334613345/******************************************************************************/
1334713346
13348- /* Bit definition for Ethernet PTP Time Stamp Contol Register */
13347+ /* Bit definition for Ethernet PTP Time Stamp Control Register */
13348+ #define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
13349+ #define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */
13350+ #define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
1334913351#define ETH_PTPTSCR_TSCNT_Pos (16U)
1335013352#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
1335113353#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
13352- #define ETH_PTPTSSR_TSSMRME_Pos (15U)
13353- #define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos ) /*!< 0x00008000 */
13354- #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
13355- #define ETH_PTPTSSR_TSSEME_Pos (14U)
13356- #define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos ) /*!< 0x00004000 */
13357- #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
13358- #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
13359- #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos ) /*!< 0x00002000 */
13360- #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
13361- #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
13362- #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos ) /*!< 0x00001000 */
13363- #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
13364- #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
13365- #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos ) /*!< 0x00000800 */
13366- #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
13367- #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
13368- #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos ) /*!< 0x00000400 */
13369- #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
13370- #define ETH_PTPTSSR_TSSSR_Pos (9U)
13371- #define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos ) /*!< 0x00000200 */
13372- #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
13373- #define ETH_PTPTSSR_TSSARFE_Pos (8U)
13374- #define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos ) /*!< 0x00000100 */
13375- #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
13354+ #define ETH_PTPTSCR_TSSMRME_Pos (15U)
13355+ #define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos ) /*!< 0x00008000 */
13356+ #define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
13357+ #define ETH_PTPTSCR_TSSEME_Pos (14U)
13358+ #define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos ) /*!< 0x00004000 */
13359+ #define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
13360+ #define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
13361+ #define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos ) /*!< 0x00002000 */
13362+ #define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
13363+ #define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
13364+ #define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos ) /*!< 0x00001000 */
13365+ #define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
13366+ #define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
13367+ #define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos ) /*!< 0x00000800 */
13368+ #define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
13369+ #define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
13370+ #define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos ) /*!< 0x00000400 */
13371+ #define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
13372+ #define ETH_PTPTSCR_TSSSR_Pos (9U)
13373+ #define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos ) /*!< 0x00000200 */
13374+ #define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
13375+ #define ETH_PTPTSCR_TSSARFE_Pos (8U)
13376+ #define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos ) /*!< 0x00000100 */
13377+ #define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
1337613378
1337713379#define ETH_PTPTSCR_TSARU_Pos (5U)
1337813380#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
@@ -13452,6 +13454,9 @@ typedef struct
1345213454/******************************************************************************/
1345313455
1345413456/* Bit definition for Ethernet DMA Bus Mode Register */
13457+ #define ETH_DMABMR_MB_Pos (26U)
13458+ #define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */
13459+ #define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
1345513460#define ETH_DMABMR_AAB_Pos (25U)
1345613461#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
1345713462#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
@@ -15295,7 +15300,7 @@ typedef struct
1529515300#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
1529615301 ((INSTANCE) == TIM5))
1529715302
15298- /***************** TIM Instances : external trigger input availabe ************/
15303+ /***************** TIM Instances : external trigger input available ************/
1529915304#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
1530015305 ((INSTANCE) == TIM2) || \
1530115306 ((INSTANCE) == TIM3) || \
@@ -15600,7 +15605,3 @@ typedef struct
1560015605#endif /* __cplusplus */
1560115606
1560215607#endif /* __STM32F407xx_H */
15603-
15604-
15605-
15606- /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
0 commit comments