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ABOSTMABOSTM
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system: Restore HSI clock at SystemInit()
When USART Bootloader jumps to application, PLL is used as System Clock. It prevents to reconfigure PLL. It is necessary to switch back to default Clock (reset value) before any further PLL configuration. Signed-off-by: Alexandre Bourdiol <[email protected]>
1 parent de25178 commit 1559816

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15 files changed

+167
-51
lines changed

15 files changed

+167
-51
lines changed

‎system/STM32F0xx/system_stm32f0xx.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -184,10 +184,10 @@ void SystemInit(void)
184184
#endif
185185

186186
/* Reset HSI14 bit */
187-
RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
187+
RCC->CR2 &= (uint32_t)0xFFFFFFFE;
188188

189-
/* Disable all interrupts */
190-
RCC->CIR = 0x00000000U;
189+
/* Disable all interrupts and clear pending bits */
190+
RCC->CIR = (uint32_t)0x00BF0000;
191191

192192
}
193193

‎system/STM32F2xx/system_stm32f2xx.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -136,19 +136,19 @@ void SystemInit(void)
136136
RCC->CR |= (uint32_t)0x00000001;
137137

138138
/* Reset CFGR register */
139-
RCC->CFGR = 0x00000000;
139+
RCC->CFGR = (uint32_t)0x00000000;
140140

141141
/* Reset HSEON, CSSON and PLLON bits */
142142
RCC->CR &= (uint32_t)0xFEF6FFFF;
143143

144144
/* Reset PLLCFGR register */
145-
RCC->PLLCFGR = 0x24003010;
145+
RCC->PLLCFGR = (uint32_t)0x24003010;
146146

147147
/* Reset HSEBYP bit */
148148
RCC->CR &= (uint32_t)0xFFFBFFFF;
149149

150-
/* Disable all interrupts */
151-
RCC->CIR = 0x00000000;
150+
/* Disable all interrupts and clear pending bits */
151+
RCC->CIR = (uint32_t)0x00BF0000;
152152

153153
#ifdef DATA_IN_ExtSRAM
154154
SystemInit_ExtMemCtl();

‎system/STM32F3xx/system_stm32f3xx.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -190,8 +190,8 @@ void SystemInit(void)
190190
/* Reset USARTSW[1:0], I2CSW and TIMs bits */
191191
RCC->CFGR3 &= 0xFF00FCCCU;
192192

193-
/* Disable all interrupts */
194-
RCC->CIR = 0x00000000U;
193+
/* Disable all interrupts and clear pending bits */
194+
RCC->CIR = 0x009F0000U;
195195

196196
/* Configure the Vector Table location -------------------------------------*/
197197
#if defined(USER_VECT_TAB_ADDRESS)

‎system/STM32F4xx/system_stm32f4xx.c‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -171,19 +171,22 @@ void SystemInit(void)
171171
RCC->CR |= (uint32_t)0x00000001;
172172

173173
/* Reset CFGR register */
174-
RCC->CFGR = 0x00000000;
174+
RCC->CFGR = (uint32_t)0x00000000;
175175

176176
/* Reset HSEON, CSSON and PLLON bits */
177177
RCC->CR &= (uint32_t)0xFEF6FFFF;
178178

179179
/* Reset PLLCFGR register */
180-
RCC->PLLCFGR = 0x24003010;
180+
RCC->PLLCFGR = (uint32_t)0x24003010;
181181

182182
/* Reset HSEBYP bit */
183183
RCC->CR &= (uint32_t)0xFFFBFFFF;
184184

185-
/* Disable all interrupts */
186-
RCC->CIR = 0x00000000;
185+
#if defined(RCC_CIR_PLLSAIRDYC)
186+
RCC->CIR = (uint32_t)0x00FF0000;
187+
#else
188+
RCC->CIR = (uint32_t)0x00BF0000;
189+
#endif
187190

188191
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
189192
SystemInit_ExtMemCtl();

‎system/STM32F7xx/system_stm32f7xx.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -152,19 +152,19 @@ void SystemInit(void)
152152
RCC->CR |= (uint32_t)0x00000001;
153153

154154
/* Reset CFGR register */
155-
RCC->CFGR = 0x00000000;
155+
RCC->CFGR = (uint32_t)0x00000000;
156156

157157
/* Reset HSEON, CSSON and PLLON bits */
158158
RCC->CR &= (uint32_t)0xFEF6FFFF;
159159

160160
/* Reset PLLCFGR register */
161-
RCC->PLLCFGR = 0x24003010;
161+
RCC->PLLCFGR = (uint32_t)0x24003010;
162162

163163
/* Reset HSEBYP bit */
164164
RCC->CR &= (uint32_t)0xFFFBFFFF;
165165

166-
/* Disable all interrupts */
167-
RCC->CIR = 0x00000000;
166+
/* Disable all interrupts and clear pending bits */
167+
RCC->CIR = (uint32_t)0x00FF0000;
168168

169169

170170
/* Configure the Vector Table location -------------------------------------*/

‎system/STM32G0xx/system_stm32g0xx.c‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -171,6 +171,31 @@
171171
*/
172172
void SystemInit(void)
173173
{
174+
/* Reset the RCC clock configuration to the default reset state ------------*/
175+
/* Set HSION bit */
176+
RCC->CR |= 0x00000500U;
177+
178+
/* Reset CFGR register */
179+
RCC->CFGR = 0x00000000U;
180+
181+
/* Reset HSEON, CSSON and PLLON bits */
182+
RCC->CR &= 0xFEF6FFFFU;
183+
184+
/* Reset PLLCFGR register */
185+
RCC->PLLCFGR = 0x00001000U;
186+
187+
/* Reset HSEBYP bit */
188+
RCC->CR &= 0xFFFBFFFFU;
189+
190+
/* Disable all interrupts and clar flags */
191+
RCC->CIER = 0x00000000U;
192+
193+
#if defined(RCC_CICR_HSI48RDYC)
194+
RCC->CICR = 0x0000033FU;
195+
#else
196+
RCC->CICR = 0x0000033BU;
197+
#endif
198+
174199
/* Configure the Vector Table location -------------------------------------*/
175200
#if defined(USER_VECT_TAB_ADDRESS)
176201
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */

‎system/STM32G4xx/system_stm32g4xx.c‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -177,6 +177,23 @@ void SystemInit(void)
177177
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
178178
#endif
179179

180+
/* Reset the RCC clock configuration to the default reset state ------------*/
181+
/* Set HSION bit */
182+
RCC->CR |= 0x00000500U;
183+
184+
/* Reset CFGR register */
185+
RCC->CFGR = 0x00000001U;
186+
187+
/* Reset CR register */
188+
RCC->CR = 0x00000500U;
189+
190+
/* Reset PLLCFGR register */
191+
RCC->PLLCFGR = 0x00001000U;
192+
193+
/* Disable all interrupts and clar flags */
194+
RCC->CIER = 0x00000000U;
195+
RCC->CICR = 0x0000073BU;
196+
180197
/* Configure the Vector Table location add offset address ------------------*/
181198
#if defined(USER_VECT_TAB_ADDRESS)
182199
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */

‎system/STM32H7xx/system_stm32h7xx.c‎

Lines changed: 18 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -187,7 +187,7 @@ void SystemInit (void)
187187
RCC->CR |= RCC_CR_HSION;
188188

189189
/* Reset CFGR register */
190-
RCC->CFGR = 0x00000000;
190+
RCC->CFGR = 0x00000000U;
191191

192192
/* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
193193
RCC->CR &= 0xEAF6ED7FU;
@@ -201,50 +201,51 @@ void SystemInit (void)
201201

202202
#if defined(D3_SRAM_BASE)
203203
/* Reset D1CFGR register */
204-
RCC->D1CFGR = 0x00000000;
204+
RCC->D1CFGR = 0x00000000U;
205205

206206
/* Reset D2CFGR register */
207-
RCC->D2CFGR = 0x00000000;
207+
RCC->D2CFGR = 0x00000000U;
208208

209209
/* Reset D3CFGR register */
210-
RCC->D3CFGR = 0x00000000;
210+
RCC->D3CFGR = 0x00000000U;
211211
#else
212212
/* Reset CDCFGR1 register */
213-
RCC->CDCFGR1 = 0x00000000;
213+
RCC->CDCFGR1 = 0x00000000U;
214214

215215
/* Reset CDCFGR2 register */
216-
RCC->CDCFGR2 = 0x00000000;
216+
RCC->CDCFGR2 = 0x00000000U;
217217

218218
/* Reset SRDCFGR register */
219-
RCC->SRDCFGR = 0x00000000;
219+
RCC->SRDCFGR = 0x00000000U;
220220
#endif
221221
/* Reset PLLCKSELR register */
222-
RCC->PLLCKSELR = 0x02020200;
222+
RCC->PLLCKSELR = 0x02020200U;
223223

224224
/* Reset PLLCFGR register */
225-
RCC->PLLCFGR = 0x01FF0000;
225+
RCC->PLLCFGR = 0x01FF0000U;
226226
/* Reset PLL1DIVR register */
227-
RCC->PLL1DIVR = 0x01010280;
227+
RCC->PLL1DIVR = 0x01010280U;
228228
/* Reset PLL1FRACR register */
229-
RCC->PLL1FRACR = 0x00000000;
229+
RCC->PLL1FRACR = 0x00000000U;
230230

231231
/* Reset PLL2DIVR register */
232-
RCC->PLL2DIVR = 0x01010280;
232+
RCC->PLL2DIVR = 0x01010280U;
233233

234234
/* Reset PLL2FRACR register */
235235

236-
RCC->PLL2FRACR = 0x00000000;
236+
RCC->PLL2FRACR = 0x00000000U;
237237
/* Reset PLL3DIVR register */
238-
RCC->PLL3DIVR = 0x01010280;
238+
RCC->PLL3DIVR = 0x01010280U;
239239

240240
/* Reset PLL3FRACR register */
241-
RCC->PLL3FRACR = 0x00000000;
241+
RCC->PLL3FRACR = 0x00000000U;
242242

243243
/* Reset HSEBYP bit */
244244
RCC->CR &= 0xFFFBFFFFU;
245245

246-
/* Disable all interrupts */
247-
RCC->CIER = 0x00000000;
246+
/* Disable all interrupts and clar flags */
247+
RCC->CIER = 0x00000000U;
248+
RCC->CICR = 0x000007FFU;
248249

249250
#if (STM32H7_DEV_ID == 0x450UL)
250251
/* dual core CM7 or single core line */

‎system/STM32L0xx/system_stm32l0xx.c‎

Lines changed: 14 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -144,25 +144,32 @@ define USER_VECT_TAB_ADDRESS
144144
void SystemInit (void)
145145
{
146146
/*!< Set MSION bit */
147-
RCC->CR |= (uint32_t)0x00000100U;
147+
RCC->CR |= 0x00000100U;
148148

149149
/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
150-
RCC->CFGR &= (uint32_t) 0x88FF400CU;
150+
RCC->CFGR = 0x00000000U;
151151

152152
/*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
153-
RCC->CR &= (uint32_t)0xFEF6FFF6U;
153+
RCC->CR = 0x00000100U;
154154

155155
/*!< Reset HSI48ON bit */
156-
RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
156+
RCC->CRRCR &= 0xFFFFFFFEU;
157157

158158
/*!< Reset HSEBYP bit */
159-
RCC->CR &= (uint32_t)0xFFFBFFFFU;
159+
RCC->CR &= 0xFFFBFFFFU;
160160

161161
/*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
162-
RCC->CFGR &= (uint32_t)0xFF02FFFFU;
162+
RCC->CFGR &= 0xFF02FFFFU;
163163

164-
/*!< Disable all interrupts */
164+
/* Disable all interrupts and clar flags */
165165
RCC->CIER = 0x00000000U;
166+
#if defined(RCC_CICR_HSI48RDYC)
167+
RCC->CICR = 0x000001FF;
168+
#elif (RCC_CICR_CSSHSEC)
169+
RCC->CICR = 0x000001BFU;
170+
#else
171+
RCC->CICR = 0x000000BFU;
172+
#endif
166173

167174
/* Configure the Vector Table location add offset address ------------------*/
168175
#if defined (USER_VECT_TAB_ADDRESS)

‎system/STM32L1xx/system_stm32l1xx.c‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -169,8 +169,12 @@ void SystemInit (void)
169169
/*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
170170
RCC->CFGR &= (uint32_t)0xFF02FFFF;
171171

172-
/*!< Disable all interrupts */
173-
RCC->CIR = 0x00000000;
172+
/* Disable all interrupts and clear pending bits */
173+
#if defined(RCC_CIR_LSECSSF)
174+
RCC->CIR = (uint32_t)0x00FF0000;
175+
#else
176+
RCC->CIR = (uint32_t)0x00BF0000;
177+
#endif
174178

175179
#ifdef DATA_IN_ExtSRAM
176180
SystemInit_ExtMemCtl();

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