impl Debug (#39)

Author: strake

src/instructions/port.rs

@@ -63,6 +63,7 @@ impl PortReadWrite for u32 {
 }
 
 /// An I/O port.
+#[derive(Debug)]
 pub struct Port<T: PortReadWrite> {
     port: u16,
     phantom: PhantomData<T>,

src/instructions/tables.rs

@@ -4,6 +4,7 @@ use structures::gdt::SegmentSelector;
 
 /// A struct describing a pointer to a descriptor table (GDT / IDT).
 /// This is in a format suitable for giving to 'lgdt' or 'lidt'.
+#[derive(Debug, Clone, Copy)]
 #[repr(C, packed)]
 pub struct DescriptorTablePointer {
     /// Size of the DT.

src/lib.rs

@@ -10,6 +10,8 @@
 #![cfg_attr(feature = "deny-warnings", deny(missing_docs))]
 #![cfg_attr(not(feature = "deny-warnings"), warn(missing_docs))]
 
+#![deny(missing_debug_implementations)]
+
 #[cfg(test)]
 #[macro_use]
 extern crate std;

src/registers/control.rs

@@ -6,6 +6,7 @@ use structures::paging::PhysFrame;
 use PhysAddr;
 
 /// Various control flags modifying the basic operation of the CPU.
+#[derive(Debug)]
 pub struct Cr0;
 
 impl Cr0 {
@@ -91,6 +92,7 @@ bitflags! {
 }
 
 /// Contains the physical address of the level 4 page table.
+#[derive(Debug)]
 pub struct Cr3;
 
 impl Cr3 {

src/registers/model_specific.rs

@@ -1,6 +1,7 @@
 //! Functions to read and write control registers.
 
 /// A model specific register.
+#[derive(Debug)]
 pub struct Msr(u32);
 
 impl Msr {
@@ -25,6 +26,7 @@ impl Msr {
 }
 
 /// The Extended Feature Enable Register.
+#[derive(Debug)]
 pub struct Efer;
 
 impl Efer {

src/structures/gdt.rs

@@ -50,6 +50,7 @@ impl fmt::Debug for SegmentSelector {
 /// switching between user and kernel mode or for loading a TSS.
 ///
 /// The GDT has a fixed size of 8 entries, trying to add more entries will panic.
+#[derive(Debug)]
 pub struct GlobalDescriptorTable {
     table: [u64; 8],
     next_free: usize,
@@ -108,6 +109,7 @@ impl GlobalDescriptorTable {
 ///
 /// Segmentation is no longer supported in 64-bit mode, so most of the descriptor
 /// contents are ignored.
+#[derive(Debug)]
 pub enum Descriptor {
     /// Descriptor for a code or data segment.
     ///

src/structures/idt.rs

@@ -30,6 +30,7 @@ use {PrivilegeLevel, VirtAddr};
 /// The field descriptions are taken from the
 /// [AMD64 manual volume 2](https://support.amd.com/TechDocs/24593.pdf)
 /// (with slight modifications).
+#[allow(missing_debug_implementations)]
 #[repr(C)]
 pub struct InterruptDescriptorTable {
     /// A divide by zero exception (`#DE`) occurs when the denominator of a DIV instruction or
@@ -505,7 +506,7 @@ impl IndexMut<usize> for InterruptDescriptorTable {
 ///
 /// The generic parameter can either be `HandlerFunc` or `HandlerFuncWithErrCode`, depending
 /// on the interrupt vector.
-#[derive(Clone, Copy)]
+#[derive(Debug, Clone, Copy)]
 #[repr(C)]
 pub struct Entry<F> {
     pointer_low: u16,

src/structures/paging/mod.rs

@@ -31,17 +31,17 @@ pub trait PageSize: Copy + Eq + PartialOrd + Ord {
 pub trait NotGiantPageSize: PageSize {}
 
 /// A standard 4KiB page.
-#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
 pub enum Size4KiB {}
 
 /// A “huge” 2MiB page.
-#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
 pub enum Size2MiB {}
 
 /// A “giant” 1GiB page.
 ///
 /// (Only available on newer x86_64 CPUs.)
-#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
+#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
 pub enum Size1GiB {}
 
 impl PageSize for Size4KiB {

src/structures/paging/recursive.rs

@@ -15,6 +15,7 @@ use {PhysAddr, VirtAddr};
 /// The old mapping might be still cached in the translation lookaside buffer (TLB), so it needs
 /// to be flushed from the TLB before it's accessed. This type is returned from function that
 /// change the mapping of a page to ensure that the TLB flush is not forgotten.
+#[derive(Debug)]
 #[must_use = "Page Table changes must be flushed or ignored."]
 pub struct MapperFlush<S: PageSize>(Page<S>);
 
@@ -94,6 +95,7 @@ pub trait Mapper<S: PageSize> {
 ///   level 3 index, then the level 2 index.
 ///
 /// This struct implements the `Mapper` trait.
+#[derive(Debug)]
 pub struct RecursivePageTable<'a> {
     p4: &'a mut PageTable,
     recursive_index: u9,

src/structures/tss.rs

@@ -6,6 +6,7 @@ use VirtAddr;
 /// directly related to the task-switch mechanism,
 /// but is used for finding kernel level stack
 /// if interrupts arrive while in kernel mode.
+#[derive(Debug, Clone, Copy)]
 #[repr(C, packed)]
 pub struct TaskStateSegment {
     reserved_1: u32,