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correct assert_instr
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-86
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3 files changed

+86
-86
lines changed

‎crates/core_arch/src/arm/neon/generated.rs‎

Lines changed: 68 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -2048,7 +2048,7 @@ pub unsafe fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t {
20482048
#[inline]
20492049
#[target_feature(enable = "neon")]
20502050
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2051-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 4))]
2051+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vext.8, N = 4))]
20522052
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 4))]
20532053
#[rustc_legacy_const_generics(2)]
20542054
pub unsafe fn vext_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
@@ -2070,7 +2070,7 @@ pub unsafe fn vext_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
20702070
#[inline]
20712071
#[target_feature(enable = "neon")]
20722072
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2073-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 8))]
2073+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vext.8, N = 8))]
20742074
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 8))]
20752075
#[rustc_legacy_const_generics(2)]
20762076
pub unsafe fn vextq_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
@@ -2100,7 +2100,7 @@ pub unsafe fn vextq_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
21002100
#[inline]
21012101
#[target_feature(enable = "neon")]
21022102
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2103-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.16", N = 2))]
2103+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vext.8, N = 2))]
21042104
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 2))]
21052105
#[rustc_legacy_const_generics(2)]
21062106
pub unsafe fn vext_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
@@ -2118,7 +2118,7 @@ pub unsafe fn vext_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
21182118
#[inline]
21192119
#[target_feature(enable = "neon")]
21202120
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2121-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.16", N = 4))]
2121+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vext.8, N = 4))]
21222122
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 4))]
21232123
#[rustc_legacy_const_generics(2)]
21242124
pub unsafe fn vextq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
@@ -2140,7 +2140,7 @@ pub unsafe fn vextq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
21402140
#[inline]
21412141
#[target_feature(enable = "neon")]
21422142
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2143-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.32", N = 1))]
2143+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vext.8, N = 1))]
21442144
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 1))]
21452145
#[rustc_legacy_const_generics(2)]
21462146
pub unsafe fn vext_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
@@ -2156,7 +2156,7 @@ pub unsafe fn vext_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
21562156
#[inline]
21572157
#[target_feature(enable = "neon")]
21582158
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2159-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.32", N = 2))]
2159+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vext.8, N = 2))]
21602160
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 2))]
21612161
#[rustc_legacy_const_generics(2)]
21622162
pub unsafe fn vextq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
@@ -2174,23 +2174,7 @@ pub unsafe fn vextq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
21742174
#[inline]
21752175
#[target_feature(enable = "neon")]
21762176
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2177-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.64", N = 1))]
2178-
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 1))]
2179-
#[rustc_legacy_const_generics(2)]
2180-
pub unsafe fn vextq_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
2181-
static_assert_imm1!(N);
2182-
match N & 0b1 {
2183-
0 => simd_shuffle2(a, b, [0, 1]),
2184-
1 => simd_shuffle2(a, b, [1, 2]),
2185-
_ => unreachable_unchecked(),
2186-
}
2187-
}
2188-
2189-
/// Extract vector from pair of vectors
2190-
#[inline]
2191-
#[target_feature(enable = "neon")]
2192-
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2193-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 4))]
2177+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vext.8, N = 4))]
21942178
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 4))]
21952179
#[rustc_legacy_const_generics(2)]
21962180
pub unsafe fn vext_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
@@ -2212,7 +2196,7 @@ pub unsafe fn vext_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
22122196
#[inline]
22132197
#[target_feature(enable = "neon")]
22142198
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2215-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 8))]
2199+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vext.8, N = 8))]
22162200
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 8))]
22172201
#[rustc_legacy_const_generics(2)]
22182202
pub unsafe fn vextq_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
@@ -2242,7 +2226,7 @@ pub unsafe fn vextq_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t
22422226
#[inline]
22432227
#[target_feature(enable = "neon")]
22442228
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2245-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.16", N = 2))]
2229+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vext.8, N = 2))]
22462230
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 2))]
22472231
#[rustc_legacy_const_generics(2)]
22482232
pub unsafe fn vext_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
@@ -2260,7 +2244,7 @@ pub unsafe fn vext_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t
22602244
#[inline]
22612245
#[target_feature(enable = "neon")]
22622246
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2263-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.16", N = 4))]
2247+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vext.8, N = 4))]
22642248
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 4))]
22652249
#[rustc_legacy_const_generics(2)]
22662250
pub unsafe fn vextq_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
@@ -2282,7 +2266,7 @@ pub unsafe fn vextq_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_
22822266
#[inline]
22832267
#[target_feature(enable = "neon")]
22842268
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2285-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.32", N = 1))]
2269+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vext.8, N = 1))]
22862270
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 1))]
22872271
#[rustc_legacy_const_generics(2)]
22882272
pub unsafe fn vext_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
@@ -2298,7 +2282,7 @@ pub unsafe fn vext_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t
22982282
#[inline]
22992283
#[target_feature(enable = "neon")]
23002284
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2301-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.32", N = 2))]
2285+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vext.8, N = 2))]
23022286
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 2))]
23032287
#[rustc_legacy_const_generics(2)]
23042288
pub unsafe fn vextq_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
@@ -2316,23 +2300,7 @@ pub unsafe fn vextq_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_
23162300
#[inline]
23172301
#[target_feature(enable = "neon")]
23182302
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2319-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.64", N = 1))]
2320-
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 1))]
2321-
#[rustc_legacy_const_generics(2)]
2322-
pub unsafe fn vextq_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
2323-
static_assert_imm1!(N);
2324-
match N & 0b1 {
2325-
0 => simd_shuffle2(a, b, [0, 1]),
2326-
1 => simd_shuffle2(a, b, [1, 2]),
2327-
_ => unreachable_unchecked(),
2328-
}
2329-
}
2330-
2331-
/// Extract vector from pair of vectors
2332-
#[inline]
2333-
#[target_feature(enable = "neon")]
2334-
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2335-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 4))]
2303+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vext.8, N = 4))]
23362304
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 4))]
23372305
#[rustc_legacy_const_generics(2)]
23382306
pub unsafe fn vext_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
@@ -2354,7 +2322,7 @@ pub unsafe fn vext_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
23542322
#[inline]
23552323
#[target_feature(enable = "neon")]
23562324
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2357-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 8))]
2325+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vext.8, N = 8))]
23582326
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 8))]
23592327
#[rustc_legacy_const_generics(2)]
23602328
pub unsafe fn vextq_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
@@ -2384,7 +2352,7 @@ pub unsafe fn vextq_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t
23842352
#[inline]
23852353
#[target_feature(enable = "neon")]
23862354
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2387-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.16", N = 2))]
2355+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vext.8, N = 2))]
23882356
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 2))]
23892357
#[rustc_legacy_const_generics(2)]
23902358
pub unsafe fn vext_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
@@ -2402,7 +2370,7 @@ pub unsafe fn vext_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t
24022370
#[inline]
24032371
#[target_feature(enable = "neon")]
24042372
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2405-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.16", N = 4))]
2373+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vext.8, N = 4))]
24062374
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 4))]
24072375
#[rustc_legacy_const_generics(2)]
24082376
pub unsafe fn vextq_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
@@ -2424,7 +2392,39 @@ pub unsafe fn vextq_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_
24242392
#[inline]
24252393
#[target_feature(enable = "neon")]
24262394
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2427-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.32", N = 1))]
2395+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
2396+
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 1))]
2397+
#[rustc_legacy_const_generics(2)]
2398+
pub unsafe fn vextq_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
2399+
static_assert_imm1!(N);
2400+
match N & 0b1 {
2401+
0 => simd_shuffle2(a, b, [0, 1]),
2402+
1 => simd_shuffle2(a, b, [1, 2]),
2403+
_ => unreachable_unchecked(),
2404+
}
2405+
}
2406+
2407+
/// Extract vector from pair of vectors
2408+
#[inline]
2409+
#[target_feature(enable = "neon")]
2410+
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2411+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
2412+
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 1))]
2413+
#[rustc_legacy_const_generics(2)]
2414+
pub unsafe fn vextq_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
2415+
static_assert_imm1!(N);
2416+
match N & 0b1 {
2417+
0 => simd_shuffle2(a, b, [0, 1]),
2418+
1 => simd_shuffle2(a, b, [1, 2]),
2419+
_ => unreachable_unchecked(),
2420+
}
2421+
}
2422+
2423+
/// Extract vector from pair of vectors
2424+
#[inline]
2425+
#[target_feature(enable = "neon")]
2426+
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2427+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vext.8, N = 1))]
24282428
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 1))]
24292429
#[rustc_legacy_const_generics(2)]
24302430
pub unsafe fn vext_f32<const N: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
@@ -2440,7 +2440,7 @@ pub unsafe fn vext_f32<const N: i32>(a: float32x2_t, b: float32x2_t) -> float32x
24402440
#[inline]
24412441
#[target_feature(enable = "neon")]
24422442
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
2443-
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.32", N = 2))]
2443+
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vext.8, N = 2))]
24442444
#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 2))]
24452445
#[rustc_legacy_const_generics(2)]
24462446
pub unsafe fn vextq_f32<const N: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
@@ -9451,15 +9451,6 @@ mod test {
94519451
assert_eq!(r, e);
94529452
}
94539453

9454-
#[simd_test(enable = "neon")]
9455-
unsafe fn test_vextq_s64() {
9456-
let a: i64x2 = i64x2::new(0, 8);
9457-
let b: i64x2 = i64x2::new(9, 11);
9458-
let e: i64x2 = i64x2::new(8, 9);
9459-
let r: i64x2 = transmute(vextq_s64::<1>(transmute(a), transmute(b)));
9460-
assert_eq!(r, e);
9461-
}
9462-
94639454
#[simd_test(enable = "neon")]
94649455
unsafe fn test_vext_u8() {
94659456
let a: u8x8 = u8x8::new(0, 8, 8, 9, 8, 9, 9, 11);
@@ -9514,15 +9505,6 @@ mod test {
95149505
assert_eq!(r, e);
95159506
}
95169507

9517-
#[simd_test(enable = "neon")]
9518-
unsafe fn test_vextq_u64() {
9519-
let a: u64x2 = u64x2::new(0, 8);
9520-
let b: u64x2 = u64x2::new(9, 11);
9521-
let e: u64x2 = u64x2::new(8, 9);
9522-
let r: u64x2 = transmute(vextq_u64::<1>(transmute(a), transmute(b)));
9523-
assert_eq!(r, e);
9524-
}
9525-
95269508
#[simd_test(enable = "neon")]
95279509
unsafe fn test_vext_p8() {
95289510
let a: i8x8 = i8x8::new(0, 8, 8, 9, 8, 9, 9, 11);
@@ -9559,6 +9541,24 @@ mod test {
95599541
assert_eq!(r, e);
95609542
}
95619543

9544+
#[simd_test(enable = "neon")]
9545+
unsafe fn test_vextq_s64() {
9546+
let a: i64x2 = i64x2::new(0, 8);
9547+
let b: i64x2 = i64x2::new(9, 11);
9548+
let e: i64x2 = i64x2::new(8, 9);
9549+
let r: i64x2 = transmute(vextq_s64::<1>(transmute(a), transmute(b)));
9550+
assert_eq!(r, e);
9551+
}
9552+
9553+
#[simd_test(enable = "neon")]
9554+
unsafe fn test_vextq_u64() {
9555+
let a: u64x2 = u64x2::new(0, 8);
9556+
let b: u64x2 = u64x2::new(9, 11);
9557+
let e: u64x2 = u64x2::new(8, 9);
9558+
let r: u64x2 = transmute(vextq_u64::<1>(transmute(a), transmute(b)));
9559+
assert_eq!(r, e);
9560+
}
9561+
95629562
#[simd_test(enable = "neon")]
95639563
unsafe fn test_vext_f32() {
95649564
let a: f32x2 = f32x2::new(0., 2.);

‎crates/stdarch-gen/neon.spec‎

Lines changed: 17 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -900,11 +900,25 @@ b = 9, 11, 14, 15, 16, 17, 18, 19, 0, 8, 8, 9, 8, 9, 9, 11
900900
n = HFLEN
901901
validate 8, 9, 9, 11, 9, 11, 14, 15, 9, 11, 14, 15, 16, 17, 18, 19
902902

903+
aarch64 = ext
904+
arm = vext.8
905+
generate int*_t, uint*_t, poly8x8_t, poly8x16_t, poly16x4_t, poly16x8_t
906+
907+
/// Extract vector from pair of vectors
908+
name = vext
909+
constn = N
910+
multi_fn = static_assert_imm-out_exp_len-N
911+
multi_fn = matchn-out_exp_len, simd_shuffle-out_len-noext, a, b, {asc-n-out_len}
912+
a = 0, 8, 8, 9, 8, 9, 9, 11, 8, 9, 9, 11, 9, 11, 14, 15
913+
b = 9, 11, 14, 15, 16, 17, 18, 19, 0, 8, 8, 9, 8, 9, 9, 11
914+
n = HFLEN
915+
validate 8, 9, 9, 11, 9, 11, 14, 15, 9, 11, 14, 15, 16, 17, 18, 19
916+
903917
aarch64 = ext
904918
generate poly64x2_t
905919

906-
arm = vext.sz
907-
generate int*_t, int64x2_t, uint*_t, uint64x2_t, poly8x8_t, poly8x16_t, poly16x4_t, poly16x8_t
920+
arm = vmov
921+
generate int64x2_t, uint64x2_t
908922

909923
/// Extract vector from pair of vectors
910924
name = vext
@@ -919,7 +933,7 @@ validate 2., 3., 3., 4.
919933
aarch64 = ext
920934
generate float64x2_t
921935

922-
arm = vext.sz
936+
arm = vext.8
923937
generate float*_t
924938

925939
/// Multiply-add to accumulator

‎crates/stdarch-gen/src/main.rs‎

Lines changed: 1 addition & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1251,20 +1251,6 @@ fn expand_intrinsic(intr: &str, t: &str) -> String {
12511251
_ => panic!("unknown type for extension: {}", t),
12521252
};
12531253
format!(r#""{}{}""#, &intr[..intr.len() - 1], ext)
1254-
} else if intr.ends_with(".sz") {
1255-
let ext = match t {
1256-
"int8x8_t" | "int8x16_t" | "uint8x8_t" | "uint8x16_t" | "poly8x8_t" | "poly8x16_t" => {
1257-
"8"
1258-
}
1259-
"int16x4_t" | "int16x8_t" | "uint16x4_t" | "uint16x8_t" | "poly16x4_t"
1260-
| "poly16x8_t" => "16",
1261-
"int32x2_t" | "int32x4_t" | "uint32x2_t" | "uint32x4_t" | "float32x2_t"
1262-
| "float32x4_t" => "32",
1263-
"int64x1_t" | "int64x2_t" | "uint64x1_t" | "uint64x2_t" | "float64x1_t"
1264-
| "float64x2_t" | "poly64x1_t" | "poly64x2_t" => "64",
1265-
_ => panic!("unknown type for extension: {}", t),
1266-
};
1267-
format!(r#""{}{}""#, &intr[..intr.len() - 2], ext)
12681254
} else {
12691255
intr.to_string()
12701256
}
@@ -1708,7 +1694,7 @@ mod test {
17081694
file_arm.write_all(out_arm.as_bytes())?;
17091695
file_arm.write_all(tests_arm.as_bytes())?;
17101696

1711-
let aarch64_out_path: PathBuf = PathBuf::from(env::var("OUT_DIR").unwrap())
1697+
//let aarch64_out_path: PathBuf = PathBuf::from(env::var("OUT_DIR").unwrap())
17121698
.join("src")
17131699
.join("aarch64")
17141700
.join("neon");

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