Add missing intrinsic translations

Author: GuillaumeGomez

src/intrinsic/llvm.rs

@@ -1340,6 +1340,75 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
         "llvm.x86.tcmmimfp16ps" => "__builtin_trap",
         "llvm.x86.tcmmrlfp16ps" => "__builtin_trap",
 
+        // Intrinsics not listed by `llvm-tblgen`.
+        "llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256",
+        "llvm.x86.avx512.mask.fpclass.pd.128" => "__builtin_ia32_fpclasspd128_mask",
+        "llvm.x86.avx512.mask.fpclass.pd.256" => "__builtin_ia32_fpclasspd256_mask",
+        "llvm.x86.avx512.mask.fpclass.pd.512" => "__builtin_ia32_fpclasspd512_mask",
+        "llvm.x86.avx512.mask.fpclass.ps.128" => "__builtin_ia32_fpclassps128_mask",
+        "llvm.x86.avx512.mask.fpclass.ps.256" => "__builtin_ia32_fpclassps256_mask",
+        "llvm.x86.avx512.mask.fpclass.ps.512" => "__builtin_ia32_fpclassps512_mask",
+        "llvm.x86.avx512.mask.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps_mask",
+        "llvm.x86.avx512.mask.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256_mask",
+        "llvm.x86.avx512.mask.vcvtph2ps.512" => "__builtin_ia32_vcvtph2ps512_mask",
+        "llvm.x86.avx512.mask.cvttps2dq.128" => "__builtin_ia32_cvttps2dq128_mask",
+        "llvm.x86.avx512.mask.cvttps2dq.256" => "__builtin_ia32_cvttps2dq256_mask",
+        "llvm.x86.avx512.mask.cvtudq2pd.128" => "__builtin_ia32_cvtudq2pd128_mask",
+        "llvm.x86.avx512.mask.cvtudq2pd.256" => "__builtin_ia32_cvtudq2pd256_mask",
+        "llvm.x86.avx512.mask.cvtudq2pd.512" => "__builtin_ia32_cvtudq2pd512_mask",
+        "llvm.x86.avx512.mask.cvtudq2ps.128" => "__builtin_ia32_cvtudq2ps128_mask",
+        "llvm.x86.avx512.mask.cvtudq2ps.256" => "__builtin_ia32_cvtudq2ps256_mask",
+        "llvm.x86.avx512.mask.cvtudq2ps.512" => "__builtin_ia32_cvtudq2ps512_mask",
+        "llvm.x86.avx512.mask.cvtuqq2pd.128" => "__builtin_ia32_cvtuqq2pd128_mask",
+        "llvm.x86.avx512.mask.cvtuqq2pd.256" => "__builtin_ia32_cvtuqq2pd256_mask",
+        "llvm.x86.avx512.mask.cvtuqq2pd.512" => "__builtin_ia32_cvtuqq2pd512_mask",
+        "llvm.x86.avx512.mask.cvtuqq2ps.256" => "__builtin_ia32_cvtuqq2ps256_mask",
+        "llvm.x86.avx512.mask.cvtuqq2ps.512" => "__builtin_ia32_cvtuqq2ps512_mask",
+        "llvm.x86.avx512.mask.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128_mask",
+        "llvm.x86.avx512.mask.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256_mask",
+        "llvm.x86.avx512.mask.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512_mask",
+        "llvm.x86.avx512.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask",
+        "llvm.x86.avx512.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask",
+        "llvm.x86.avx512.sqrt.sd" => "__builtin_ia32_sqrtrndsd",
+        "llvm.x86.avx512.sqrt.ss" => "__builtin_ia32_sqrtrndss",
+        "llvm.x86.rdtscp" => "__builtin_ia32_rdtscp",
+        "llvm.x86.sse2.add.sd" => "__builtin_ia32_addsd",
+        "llvm.x86.sse2.cmp.pd" => "__builtin_ia32_cmppd",
+        "llvm.x86.sse2.cvtdq2pd" => "__builtin_ia32_cvtdq2pd",
+        "llvm.x86.sse2.cvtdq2ps" => "__builtin_ia32_cvtdq2ps",
+        "llvm.x86.sse2.cvtps2pd" => "__builtin_ia32_cvtps2pd",
+        "llvm.x86.sse2.cvtsi2sd" => "__builtin_ia32_cvtsi2sd",
+        "llvm.x86.sse2.cvtsi642sd" => "__builtin_ia32_cvtsi642sd",
+        "llvm.x86.sse2.cvtss2sd" => "__builtin_ia32_cvtss2sd",
+        "llvm.x86.sse2.div.sd" => "__builtin_ia32_divsd",
+        "llvm.x86.sse2.mul.sd" => "__builtin_ia32_mulsd",
+        "llvm.x86.sse2.padds.b" => "__builtin_ia32_paddsb128",
+        "llvm.x86.sse2.padds.w" => "__builtin_ia32_paddsw128",
+        "llvm.x86.sse2.paddus.b" => "__builtin_ia32_paddusb128",
+        "llvm.x86.sse2.paddus.w" => "__builtin_ia32_paddusw128",
+        "llvm.x86.sse2.pmaxs.w" => "__builtin_ia32_pmaxsw128",
+        "llvm.x86.sse2.pmaxu.b" => "__builtin_ia32_pmaxub128",
+        "llvm.x86.sse2.pmins.w" => "__builtin_ia32_pminsw128",
+        "llvm.x86.sse2.pminu.b" => "__builtin_ia32_pminub128",
+        "llvm.x86.sse2.pmulu.dq" => "__builtin_ia32_pmuludq128",
+        "llvm.x86.sse2.pshuf.d" => "__builtin_ia32_pshufd",
+        "llvm.x86.sse2.pshufh.w" => "__builtin_ia32_pshufhw",
+        "llvm.x86.sse2.pshufl.w" => "__builtin_ia32_pshuflw",
+        "llvm.x86.sse2.psll.dq" => "__builtin_ia32_pslldqi128",
+        "llvm.x86.sse2.psll.dq.bs" => "__builtin_ia32_pslldqi128_byteshift",
+        "llvm.x86.sse2.psrl.dq" => "__builtin_ia32_psrldqi128",
+        "llvm.x86.sse2.psrl.dq.bs" => "__builtin_ia32_psrldqi128_byteshift",
+        "llvm.x86.sse2.psubs.b" => "__builtin_ia32_psubsb128",
+        "llvm.x86.sse2.psubs.w" => "__builtin_ia32_psubsw128",
+        "llvm.x86.sse2.psubus.b" => "__builtin_ia32_psubusb128",
+        "llvm.x86.sse2.psubus.w" => "__builtin_ia32_psubusw128",
+        "llvm.x86.sse2.sqrt.pd" => "__builtin_ia32_sqrtpd",
+        "llvm.x86.sse2.sqrt.sd" => "__builtin_ia32_sqrtsd",
+        "llvm.x86.sse2.storel.dq" => "__builtin_ia32_storelv4si",
+        "llvm.x86.sse2.storeu.dq" => "__builtin_ia32_storedqu",
+        "llvm.x86.sse2.storeu.pd" => "__builtin_ia32_storeupd",
+        "llvm.x86.sse2.sub.sd" => "__builtin_ia32_subsd",
+
         // NOTE: this file is generated by https://github.com/GuillaumeGomez/llvmint/blob/master/generate_list.py
         _ => include!("archs.rs"),
     };