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Auto merge of #78066 - bugadani:wat, r=jonas-schievink
Clean up small, surprising bits of code This PR clean up a small number of unrelated, small things I found while browsing the code base.
2 parents 98e1688 + 2e99439 commit 834821e

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6 files changed

+48
-53
lines changed

6 files changed

+48
-53
lines changed

‎compiler/rustc_ast/src/util/lev_distance.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ where
5454
T: Iterator<Item = &'a Symbol>,
5555
{
5656
let lookup = &lookup.as_str();
57-
let max_dist = dist.map_or_else(|| cmp::max(lookup.len(), 3) / 3, |d| d);
57+
let max_dist = dist.unwrap_or_else(|| cmp::max(lookup.len(), 3) / 3);
5858
let name_vec: Vec<&Symbol> = iter_names.collect();
5959

6060
let (case_insensitive_match, levenshtein_match) = name_vec

‎compiler/rustc_ast_lowering/src/expr.rs‎

Lines changed: 39 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -1190,52 +1190,47 @@ impl<'hir> LoweringContext<'_, 'hir> {
11901190
input| {
11911191
match used_regs.entry(r) {
11921192
Entry::Occupied(o) => {
1193-
if !skip {
1194-
skip = true;
1195-
1196-
let idx2 = *o.get();
1197-
let op2 = &operands[idx2];
1198-
let op_sp2 = asm.operands[idx2].1;
1199-
let reg2 = match op2.reg() {
1200-
Some(asm::InlineAsmRegOrRegClass::Reg(r)) => r,
1201-
_ => unreachable!(),
1202-
};
1203-
1204-
let msg = format!(
1205-
"register `{}` conflicts with register `{}`",
1206-
reg.name(),
1207-
reg2.name()
1208-
);
1209-
let mut err = sess.struct_span_err(op_sp, &msg);
1210-
err.span_label(
1211-
op_sp,
1212-
&format!("register `{}`", reg.name()),
1213-
);
1214-
err.span_label(
1215-
op_sp2,
1216-
&format!("register `{}`", reg2.name()),
1217-
);
1218-
1219-
match (op, op2) {
1220-
(
1221-
hir::InlineAsmOperand::In { .. },
1222-
hir::InlineAsmOperand::Out { late, .. },
1223-
)
1224-
| (
1225-
hir::InlineAsmOperand::Out { late, .. },
1226-
hir::InlineAsmOperand::In { .. },
1227-
) => {
1228-
assert!(!*late);
1229-
let out_op_sp = if input { op_sp2 } else { op_sp };
1230-
let msg = "use `lateout` instead of \
1231-
`out` to avoid conflict";
1232-
err.span_help(out_op_sp, msg);
1233-
}
1234-
_ => {}
1193+
if skip {
1194+
return;
1195+
}
1196+
skip = true;
1197+
1198+
let idx2 = *o.get();
1199+
let op2 = &operands[idx2];
1200+
let op_sp2 = asm.operands[idx2].1;
1201+
let reg2 = match op2.reg() {
1202+
Some(asm::InlineAsmRegOrRegClass::Reg(r)) => r,
1203+
_ => unreachable!(),
1204+
};
1205+
1206+
let msg = format!(
1207+
"register `{}` conflicts with register `{}`",
1208+
reg.name(),
1209+
reg2.name()
1210+
);
1211+
let mut err = sess.struct_span_err(op_sp, &msg);
1212+
err.span_label(op_sp, &format!("register `{}`", reg.name()));
1213+
err.span_label(op_sp2, &format!("register `{}`", reg2.name()));
1214+
1215+
match (op, op2) {
1216+
(
1217+
hir::InlineAsmOperand::In { .. },
1218+
hir::InlineAsmOperand::Out { late, .. },
1219+
)
1220+
| (
1221+
hir::InlineAsmOperand::Out { late, .. },
1222+
hir::InlineAsmOperand::In { .. },
1223+
) => {
1224+
assert!(!*late);
1225+
let out_op_sp = if input { op_sp2 } else { op_sp };
1226+
let msg = "use `lateout` instead of \
1227+
`out` to avoid conflict";
1228+
err.span_help(out_op_sp, msg);
12351229
}
1236-
1237-
err.emit();
1230+
_ => {}
12381231
}
1232+
1233+
err.emit();
12391234
}
12401235
Entry::Vacant(v) => {
12411236
v.insert(idx);

‎compiler/rustc_lint/src/builtin.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -968,7 +968,7 @@ fn warn_if_doc(cx: &EarlyContext<'_>, node_span: Span, node_kind: &str, attrs: &
968968
while let Some(attr) = attrs.next() {
969969
if attr.is_doc_comment() {
970970
sugared_span =
971-
Some(sugared_span.map_or_else(|| attr.span, |span| span.with_hi(attr.span.hi())));
971+
Some(sugared_span.map_or(attr.span, |span| span.with_hi(attr.span.hi())));
972972
}
973973

974974
if attrs.peek().map(|next_attr| next_attr.is_doc_comment()).unwrap_or_default() {

‎compiler/rustc_middle/src/hir/place.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -103,7 +103,7 @@ impl<'tcx> Place<'tcx> {
103103

104104
/// Returns the type of this `Place` after all projections have been applied.
105105
pub fn ty(&self) -> Ty<'tcx> {
106-
self.projections.last().map_or_else(|| self.base_ty, |proj| proj.ty)
106+
self.projections.last().map_or(self.base_ty, |proj| proj.ty)
107107
}
108108

109109
/// Returns the type of this `Place` immediately before `projection_index`th projection

‎compiler/rustc_mir/src/borrow_check/type_check/input_output.rs‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,7 @@ impl<'a, 'tcx> TypeChecker<'a, 'tcx> {
7373
);
7474

7575
// Equate expected input tys with those in the MIR.
76-
for (&normalized_input_ty, argument_index) in normalized_input_tys.iter().zip(0..) {
76+
for (argument_index, &normalized_input_ty) in normalized_input_tys.iter().enumerate() {
7777
// In MIR, argument N is stored in local N+1.
7878
let local = Local::new(argument_index + 1);
7979

@@ -87,8 +87,8 @@ impl<'a, 'tcx> TypeChecker<'a, 'tcx> {
8787
}
8888

8989
if let Some(user_provided_sig) = user_provided_sig {
90-
for (&user_provided_input_ty, argument_index) in
91-
user_provided_sig.inputs().iter().zip(0..)
90+
for (argument_index, &user_provided_input_ty) in
91+
user_provided_sig.inputs().iter().enumerate()
9292
{
9393
// In MIR, closures begin an implicit `self`, so
9494
// argument N is stored in local N+2.

‎compiler/rustc_passes/src/dead.rs‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -458,8 +458,8 @@ fn create_and_seed_worklist<'tcx>(
458458
.map
459459
.iter()
460460
.filter_map(
461-
|(&id, level)| {
462-
if level >= &privacy::AccessLevel::Reachable { Some(id) } else { None }
461+
|(&id, &level)| {
462+
if level >= privacy::AccessLevel::Reachable { Some(id) } else { None }
463463
},
464464
)
465465
.chain(
@@ -547,7 +547,7 @@ impl DeadVisitor<'tcx> {
547547
let def_id = self.tcx.hir().local_def_id(id);
548548
let inherent_impls = self.tcx.inherent_impls(def_id);
549549
for &impl_did in inherent_impls.iter() {
550-
for &item_did in &self.tcx.associated_item_def_ids(impl_did)[..] {
550+
for item_did in self.tcx.associated_item_def_ids(impl_did) {
551551
if let Some(did) = item_did.as_local() {
552552
let item_hir_id = self.tcx.hir().local_def_id_to_hir_id(did);
553553
if self.live_symbols.contains(&item_hir_id) {

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