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[RISCV] Add lowering of addressing sequences for PIC
This patch allows lowering of PIC addresses by using PC-relative addressing for DSO-local symbols and accessing the address through the global offset table for non-DSO-local symbols. Differential Revision: https://reviews.llvm.org/D55303 llvm-svn: 363058
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+149
-16
lines changed

7 files changed

+149
-16
lines changed

‎llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

Lines changed: 39 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -55,9 +55,16 @@ class RISCVExpandPseudo : public MachineFunctionPass {
5555
bool expandAtomicCmpXchg(MachineBasicBlock &MBB,
5656
MachineBasicBlock::iterator MBBI, bool IsMasked,
5757
int Width, MachineBasicBlock::iterator &NextMBBI);
58+
bool expandAuipcInstPair(MachineBasicBlock &MBB,
59+
MachineBasicBlock::iterator MBBI,
60+
MachineBasicBlock::iterator &NextMBBI,
61+
unsigned FlagsHi, unsigned SecondOpcode);
5862
bool expandLoadLocalAddress(MachineBasicBlock &MBB,
5963
MachineBasicBlock::iterator MBBI,
6064
MachineBasicBlock::iterator &NextMBBI);
65+
bool expandLoadAddress(MachineBasicBlock &MBB,
66+
MachineBasicBlock::iterator MBBI,
67+
MachineBasicBlock::iterator &NextMBBI);
6168
};
6269

6370
char RISCVExpandPseudo::ID = 0;
@@ -123,6 +130,8 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
123130
return expandAtomicCmpXchg(MBB, MBBI, true, 32, NextMBBI);
124131
case RISCV::PseudoLLA:
125132
return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
133+
case RISCV::PseudoLA:
134+
return expandLoadAddress(MBB, MBBI, NextMBBI);
126135
}
127136

128137
return false;
@@ -603,9 +612,10 @@ bool RISCVExpandPseudo::expandAtomicCmpXchg(
603612
return true;
604613
}
605614

606-
bool RISCVExpandPseudo::expandLoadLocalAddress(
615+
bool RISCVExpandPseudo::expandAuipcInstPair(
607616
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
608-
MachineBasicBlock::iterator &NextMBBI) {
617+
MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
618+
unsigned SecondOpcode) {
609619
MachineFunction *MF = MBB.getParent();
610620
MachineInstr &MI = *MBBI;
611621
DebugLoc DL = MI.getDebugLoc();
@@ -622,8 +632,8 @@ bool RISCVExpandPseudo::expandLoadLocalAddress(
622632
MF->insert(++MBB.getIterator(), NewMBB);
623633

624634
BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg)
625-
.addDisp(Symbol, 0, RISCVII::MO_PCREL_HI);
626-
BuildMI(NewMBB, DL, TII->get(RISCV::ADDI), DestReg)
635+
.addDisp(Symbol, 0, FlagsHi);
636+
BuildMI(NewMBB, DL, TII->get(SecondOpcode), DestReg)
627637
.addReg(DestReg)
628638
.addMBB(NewMBB, RISCVII::MO_PCREL_LO);
629639

@@ -643,6 +653,31 @@ bool RISCVExpandPseudo::expandLoadLocalAddress(
643653
return true;
644654
}
645655

656+
bool RISCVExpandPseudo::expandLoadLocalAddress(
657+
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
658+
MachineBasicBlock::iterator &NextMBBI) {
659+
return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
660+
RISCV::ADDI);
661+
}
662+
663+
bool RISCVExpandPseudo::expandLoadAddress(
664+
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
665+
MachineBasicBlock::iterator &NextMBBI) {
666+
MachineFunction *MF = MBB.getParent();
667+
668+
unsigned SecondOpcode;
669+
unsigned FlagsHi;
670+
if (MF->getTarget().isPositionIndependent()) {
671+
const auto &STI = MF->getSubtarget<RISCVSubtarget>();
672+
SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
673+
FlagsHi = RISCVII::MO_GOT_HI;
674+
} else {
675+
SecondOpcode = RISCV::ADDI;
676+
FlagsHi = RISCVII::MO_PCREL_HI;
677+
}
678+
return expandAuipcInstPair(MBB, MBBI, NextMBBI, FlagsHi, SecondOpcode);
679+
}
680+
646681
} // end of anonymous namespace
647682

648683
INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 19 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -374,10 +374,25 @@ static SDValue getTargetNode(ConstantPoolSDNode *N, SDLoc DL, EVT Ty,
374374
}
375375

376376
template <class NodeTy>
377-
SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG) const {
377+
SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
378+
bool IsLocal) const {
378379
SDLoc DL(N);
379380
EVT Ty = getPointerTy(DAG.getDataLayout());
380381

382+
if (isPositionIndependent()) {
383+
SDValue Addr = getTargetNode(N, DL, Ty, DAG, 0);
384+
if (IsLocal)
385+
// Use PC-relative addressing to access the symbol. This generates the
386+
// pattern (PseudoLLA sym), which expands to (addi (auipc %pcrel_hi(sym))
387+
// %pcrel_lo(auipc)).
388+
return SDValue(DAG.getMachineNode(RISCV::PseudoLLA, DL, Ty, Addr), 0);
389+
390+
// Use PC-relative addressing to access the GOT for this symbol, then load
391+
// the address from the GOT. This generates the pattern (PseudoLA sym),
392+
// which expands to (ld (addi (auipc %got_pcrel_hi(sym)) %pcrel_lo(auipc))).
393+
return SDValue(DAG.getMachineNode(RISCV::PseudoLA, DL, Ty, Addr), 0);
394+
}
395+
381396
switch (getTargetMachine().getCodeModel()) {
382397
default:
383398
report_fatal_error("Unsupported code model for lowering");
@@ -407,10 +422,9 @@ SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op,
407422
int64_t Offset = N->getOffset();
408423
MVT XLenVT = Subtarget.getXLenVT();
409424

410-
if (isPositionIndependent())
411-
report_fatal_error("Unable to lowerGlobalAddress");
412-
413-
SDValue Addr = getAddr(N, DAG);
425+
const GlobalValue *GV = N->getGlobal();
426+
bool IsLocal = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
427+
SDValue Addr = getAddr(N, DAG, IsLocal);
414428

415429
// In order to maximise the opportunity for common subexpression elimination,
416430
// emit a separate ADD node for the global address offset instead of folding
@@ -426,19 +440,13 @@ SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op,
426440
SelectionDAG &DAG) const {
427441
BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
428442

429-
if (isPositionIndependent())
430-
report_fatal_error("Unable to lowerBlockAddress");
431-
432443
return getAddr(N, DAG);
433444
}
434445

435446
SDValue RISCVTargetLowering::lowerConstantPool(SDValue Op,
436447
SelectionDAG &DAG) const {
437448
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
438449

439-
if (isPositionIndependent())
440-
report_fatal_error("Unable to lowerConstantPool");
441-
442450
return getAddr(N, DAG);
443451
}
444452

‎llvm/lib/Target/RISCV/RISCVISelLowering.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -136,7 +136,7 @@ class RISCVTargetLowering : public TargetLowering {
136136
}
137137

138138
template <class NodeTy>
139-
SDValue getAddr(NodeTy *N, SelectionDAG &DAG) const;
139+
SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
140140

141141
SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
142142
SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -440,6 +440,7 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
440440
case RISCV::PseudoCALL:
441441
case RISCV::PseudoTAIL:
442442
case RISCV::PseudoLLA:
443+
case RISCV::PseudoLA:
443444
return 8;
444445
case TargetOpcode::INLINEASM: {
445446
const MachineFunction &MF = *MI.getParent()->getParent();

‎llvm/lib/Target/RISCV/RISCVMCInstLower.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,9 @@ static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
4949
case RISCVII::MO_PCREL_HI:
5050
Kind = RISCVMCExpr::VK_RISCV_PCREL_HI;
5151
break;
52+
case RISCVII::MO_GOT_HI:
53+
Kind = RISCVMCExpr::VK_RISCV_GOT_HI;
54+
break;
5255
}
5356

5457
const MCExpr *ME =

‎llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,6 +53,7 @@ enum {
5353
MO_HI,
5454
MO_PCREL_LO,
5555
MO_PCREL_HI,
56+
MO_GOT_HI,
5657
};
5758
} // namespace RISCVII
5859

‎llvm/test/CodeGen/RISCV/pic-models.ll

Lines changed: 85 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,85 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=riscv32 -relocation-model=static < %s \
3+
; RUN: | FileCheck -check-prefix=RV32-STATIC %s
4+
; RUN: llc -mtriple=riscv32 -relocation-model=pic < %s \
5+
; RUN: | FileCheck -check-prefix=RV32-PIC %s
6+
; RUN: llc -mtriple=riscv64 -relocation-model=static < %s \
7+
; RUN: | FileCheck -check-prefix=RV64-STATIC %s
8+
; RUN: llc -mtriple=riscv64 -relocation-model=pic < %s \
9+
; RUN: | FileCheck -check-prefix=RV64-PIC %s
10+
11+
; Check basic lowering of PIC addressing.
12+
; TODO: Check other relocation models?
13+
14+
@external_var = external global i32
15+
@internal_var = internal global i32 42
16+
17+
18+
; external address
19+
20+
define i32* @f1() nounwind {
21+
; RV32-STATIC-LABEL: f1:
22+
; RV32-STATIC: # %bb.0: # %entry
23+
; RV32-STATIC-NEXT: lui a0, %hi(external_var)
24+
; RV32-STATIC-NEXT: addi a0, a0, %lo(external_var)
25+
; RV32-STATIC-NEXT: ret
26+
;
27+
; RV32-PIC-LABEL: f1:
28+
; RV32-PIC: # %bb.0: # %entry
29+
; RV32-PIC-NEXT: .LBB0_1: # %entry
30+
; RV32-PIC-NEXT: # Label of block must be emitted
31+
; RV32-PIC-NEXT: auipc a0, %got_pcrel_hi(external_var)
32+
; RV32-PIC-NEXT: lw a0, %pcrel_lo(.LBB0_1)(a0)
33+
; RV32-PIC-NEXT: ret
34+
;
35+
; RV64-STATIC-LABEL: f1:
36+
; RV64-STATIC: # %bb.0: # %entry
37+
; RV64-STATIC-NEXT: lui a0, %hi(external_var)
38+
; RV64-STATIC-NEXT: addi a0, a0, %lo(external_var)
39+
; RV64-STATIC-NEXT: ret
40+
;
41+
; RV64-PIC-LABEL: f1:
42+
; RV64-PIC: # %bb.0: # %entry
43+
; RV64-PIC-NEXT: .LBB0_1: # %entry
44+
; RV64-PIC-NEXT: # Label of block must be emitted
45+
; RV64-PIC-NEXT: auipc a0, %got_pcrel_hi(external_var)
46+
; RV64-PIC-NEXT: ld a0, %pcrel_lo(.LBB0_1)(a0)
47+
; RV64-PIC-NEXT: ret
48+
entry:
49+
ret i32* @external_var
50+
}
51+
52+
53+
; internal address
54+
55+
define i32* @f2() nounwind {
56+
; RV32-STATIC-LABEL: f2:
57+
; RV32-STATIC: # %bb.0: # %entry
58+
; RV32-STATIC-NEXT: lui a0, %hi(internal_var)
59+
; RV32-STATIC-NEXT: addi a0, a0, %lo(internal_var)
60+
; RV32-STATIC-NEXT: ret
61+
;
62+
; RV32-PIC-LABEL: f2:
63+
; RV32-PIC: # %bb.0: # %entry
64+
; RV32-PIC-NEXT: .LBB1_1: # %entry
65+
; RV32-PIC-NEXT: # Label of block must be emitted
66+
; RV32-PIC-NEXT: auipc a0, %pcrel_hi(internal_var)
67+
; RV32-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB1_1)
68+
; RV32-PIC-NEXT: ret
69+
;
70+
; RV64-STATIC-LABEL: f2:
71+
; RV64-STATIC: # %bb.0: # %entry
72+
; RV64-STATIC-NEXT: lui a0, %hi(internal_var)
73+
; RV64-STATIC-NEXT: addi a0, a0, %lo(internal_var)
74+
; RV64-STATIC-NEXT: ret
75+
;
76+
; RV64-PIC-LABEL: f2:
77+
; RV64-PIC: # %bb.0: # %entry
78+
; RV64-PIC-NEXT: .LBB1_1: # %entry
79+
; RV64-PIC-NEXT: # Label of block must be emitted
80+
; RV64-PIC-NEXT: auipc a0, %pcrel_hi(internal_var)
81+
; RV64-PIC-NEXT: addi a0, a0, %pcrel_lo(.LBB1_1)
82+
; RV64-PIC-NEXT: ret
83+
entry:
84+
ret i32* @internal_var
85+
}

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