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[AMDGPU] Make OMod explicit for V_CVT_{U,I}*
Make OMod explicit instead of implied by HasModifiers in the operand list. Requires explicitly setting HasOMod=1 for irregular OMod usage in instruction V_CVT_{U,I}* Reviewed By: foad Differential Revision: https://reviews.llvm.org/D97587 Change-Id: I230e1476f529e816eec60e242531f23a99e3839f
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5 files changed

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‎llvm/lib/Target/AMDGPU/SIInstrInfo.td‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1623,8 +1623,11 @@ class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
16231623
!if (!eq(NumSrcArgs, 1),
16241624
!if (HasModifiers,
16251625
// VOP1 with modifiers
1626-
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1627-
clampmod0:$clamp, omod0:$omod)
1626+
!if(HasOMod,
1627+
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1628+
clampmod0:$clamp, omod0:$omod),
1629+
(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1630+
clampmod0:$clamp))
16281631
/* else */,
16291632
// VOP1 without modifiers
16301633
!if (HasClamp,

‎llvm/lib/Target/AMDGPU/VOP1Instructions.td‎

Lines changed: 23 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -144,6 +144,15 @@ def VOP1_F64_I32 : VOPProfileI2F <f64, i32>;
144144
def VOP1_F32_I32 : VOPProfileI2F <f32, i32>;
145145
def VOP1_F16_I16 : VOPProfileI2F <f16, i16>;
146146

147+
class VOP_SPECIAL_OMOD_PROF<ValueType dstVt, ValueType srcVt> :
148+
VOPProfile<[dstVt, srcVt, untyped, untyped]> {
149+
150+
let HasOMod = 1;
151+
}
152+
def VOP_I32_F32_SPECIAL_OMOD : VOP_SPECIAL_OMOD_PROF<i32, f32>;
153+
def VOP_I32_F64_SPECIAL_OMOD : VOP_SPECIAL_OMOD_PROF<i32, f64>;
154+
def VOP_I16_F16_SPECIAL_OMOD : VOP_SPECIAL_OMOD_PROF<i16, f16>;
155+
147156
//===----------------------------------------------------------------------===//
148157
// VOP1 Instructions
149158
//===----------------------------------------------------------------------===//
@@ -188,15 +197,17 @@ def V_READFIRSTLANE_B32 :
188197
}
189198

190199
let SchedRW = [WriteDoubleCvt] in {
191-
defm V_CVT_I32_F64 : VOP1Inst <"v_cvt_i32_f64", VOP_I32_F64, fp_to_sint>;
200+
// OMod clears exceptions when set in this instruction
201+
defm V_CVT_I32_F64 : VOP1Inst <"v_cvt_i32_f64", VOP_I32_F64_SPECIAL_OMOD, fp_to_sint>;
192202

193203
let mayRaiseFPException = 0 in {
194204
defm V_CVT_F64_I32 : VOP1Inst <"v_cvt_f64_i32", VOP1_F64_I32, sint_to_fp>;
195205
}
196206

197207
defm V_CVT_F32_F64 : VOP1Inst <"v_cvt_f32_f64", VOP_F32_F64, fpround>;
198208
defm V_CVT_F64_F32 : VOP1Inst <"v_cvt_f64_f32", VOP_F64_F32, fpextend>;
199-
defm V_CVT_U32_F64 : VOP1Inst <"v_cvt_u32_f64", VOP_I32_F64, fp_to_uint>;
209+
// OMod clears exceptions when set in this instruction
210+
defm V_CVT_U32_F64 : VOP1Inst <"v_cvt_u32_f64", VOP_I32_F64_SPECIAL_OMOD, fp_to_uint>;
200211

201212
let mayRaiseFPException = 0 in {
202213
defm V_CVT_F64_U32 : VOP1Inst <"v_cvt_f64_u32", VOP1_F64_I32, uint_to_fp>;
@@ -213,8 +224,9 @@ defm V_CVT_F32_I32 : VOP1Inst <"v_cvt_f32_i32", VOP1_F32_I32, sint_to_fp>;
213224
defm V_CVT_F32_U32 : VOP1Inst <"v_cvt_f32_u32", VOP1_F32_I32, uint_to_fp>;
214225
}
215226

216-
defm V_CVT_U32_F32 : VOP1Inst <"v_cvt_u32_f32", VOP_I32_F32, fp_to_uint>;
217-
defm V_CVT_I32_F32 : VOP1Inst <"v_cvt_i32_f32", VOP_I32_F32, fp_to_sint>;
227+
// OMod clears exceptions when set in these 2 instructions
228+
defm V_CVT_U32_F32 : VOP1Inst <"v_cvt_u32_f32", VOP_I32_F32_SPECIAL_OMOD, fp_to_uint>;
229+
defm V_CVT_I32_F32 : VOP1Inst <"v_cvt_i32_f32", VOP_I32_F32_SPECIAL_OMOD, fp_to_sint>;
218230
let FPDPRounding = 1 in {
219231
defm V_CVT_F16_F32 : VOP1Inst <"v_cvt_f16_f32", VOP_F16_F32, fpround>;
220232
} // End FPDPRounding = 1
@@ -268,7 +280,7 @@ defm V_FFBL_B32 : VOP1Inst <"v_ffbl_b32", VOP_I32_I32, AMDGPUffbl_b32>;
268280
defm V_FFBH_I32 : VOP1Inst <"v_ffbh_i32", VOP_I32_I32, AMDGPUffbh_i32>;
269281

270282
let SchedRW = [WriteDoubleAdd] in {
271-
defm V_FREXP_EXP_I32_F64 : VOP1Inst <"v_frexp_exp_i32_f64", VOP_I32_F64, int_amdgcn_frexp_exp>;
283+
defm V_FREXP_EXP_I32_F64 : VOP1Inst <"v_frexp_exp_i32_f64", VOP_I32_F64_SPECIAL_OMOD, int_amdgcn_frexp_exp>;
272284
defm V_FREXP_MANT_F64 : VOP1Inst <"v_frexp_mant_f64", VOP_F64_F64, int_amdgcn_frexp_mant>;
273285
let FPDPRounding = 1 in {
274286
defm V_FRACT_F64 : VOP1Inst <"v_fract_f64", VOP_F64_F64, AMDGPUfract>;
@@ -381,8 +393,9 @@ let FPDPRounding = 1 in {
381393
defm V_CVT_F16_U16 : VOP1Inst <"v_cvt_f16_u16", VOP1_F16_I16, uint_to_fp>;
382394
defm V_CVT_F16_I16 : VOP1Inst <"v_cvt_f16_i16", VOP1_F16_I16, sint_to_fp>;
383395
} // End FPDPRounding = 1
384-
defm V_CVT_U16_F16 : VOP1Inst <"v_cvt_u16_f16", VOP_I16_F16, fp_to_uint>;
385-
defm V_CVT_I16_F16 : VOP1Inst <"v_cvt_i16_f16", VOP_I16_F16, fp_to_sint>;
396+
// OMod clears exceptions when set in these two instructions
397+
defm V_CVT_U16_F16 : VOP1Inst <"v_cvt_u16_f16", VOP_I16_F16_SPECIAL_OMOD, fp_to_uint>;
398+
defm V_CVT_I16_F16 : VOP1Inst <"v_cvt_i16_f16", VOP_I16_F16_SPECIAL_OMOD, fp_to_sint>;
386399
let TRANS = 1, SchedRW = [WriteTrans32] in {
387400
defm V_RCP_F16 : VOP1Inst <"v_rcp_f16", VOP_F16_F16, AMDGPUrcp>;
388401
defm V_SQRT_F16 : VOP1Inst <"v_sqrt_f16", VOP_F16_F16, any_amdgcn_sqrt>;
@@ -393,7 +406,7 @@ defm V_SIN_F16 : VOP1Inst <"v_sin_f16", VOP_F16_F16, AMDGPUsin>;
393406
defm V_COS_F16 : VOP1Inst <"v_cos_f16", VOP_F16_F16, AMDGPUcos>;
394407
} // End TRANS = 1, SchedRW = [WriteTrans32]
395408
defm V_FREXP_MANT_F16 : VOP1Inst <"v_frexp_mant_f16", VOP_F16_F16, int_amdgcn_frexp_mant>;
396-
defm V_FREXP_EXP_I16_F16 : VOP1Inst <"v_frexp_exp_i16_f16", VOP_I16_F16, int_amdgcn_frexp_exp>;
409+
defm V_FREXP_EXP_I16_F16 : VOP1Inst <"v_frexp_exp_i16_f16", VOP_I16_F16_SPECIAL_OMOD, int_amdgcn_frexp_exp>;
397410
defm V_FLOOR_F16 : VOP1Inst <"v_floor_f16", VOP_F16_F16, ffloor>;
398411
defm V_CEIL_F16 : VOP1Inst <"v_ceil_f16", VOP_F16_F16, fceil>;
399412
defm V_TRUNC_F16 : VOP1Inst <"v_trunc_f16", VOP_F16_F16, ftrunc>;
@@ -437,8 +450,8 @@ let SubtargetPredicate = isGFX9Plus in {
437450
defm V_SAT_PK_U8_I16 : VOP1Inst<"v_sat_pk_u8_i16", VOP_I32_I32>;
438451

439452
let mayRaiseFPException = 0 in {
440-
defm V_CVT_NORM_I16_F16 : VOP1Inst<"v_cvt_norm_i16_f16", VOP_I16_F16>;
441-
defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16>;
453+
defm V_CVT_NORM_I16_F16 : VOP1Inst<"v_cvt_norm_i16_f16", VOP_I16_F16_SPECIAL_OMOD>;
454+
defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16_SPECIAL_OMOD>;
442455
} // End mayRaiseFPException = 0
443456
} // End SubtargetPredicate = isGFX9Plus
444457

‎llvm/test/MC/AMDGPU/gfx10_asm_vop1.s‎

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -367,6 +367,12 @@ v_cvt_i32_f64_e64 v5, |v[1:2]|
367367
v_cvt_i32_f64_e64 v5, v[1:2] clamp
368368
// GFX10: encoding: [0x05,0x80,0x83,0xd5,0x01,0x01,0x00,0x00]
369369

370+
v_cvt_i32_f64_e64 v5, s[4:5] mul:2
371+
// GFX10: encoding: [0x05,0x00,0x83,0xd5,0x04,0x00,0x00,0x08]
372+
373+
v_cvt_i32_f64_e64 v5, v[1:2] clamp div:2
374+
// GFX10: encoding: [0x05,0x80,0x83,0xd5,0x01,0x01,0x00,0x18]
375+
370376
v_cvt_f64_i32_e32 v[5:6], v1
371377
// GFX10: encoding: [0x01,0x09,0x0a,0x7e]
372378

@@ -1126,6 +1132,12 @@ v_cvt_u32_f32_e64 v5, |v1|
11261132
v_cvt_u32_f32_e64 v5, v1 clamp
11271133
// GFX10: encoding: [0x05,0x80,0x87,0xd5,0x01,0x01,0x00,0x00]
11281134

1135+
v_cvt_u32_f32_e64 v5, s1 mul:2
1136+
// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x01,0x00,0x00,0x08]
1137+
1138+
v_cvt_u32_f32_e64 v5, v1 clamp div:2
1139+
// GFX10: encoding: [0x05,0x80,0x87,0xd5,0x01,0x01,0x00,0x18]
1140+
11291141
v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
11301142
// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
11311143

@@ -1393,6 +1405,12 @@ v_cvt_i32_f32_e64 v5, |v1|
13931405
v_cvt_i32_f32_e64 v5, v1 clamp
13941406
// GFX10: encoding: [0x05,0x80,0x88,0xd5,0x01,0x01,0x00,0x00]
13951407

1408+
v_cvt_i32_f32_e64 v5, v1 mul:2
1409+
// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x01,0x01,0x00,0x08]
1410+
1411+
v_cvt_i32_f32_e64 v5, v1 clamp div:2
1412+
// GFX10: encoding: [0x05,0x80,0x88,0xd5,0x01,0x01,0x00,0x18]
1413+
13961414
v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
13971415
// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
13981416

@@ -4330,6 +4348,12 @@ v_cvt_u32_f64_e64 v5, |v[1:2]|
43304348
v_cvt_u32_f64_e64 v5, v[1:2] clamp
43314349
// GFX10: encoding: [0x05,0x80,0x95,0xd5,0x01,0x01,0x00,0x00]
43324350

4351+
v_cvt_u32_f64_e64 v5, s[4:5] mul:2
4352+
// GFX10: encoding: [0x05,0x00,0x95,0xd5,0x04,0x00,0x00,0x08]
4353+
4354+
v_cvt_u32_f64_e64 v5, v[1:2] clamp div:2
4355+
// GFX10: encoding: [0x05,0x80,0x95,0xd5,0x01,0x01,0x00,0x18]
4356+
43334357
v_cvt_f64_u32 v[5:6], v1
43344358
// GFX10: encoding: [0x01,0x2d,0x0a,0x7e]
43354359

@@ -11719,6 +11743,12 @@ v_cvt_u16_f16_e64 v5, |v1|
1171911743
v_cvt_u16_f16_e64 v5, v1 clamp
1172011744
// GFX10: encoding: [0x05,0x80,0xd2,0xd5,0x01,0x01,0x00,0x00]
1172111745

11746+
v_cvt_u16_f16_e64 v5, s1 mul:2
11747+
// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x01,0x00,0x00,0x08]
11748+
11749+
v_cvt_u16_f16_e64 v5, v1 clamp div:2
11750+
// GFX10: encoding: [0x05,0x80,0xd2,0xd5,0x01,0x01,0x00,0x18]
11751+
1172211752
v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
1172311753
// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x06,0x00]
1172411754

@@ -11974,6 +12004,12 @@ v_cvt_i16_f16_e64 v5, |v1|
1197412004
v_cvt_i16_f16_e64 v5, v1 clamp
1197512005
// GFX10: encoding: [0x05,0x80,0xd3,0xd5,0x01,0x01,0x00,0x00]
1197612006

12007+
v_cvt_i16_f16_e64 v5, v1 mul:2
12008+
// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x01,0x01,0x00,0x08]
12009+
12010+
v_cvt_i16_f16_e64 v5, v1 clamp div:2
12011+
// GFX10: encoding: [0x05,0x80,0xd3,0xd5,0x01,0x01,0x00,0x18]
12012+
1197712013
v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
1197812014
// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x06,0x00]
1197912015

‎llvm/test/MC/AMDGPU/gfx9_asm_vop3.s‎

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -258,6 +258,12 @@ v_cvt_i32_f64_e64 v5, |v[1:2]|
258258
v_cvt_i32_f64_e64 v5, v[1:2] clamp
259259
// CHECK: [0x05,0x80,0x43,0xd1,0x01,0x01,0x00,0x00]
260260

261+
v_cvt_i32_f64_e64 v5, s[4:5] mul:2
262+
// CHECK: [0x05,0x00,0x43,0xd1,0x04,0x00,0x00,0x08]
263+
264+
v_cvt_i32_f64_e64 v5, v[1:2] clamp div:2
265+
// CHECK: [0x05,0x80,0x43,0xd1,0x01,0x01,0x00,0x18]
266+
261267
v_cvt_f64_i32_e64 v[5:6], v1
262268
// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x01,0x00,0x00]
263269

@@ -555,6 +561,12 @@ v_cvt_u32_f32_e64 v5, |v1|
555561
v_cvt_u32_f32_e64 v5, v1 clamp
556562
// CHECK: [0x05,0x80,0x47,0xd1,0x01,0x01,0x00,0x00]
557563

564+
v_cvt_u32_f32_e64 v5, s1 mul:2
565+
// CHECK: [0x05,0x00,0x47,0xd1,0x01,0x00,0x00,0x08]
566+
567+
v_cvt_u32_f32_e64 v5, v1 clamp div:2
568+
// CHECK: [0x05,0x80,0x47,0xd1,0x01,0x01,0x00,0x18]
569+
558570
v_cvt_i32_f32_e64 v5, v1
559571
// CHECK: [0x05,0x00,0x48,0xd1,0x01,0x01,0x00,0x00]
560572

@@ -627,6 +639,12 @@ v_cvt_i32_f32_e64 v5, |v1|
627639
v_cvt_i32_f32_e64 v5, v1 clamp
628640
// CHECK: [0x05,0x80,0x48,0xd1,0x01,0x01,0x00,0x00]
629641

642+
v_cvt_i32_f32_e64 v5, v1 mul:2
643+
// CHECK: [0x05,0x00,0x48,0xd1,0x01,0x01,0x00,0x08]
644+
645+
v_cvt_i32_f32_e64 v5, v1 clamp div:2
646+
// CHECK: [0x05,0x80,0x48,0xd1,0x01,0x01,0x00,0x18]
647+
630648
v_cvt_f16_f32_e64 v5, v1
631649
// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x00]
632650

@@ -1512,6 +1530,12 @@ v_cvt_u32_f64_e64 v5, |v[1:2]|
15121530
v_cvt_u32_f64_e64 v5, v[1:2] clamp
15131531
// CHECK: [0x05,0x80,0x55,0xd1,0x01,0x01,0x00,0x00]
15141532

1533+
v_cvt_u32_f64_e64 v5, s[4:5] mul:2
1534+
// CHECK: [0x05,0x00,0x55,0xd1,0x04,0x00,0x00,0x08]
1535+
1536+
v_cvt_u32_f64_e64 v5, v[1:2] clamp div:2
1537+
// CHECK: [0x05,0x80,0x55,0xd1,0x01,0x01,0x00,0x18]
1538+
15151539
v_cvt_f64_u32_e64 v[5:6], v1
15161540
// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x01,0x00,0x00]
15171541

@@ -3495,6 +3519,9 @@ v_frexp_exp_i32_f64_e64 v5, -v[1:2]
34953519
v_frexp_exp_i32_f64_e64 v5, |v[1:2]|
34963520
// CHECK: [0x05,0x01,0x70,0xd1,0x01,0x01,0x00,0x00]
34973521

3522+
v_frexp_exp_i32_f64_e64 v5, s[4:5] mul:2
3523+
// CHECK: [0x05,0x00,0x70,0xd1,0x04,0x00,0x00,0x08]
3524+
34983525
v_frexp_mant_f64_e64 v[5:6], v[1:2]
34993526
// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x00]
35003527

@@ -4041,6 +4068,12 @@ v_cvt_u16_f16_e64 v5, |v1|
40414068
v_cvt_u16_f16_e64 v5, v1 clamp
40424069
// CHECK: [0x05,0x80,0x7b,0xd1,0x01,0x01,0x00,0x00]
40434070

4071+
v_cvt_u16_f16_e64 v5, s1 mul:2
4072+
// CHECK: [0x05,0x00,0x7b,0xd1,0x01,0x00,0x00,0x08]
4073+
4074+
v_cvt_u16_f16_e64 v5, v1 clamp div:2
4075+
// CHECK: [0x05,0x80,0x7b,0xd1,0x01,0x01,0x00,0x18]
4076+
40444077
v_cvt_i16_f16_e64 v5, v1
40454078
// CHECK: [0x05,0x00,0x7c,0xd1,0x01,0x01,0x00,0x00]
40464079

@@ -4113,6 +4146,12 @@ v_cvt_i16_f16_e64 v5, |v1|
41134146
v_cvt_i16_f16_e64 v5, v1 clamp
41144147
// CHECK: [0x05,0x80,0x7c,0xd1,0x01,0x01,0x00,0x00]
41154148

4149+
v_cvt_i16_f16_e64 v5, v1 mul:2
4150+
// CHECK: [0x05,0x00,0x7c,0xd1,0x01,0x01,0x00,0x08]
4151+
4152+
v_cvt_i16_f16_e64 v5, v1 clamp div:2
4153+
// CHECK: [0x05,0x80,0x7c,0xd1,0x01,0x01,0x00,0x18]
4154+
41164155
v_rcp_f16_e64 v5, v1
41174156
// CHECK: [0x05,0x00,0x7d,0xd1,0x01,0x01,0x00,0x00]
41184157

@@ -4614,6 +4653,9 @@ v_frexp_exp_i16_f16_e64 v5, -v1
46144653
v_frexp_exp_i16_f16_e64 v5, |v1|
46154654
// CHECK: [0x05,0x01,0x83,0xd1,0x01,0x01,0x00,0x00]
46164655

4656+
v_frexp_exp_i16_f16_e64 v5, s1 mul:2
4657+
// CHECK: [0x05,0x00,0x83,0xd1,0x01,0x00,0x00,0x08]
4658+
46174659
v_floor_f16_e64 v5, v1
46184660
// CHECK: [0x05,0x00,0x84,0xd1,0x01,0x01,0x00,0x00]
46194661

@@ -5352,6 +5394,9 @@ v_cvt_norm_i16_f16_e64 v5, |v1|
53525394
v_cvt_norm_i16_f16_e64 v5, v1 clamp
53535395
// CHECK: [0x05,0x80,0x8d,0xd1,0x01,0x01,0x00,0x00]
53545396

5397+
v_cvt_norm_i16_f16_e64 v5, v1 mul:2
5398+
// CHECK: [0x05,0x00,0x8d,0xd1,0x01,0x01,0x00,0x08]
5399+
53555400
v_cvt_norm_u16_f16_e64 v5, v1
53565401
// CHECK: [0x05,0x00,0x8e,0xd1,0x01,0x01,0x00,0x00]
53575402

@@ -5424,6 +5469,9 @@ v_cvt_norm_u16_f16_e64 v5, |v1|
54245469
v_cvt_norm_u16_f16_e64 v5, v1 clamp
54255470
// CHECK: [0x05,0x80,0x8e,0xd1,0x01,0x01,0x00,0x00]
54265471

5472+
v_cvt_norm_u16_f16_e64 v5, v1 mul:2
5473+
// CHECK: [0x05,0x00,0x8e,0xd1,0x01,0x01,0x00,0x08]
5474+
54275475
v_sat_pk_u8_i16_e64 v5, v1
54285476
// CHECK: [0x05,0x00,0x8f,0xd1,0x01,0x01,0x00,0x00]
54295477

‎llvm/test/MC/AMDGPU/vop3-errs.s‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -43,9 +43,6 @@ v_cmp_eq_f32_e64 vcc, v0, v1 mul:2
4343
v_cmp_le_f64_e64 vcc, v0, v1 mul:4
4444
// GCN: error: invalid operand for instruction
4545

46-
v_cvt_u32_f32_e64 v0, v1 div:2
47-
// GCN: error: invalid operand for instruction
48-
4946
//
5047
// mul
5148
//

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