From fa353402d2081c1d5cef3b856e3b0a5fe0abf014 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?=
 <rcardenas.rod@gmail.com>
Date: Fri, 23 Feb 2024 11:40:15 +0100
Subject: [PATCH] Add pre_init_trap

---
 riscv-rt/CHANGELOG.md |  4 ++++
 riscv-rt/src/asm.rs   | 19 +++++++++++++++----
 2 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index d482443d..ff85f0e0 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Added
+
+- Add `pre_init_trap` to detect early errors during the boot process.
+
 ### Changed
 
 - Moved all the assembly code to `asm.rs`
diff --git a/riscv-rt/src/asm.rs b/riscv-rt/src/asm.rs
index 820b17f5..2cdcf46e 100644
--- a/riscv-rt/src/asm.rs
+++ b/riscv-rt/src/asm.rs
@@ -66,12 +66,19 @@ _abs_start:
     .option norelax
     .cfi_startproc
     .cfi_undefined ra",
+    // Disable interrupts
     #[cfg(feature = "s-mode")]
     "csrw sie, 0
     csrw sip, 0",
     #[cfg(not(feature = "s-mode"))]
     "csrw mie, 0
     csrw mip, 0",
+    // Set pre-init trap vector
+    "la t0, pre_init_trap",
+    #[cfg(feature = "s-mode")]
+    "csrw stvec, t0",
+    #[cfg(not(feature = "s-mode"))]
+    "csrw mtvec, t0",
 );
 
 // ZERO OUT GENERAL-PURPOSE REGISTERS
@@ -280,10 +287,14 @@ trap_handler!(
      (a0, 8), (a1, 9), (a2, 10), (a3, 11), (a4, 12), (a5, 13), (a6, 14), (a7, 15)]
 );
 
-// Make sure there is an abort when linking
+#[rustfmt::skip]
 global_asm!(
     ".section .text.abort
-     .globl abort
-abort:
-    j abort"
+    .global abort
+abort:  // make sure there is an abort symbol when linking
+    j abort
+
+    .align  2
+pre_init_trap:  // if you end up here, there is a bug in the boot code
+    j pre_init_trap"
 );