From c0e7dcb9334e735040d7a7e1c3f44cadc61fec73 Mon Sep 17 00:00:00 2001
From: Jorge Aparicio <jorge@japaric.io>
Date: Wed, 28 Jun 2017 22:26:43 -0500
Subject: [PATCH 1/2] don't expose registers clidr, ctr, ccsidr, csselr to
 ARMv6-M targets

as these are only available on ARMv7-M devices

closes #46
---
 src/peripheral/mod.rs | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs
index 1b21bc54..e210c791 100644
--- a/src/peripheral/mod.rs
+++ b/src/peripheral/mod.rs
@@ -104,12 +104,16 @@ pub struct Cpuid {
     pub isar: [RO<u32>; 5],
     reserved1: u32,
     /// Cache Level ID
+    #[cfg(armv7m)]
     pub clidr: RO<u32>,
     /// Cache Type
+    #[cfg(armv7m)]
     pub ctr: RO<u32>,
     /// Cache Size ID
+    #[cfg(armv7m)]
     pub ccsidr: RO<u32>,
     /// Cache Size Selection
+    #[cfg(armv7m)]
     pub csselr: RW<u32>,
 }
 

From 58b53670ca6a27c0a7007068f0886330ca448de8 Mon Sep 17 00:00:00 2001
From: Jorge Aparicio <jorge@japaric.io>
Date: Fri, 30 Jun 2017 12:23:39 -0500
Subject: [PATCH 2/2] unbreak test

---
 src/peripheral/mod.rs | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/peripheral/mod.rs b/src/peripheral/mod.rs
index e210c791..7750c47b 100644
--- a/src/peripheral/mod.rs
+++ b/src/peripheral/mod.rs
@@ -104,16 +104,16 @@ pub struct Cpuid {
     pub isar: [RO<u32>; 5],
     reserved1: u32,
     /// Cache Level ID
-    #[cfg(armv7m)]
+    #[cfg(any(armv7m, test))]
     pub clidr: RO<u32>,
     /// Cache Type
-    #[cfg(armv7m)]
+    #[cfg(any(armv7m, test))]
     pub ctr: RO<u32>,
     /// Cache Size ID
-    #[cfg(armv7m)]
+    #[cfg(any(armv7m, test))]
     pub ccsidr: RO<u32>,
     /// Cache Size Selection
-    #[cfg(armv7m)]
+    #[cfg(any(armv7m, test))]
     pub csselr: RW<u32>,
 }