@@ -246,7 +246,7 @@ private int writeVarLocations(DebugContext context, DebugLocalInfo local, long b
246246 pos = writePrimitiveConstantLocation (context , value .constantValue (), buffer , pos );
247247 } else if (constant .isNull ()) {
248248 pos = writeNullConstantLocation (context , value .constantValue (), buffer , pos );
249- } else {
249+ } else {
250250 pos = writeObjectConstantLocation (context , value .constantValue (), value .heapOffset (), buffer , pos );
251251 }
252252 break ;
@@ -353,7 +353,7 @@ private int writePrimitiveConstantLocation(DebugContext context, JavaConstant co
353353 pos += putShort ((short ) byteCount , scratch , 0 );
354354 pos += putByte (op , scratch , 0 );
355355 pos += putULEB (dataByteCount , scratch , 0 );
356-
356+
357357 if (dataByteCount == 1 ) {
358358 if (kind == JavaKind .Boolean ) {
359359 pos += putByte ((byte ) (constant .asBoolean () ? 1 : 0 ), scratch , 0 );
@@ -388,7 +388,7 @@ private int writePrimitiveConstantLocation(DebugContext context, JavaConstant co
388388 long l = (kind == JavaKind .Long ? constant .asLong () : Double .doubleToRawLongBits (constant .asDouble ()));
389389 pos = putLong (l , buffer , pos );
390390 }
391- verboseLog (context , " [0x%08x] CONSTANT %s" , pos , constant .toValueString ());
391+ verboseLog (context , " [0x%08x] CONSTANT (primitive) %s" , pos , constant .toValueString ());
392392 }
393393 return pos ;
394394 }
@@ -410,15 +410,16 @@ private int writeNullConstantLocation(DebugContext context, JavaConstant constan
410410 pos = putByte (op , buffer , pos );
411411 pos = putULEB (dataByteCount , buffer , pos );
412412 pos = writeAttrData8 (0 , buffer , pos );
413- verboseLog (context , " [0x%08x] CONSTANT %s" , pos , constant .toValueString ());
413+ verboseLog (context , " [0x%08x] CONSTANT (null) %s" , pos , constant .toValueString ());
414414 }
415415 return pos ;
416416 }
417417
418418 private int writeObjectConstantLocation (DebugContext context , JavaConstant constant , long heapOffset , byte [] buffer , int p ) {
419419 assert constant .getJavaKind () == JavaKind .Object && !constant .isNull ();
420420 int pos = p ;
421- pos = writeHeapLocationLocList (heapOffset , buffer , pos ) ;
421+ pos = writeHeapLocationLocList (heapOffset , buffer , pos );
422+ verboseLog (context , " [0x%08x] CONSTANT (object) %s" , pos , constant .toValueString ());
422423 return pos ;
423424 }
424425
@@ -607,72 +608,72 @@ public enum DwarfRegEncodingAArch64 {
607608
608609 // map from compiler AArch64 register indices to corresponding dwarf AArch64 register index
609610 private static final int [] GRAAL_AARCH64_TO_DWARF_REG_MAP = {
610- DwarfRegEncodingAArch64 .R0 .encoding ,
611- DwarfRegEncodingAArch64 .R1 .encoding ,
612- DwarfRegEncodingAArch64 .R2 .encoding ,
613- DwarfRegEncodingAArch64 .R3 .encoding ,
614- DwarfRegEncodingAArch64 .R4 .encoding ,
615- DwarfRegEncodingAArch64 .R5 .encoding ,
616- DwarfRegEncodingAArch64 .R6 .encoding ,
617- DwarfRegEncodingAArch64 .R7 .encoding ,
618- DwarfRegEncodingAArch64 .R8 .encoding ,
619- DwarfRegEncodingAArch64 .R9 .encoding ,
620- DwarfRegEncodingAArch64 .R10 .encoding ,
621- DwarfRegEncodingAArch64 .R11 .encoding ,
622- DwarfRegEncodingAArch64 .R12 .encoding ,
623- DwarfRegEncodingAArch64 .R13 .encoding ,
624- DwarfRegEncodingAArch64 .R14 .encoding ,
625- DwarfRegEncodingAArch64 .R15 .encoding ,
626- DwarfRegEncodingAArch64 .R16 .encoding ,
627- DwarfRegEncodingAArch64 .R17 .encoding ,
628- DwarfRegEncodingAArch64 .R18 .encoding ,
629- DwarfRegEncodingAArch64 .R19 .encoding ,
630- DwarfRegEncodingAArch64 .R20 .encoding ,
631- DwarfRegEncodingAArch64 .R21 .encoding ,
632- DwarfRegEncodingAArch64 .R22 .encoding ,
633- DwarfRegEncodingAArch64 .R23 .encoding ,
634- DwarfRegEncodingAArch64 .R24 .encoding ,
635- DwarfRegEncodingAArch64 .R25 .encoding ,
636- DwarfRegEncodingAArch64 .R26 .encoding ,
637- DwarfRegEncodingAArch64 .R27 .encoding ,
638- DwarfRegEncodingAArch64 .R28 .encoding ,
639- DwarfRegEncodingAArch64 .R29 .encoding ,
640- DwarfRegEncodingAArch64 .R30 .encoding ,
641- DwarfRegEncodingAArch64 .R31 .encoding ,
642- DwarfRegEncodingAArch64 .ZR .encoding ,
643- DwarfRegEncodingAArch64 .SP .encoding ,
644- DwarfRegEncodingAArch64 .V0 .encoding ,
645- DwarfRegEncodingAArch64 .V1 .encoding ,
646- DwarfRegEncodingAArch64 .V2 .encoding ,
647- DwarfRegEncodingAArch64 .V3 .encoding ,
648- DwarfRegEncodingAArch64 .V4 .encoding ,
649- DwarfRegEncodingAArch64 .V5 .encoding ,
650- DwarfRegEncodingAArch64 .V6 .encoding ,
651- DwarfRegEncodingAArch64 .V7 .encoding ,
652- DwarfRegEncodingAArch64 .V8 .encoding ,
653- DwarfRegEncodingAArch64 .V9 .encoding ,
654- DwarfRegEncodingAArch64 .V10 .encoding ,
655- DwarfRegEncodingAArch64 .V11 .encoding ,
656- DwarfRegEncodingAArch64 .V12 .encoding ,
657- DwarfRegEncodingAArch64 .V13 .encoding ,
658- DwarfRegEncodingAArch64 .V14 .encoding ,
659- DwarfRegEncodingAArch64 .V15 .encoding ,
660- DwarfRegEncodingAArch64 .V16 .encoding ,
661- DwarfRegEncodingAArch64 .V17 .encoding ,
662- DwarfRegEncodingAArch64 .V18 .encoding ,
663- DwarfRegEncodingAArch64 .V19 .encoding ,
664- DwarfRegEncodingAArch64 .V20 .encoding ,
665- DwarfRegEncodingAArch64 .V21 .encoding ,
666- DwarfRegEncodingAArch64 .V22 .encoding ,
667- DwarfRegEncodingAArch64 .V23 .encoding ,
668- DwarfRegEncodingAArch64 .V24 .encoding ,
669- DwarfRegEncodingAArch64 .V25 .encoding ,
670- DwarfRegEncodingAArch64 .V26 .encoding ,
671- DwarfRegEncodingAArch64 .V27 .encoding ,
672- DwarfRegEncodingAArch64 .V28 .encoding ,
673- DwarfRegEncodingAArch64 .V29 .encoding ,
674- DwarfRegEncodingAArch64 .V30 .encoding ,
675- DwarfRegEncodingAArch64 .V31 .encoding ,
611+ DwarfRegEncodingAArch64 .R0 .encoding ,
612+ DwarfRegEncodingAArch64 .R1 .encoding ,
613+ DwarfRegEncodingAArch64 .R2 .encoding ,
614+ DwarfRegEncodingAArch64 .R3 .encoding ,
615+ DwarfRegEncodingAArch64 .R4 .encoding ,
616+ DwarfRegEncodingAArch64 .R5 .encoding ,
617+ DwarfRegEncodingAArch64 .R6 .encoding ,
618+ DwarfRegEncodingAArch64 .R7 .encoding ,
619+ DwarfRegEncodingAArch64 .R8 .encoding ,
620+ DwarfRegEncodingAArch64 .R9 .encoding ,
621+ DwarfRegEncodingAArch64 .R10 .encoding ,
622+ DwarfRegEncodingAArch64 .R11 .encoding ,
623+ DwarfRegEncodingAArch64 .R12 .encoding ,
624+ DwarfRegEncodingAArch64 .R13 .encoding ,
625+ DwarfRegEncodingAArch64 .R14 .encoding ,
626+ DwarfRegEncodingAArch64 .R15 .encoding ,
627+ DwarfRegEncodingAArch64 .R16 .encoding ,
628+ DwarfRegEncodingAArch64 .R17 .encoding ,
629+ DwarfRegEncodingAArch64 .R18 .encoding ,
630+ DwarfRegEncodingAArch64 .R19 .encoding ,
631+ DwarfRegEncodingAArch64 .R20 .encoding ,
632+ DwarfRegEncodingAArch64 .R21 .encoding ,
633+ DwarfRegEncodingAArch64 .R22 .encoding ,
634+ DwarfRegEncodingAArch64 .R23 .encoding ,
635+ DwarfRegEncodingAArch64 .R24 .encoding ,
636+ DwarfRegEncodingAArch64 .R25 .encoding ,
637+ DwarfRegEncodingAArch64 .R26 .encoding ,
638+ DwarfRegEncodingAArch64 .R27 .encoding ,
639+ DwarfRegEncodingAArch64 .R28 .encoding ,
640+ DwarfRegEncodingAArch64 .R29 .encoding ,
641+ DwarfRegEncodingAArch64 .R30 .encoding ,
642+ DwarfRegEncodingAArch64 .R31 .encoding ,
643+ DwarfRegEncodingAArch64 .ZR .encoding ,
644+ DwarfRegEncodingAArch64 .SP .encoding ,
645+ DwarfRegEncodingAArch64 .V0 .encoding ,
646+ DwarfRegEncodingAArch64 .V1 .encoding ,
647+ DwarfRegEncodingAArch64 .V2 .encoding ,
648+ DwarfRegEncodingAArch64 .V3 .encoding ,
649+ DwarfRegEncodingAArch64 .V4 .encoding ,
650+ DwarfRegEncodingAArch64 .V5 .encoding ,
651+ DwarfRegEncodingAArch64 .V6 .encoding ,
652+ DwarfRegEncodingAArch64 .V7 .encoding ,
653+ DwarfRegEncodingAArch64 .V8 .encoding ,
654+ DwarfRegEncodingAArch64 .V9 .encoding ,
655+ DwarfRegEncodingAArch64 .V10 .encoding ,
656+ DwarfRegEncodingAArch64 .V11 .encoding ,
657+ DwarfRegEncodingAArch64 .V12 .encoding ,
658+ DwarfRegEncodingAArch64 .V13 .encoding ,
659+ DwarfRegEncodingAArch64 .V14 .encoding ,
660+ DwarfRegEncodingAArch64 .V15 .encoding ,
661+ DwarfRegEncodingAArch64 .V16 .encoding ,
662+ DwarfRegEncodingAArch64 .V17 .encoding ,
663+ DwarfRegEncodingAArch64 .V18 .encoding ,
664+ DwarfRegEncodingAArch64 .V19 .encoding ,
665+ DwarfRegEncodingAArch64 .V20 .encoding ,
666+ DwarfRegEncodingAArch64 .V21 .encoding ,
667+ DwarfRegEncodingAArch64 .V22 .encoding ,
668+ DwarfRegEncodingAArch64 .V23 .encoding ,
669+ DwarfRegEncodingAArch64 .V24 .encoding ,
670+ DwarfRegEncodingAArch64 .V25 .encoding ,
671+ DwarfRegEncodingAArch64 .V26 .encoding ,
672+ DwarfRegEncodingAArch64 .V27 .encoding ,
673+ DwarfRegEncodingAArch64 .V28 .encoding ,
674+ DwarfRegEncodingAArch64 .V29 .encoding ,
675+ DwarfRegEncodingAArch64 .V30 .encoding ,
676+ DwarfRegEncodingAArch64 .V31 .encoding ,
676677 };
677678
678679 // register numbers used by DWARF for AMD64 registers
@@ -719,37 +720,37 @@ public enum DwarfRegEncodingAMD64 {
719720
720721 // map from compiler X86_64 register indices to corresponding dwarf AMD64 register index
721722 private static final int [] GRAAL_X86_64_TO_DWARF_REG_MAP = {
722- DwarfRegEncodingAMD64 .RAX .encoding ,
723- DwarfRegEncodingAMD64 .RCX .encoding ,
724- DwarfRegEncodingAMD64 .RDX .encoding ,
725- DwarfRegEncodingAMD64 .RBX .encoding ,
726- DwarfRegEncodingAMD64 .RSP .encoding ,
727- DwarfRegEncodingAMD64 .RBP .encoding ,
728- DwarfRegEncodingAMD64 .RSI .encoding ,
729- DwarfRegEncodingAMD64 .RDI .encoding ,
730- DwarfRegEncodingAMD64 .R8 .encoding ,
731- DwarfRegEncodingAMD64 .R9 .encoding ,
732- DwarfRegEncodingAMD64 .R10 .encoding ,
733- DwarfRegEncodingAMD64 .R11 .encoding ,
734- DwarfRegEncodingAMD64 .R12 .encoding ,
735- DwarfRegEncodingAMD64 .R13 .encoding ,
736- DwarfRegEncodingAMD64 .R14 .encoding ,
737- DwarfRegEncodingAMD64 .R15 .encoding ,
738- DwarfRegEncodingAMD64 .XMM0 .encoding ,
739- DwarfRegEncodingAMD64 .XMM1 .encoding ,
740- DwarfRegEncodingAMD64 .XMM2 .encoding ,
741- DwarfRegEncodingAMD64 .XMM3 .encoding ,
742- DwarfRegEncodingAMD64 .XMM4 .encoding ,
743- DwarfRegEncodingAMD64 .XMM5 .encoding ,
744- DwarfRegEncodingAMD64 .XMM6 .encoding ,
745- DwarfRegEncodingAMD64 .XMM7 .encoding ,
746- DwarfRegEncodingAMD64 .XMM8 .encoding ,
747- DwarfRegEncodingAMD64 .XMM9 .encoding ,
748- DwarfRegEncodingAMD64 .XMM10 .encoding ,
749- DwarfRegEncodingAMD64 .XMM11 .encoding ,
750- DwarfRegEncodingAMD64 .XMM12 .encoding ,
751- DwarfRegEncodingAMD64 .XMM13 .encoding ,
752- DwarfRegEncodingAMD64 .XMM14 .encoding ,
753- DwarfRegEncodingAMD64 .XMM15 .encoding ,
723+ DwarfRegEncodingAMD64 .RAX .encoding ,
724+ DwarfRegEncodingAMD64 .RCX .encoding ,
725+ DwarfRegEncodingAMD64 .RDX .encoding ,
726+ DwarfRegEncodingAMD64 .RBX .encoding ,
727+ DwarfRegEncodingAMD64 .RSP .encoding ,
728+ DwarfRegEncodingAMD64 .RBP .encoding ,
729+ DwarfRegEncodingAMD64 .RSI .encoding ,
730+ DwarfRegEncodingAMD64 .RDI .encoding ,
731+ DwarfRegEncodingAMD64 .R8 .encoding ,
732+ DwarfRegEncodingAMD64 .R9 .encoding ,
733+ DwarfRegEncodingAMD64 .R10 .encoding ,
734+ DwarfRegEncodingAMD64 .R11 .encoding ,
735+ DwarfRegEncodingAMD64 .R12 .encoding ,
736+ DwarfRegEncodingAMD64 .R13 .encoding ,
737+ DwarfRegEncodingAMD64 .R14 .encoding ,
738+ DwarfRegEncodingAMD64 .R15 .encoding ,
739+ DwarfRegEncodingAMD64 .XMM0 .encoding ,
740+ DwarfRegEncodingAMD64 .XMM1 .encoding ,
741+ DwarfRegEncodingAMD64 .XMM2 .encoding ,
742+ DwarfRegEncodingAMD64 .XMM3 .encoding ,
743+ DwarfRegEncodingAMD64 .XMM4 .encoding ,
744+ DwarfRegEncodingAMD64 .XMM5 .encoding ,
745+ DwarfRegEncodingAMD64 .XMM6 .encoding ,
746+ DwarfRegEncodingAMD64 .XMM7 .encoding ,
747+ DwarfRegEncodingAMD64 .XMM8 .encoding ,
748+ DwarfRegEncodingAMD64 .XMM9 .encoding ,
749+ DwarfRegEncodingAMD64 .XMM10 .encoding ,
750+ DwarfRegEncodingAMD64 .XMM11 .encoding ,
751+ DwarfRegEncodingAMD64 .XMM12 .encoding ,
752+ DwarfRegEncodingAMD64 .XMM13 .encoding ,
753+ DwarfRegEncodingAMD64 .XMM14 .encoding ,
754+ DwarfRegEncodingAMD64 .XMM15 .encoding ,
754755 };
755756}
0 commit comments