[GR-57104] Use r12 as zero value register where applicable.

PullRequest: graal/18684

Author: mur47x111

compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/asm/amd64/AMD64Assembler.java

@@ -512,7 +512,8 @@ public static class AMD64MROp extends AMD64RROp {
         // @formatter:off
         public static final AMD64MROp MOVB   = new AMD64MROp("MOVB", 0x88, OpAssertion.ByteAssertion);
         public static final AMD64MROp MOV    = new AMD64MROp("MOV",  0x89, OpAssertion.WordOrLargerAssertion);
-       // @formatter:on
+        public static final AMD64MROp TEST   = new AMD64MROp("TEST", 0x85, OpAssertion.WordOrLargerAssertion);
+        // @formatter:on
 
         protected AMD64MROp(String opcode, int op, OpAssertion assertion) {
             this(opcode, 0, 0, op, assertion, null);

compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/asm/amd64/AMD64MacroAssembler.java

@@ -299,7 +299,7 @@ public final void movdbl(AMD64Address dst, Register src) {
      */
     public final void movlong(AMD64Address dst, long src) {
         if (NumUtil.isInt(src)) {
-            AMD64MIOp.MOV.emit(this, OperandSize.QWORD, dst, (int) src);
+            emitAMD64MIOp(AMD64MIOp.MOV, OperandSize.QWORD, dst, (int) src, false);
         } else {
             AMD64Address high = new AMD64Address(dst.getBase(), dst.getIndex(), dst.getScale(), dst.getDisplacement() + 4, dst.getDisplacementAnnotation(), dst.instructionStartPosition);
             movl(dst, (int) (src & 0xFFFFFFFF));
@@ -1439,4 +1439,79 @@ public final void ptestU(AVXKind.AVXSize size, Register dst, AMD64Address src, R
     public boolean isAVX() {
         return supports(CPUFeature.AVX);
     }
+
+    public final void moveInt(Register dst, int imm) {
+        if (imm == 0) {
+            Register zeroValueRegister = getZeroValueRegister();
+            if (!Register.None.equals(zeroValueRegister)) {
+                movl(dst, zeroValueRegister);
+                return;
+            }
+        }
+        movl(dst, imm);
+    }
+
+    public final void moveInt(AMD64Address dst, int imm) {
+        if (imm == 0) {
+            Register zeroValueRegister = getZeroValueRegister();
+            if (!Register.None.equals(zeroValueRegister)) {
+                movl(dst, zeroValueRegister);
+                return;
+            }
+        }
+        movl(dst, imm);
+    }
+
+    public final void moveIntSignExtend(Register result, int imm) {
+        if (imm == 0) {
+            Register zeroValueRegister = getZeroValueRegister();
+            if (!Register.None.equals(zeroValueRegister)) {
+                movl(result, zeroValueRegister);
+                return;
+            }
+        }
+        movslq(result, imm);
+    }
+
+    private static AMD64MROp toMR(AMD64MIOp op) {
+        if (op == AMD64MIOp.MOVB) {
+            return AMD64MROp.MOVB;
+        } else if (op == AMD64MIOp.MOV) {
+            return AMD64MROp.MOV;
+        } else if (op == AMD64MIOp.TEST) {
+            return AMD64MROp.TEST;
+        }
+        return null;
+    }
+
+    public final void emitAMD64MIOp(AMD64MIOp opcode, OperandSize size, Register dst, int imm, boolean annotateImm) {
+        if (imm == 0) {
+            Register zeroValueRegister = getZeroValueRegister();
+            AMD64MROp mrOp = toMR(opcode);
+            if (!Register.None.equals(zeroValueRegister) && mrOp != null) {
+                mrOp.emit(this, size, dst, zeroValueRegister);
+                return;
+            }
+        }
+        opcode.emit(this, size, dst, imm, annotateImm);
+    }
+
+    public final void emitAMD64MIOp(AMD64MIOp opcode, OperandSize size, AMD64Address dst, int imm, boolean annotateImm) {
+        if (imm == 0) {
+            Register zeroValueRegister = getZeroValueRegister();
+            AMD64MROp mrOp = toMR(opcode);
+            if (!Register.None.equals(zeroValueRegister) && mrOp != null) {
+                mrOp.emit(this, size, dst, zeroValueRegister);
+                return;
+            }
+        }
+        opcode.emit(this, size, dst, imm, annotateImm);
+    }
+
+    /**
+     * Returns a register whose content is always zero.
+     */
+    public Register getZeroValueRegister() {
+        return Register.None;
+    }
 }

compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/AMD64HotSpotLIRGenerator.java

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012, 2023, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012, 2024, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -96,13 +96,15 @@
 import jdk.vm.ci.code.RegisterConfig;
 import jdk.vm.ci.code.RegisterValue;
 import jdk.vm.ci.meta.AllocatableValue;
+import jdk.vm.ci.meta.Constant;
 import jdk.vm.ci.meta.DeoptimizationAction;
 import jdk.vm.ci.meta.DeoptimizationReason;
 import jdk.vm.ci.meta.JavaConstant;
 import jdk.vm.ci.meta.JavaKind;
 import jdk.vm.ci.meta.PlatformKind;
 import jdk.vm.ci.meta.SpeculationLog;
 import jdk.vm.ci.meta.Value;
+import jdk.vm.ci.meta.ValueKind;
 
 /**
  * LIR generator specialized for AMD64 HotSpot.
@@ -655,4 +657,15 @@ public int getArrayLengthOffset() {
     public Register getHeapBaseRegister() {
         return getProviders().getRegisters().getHeapBaseRegister();
     }
+
+    @Override
+    public AllocatableValue emitLoadConstant(ValueKind<?> kind, Constant constant) {
+        if (((AMD64Kind) kind.getPlatformKind()).isInteger() && constant instanceof JavaConstant && constant.isDefaultForKind()) {
+            Register zeroValueRegister = getProviders().getRegisters().getZeroValueRegister(config);
+            if (!Register.None.equals(zeroValueRegister)) {
+                return zeroValueRegister.asValue(kind);
+            }
+        }
+        return super.emitLoadConstant(kind, constant);
+    }
 }

compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/AMD64HotSpotMacroAssembler.java

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2022, 2024, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -171,4 +171,9 @@ protected final int membarOffset() {
         }
         return offset;
     }
+
+    @Override
+    public Register getZeroValueRegister() {
+        return providers.getRegisters().getZeroValueRegister(config);
+    }
 }

compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/x/AMD64HotSpotXAtomicReadAndWriteOp.java

@@ -54,7 +54,7 @@ public AMD64HotSpotXAtomicReadAndWriteOp(Variable result, AMD64AddressValue load
     @Override
     public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
         AMD64Move.move(QWORD, crb, masm, result, newValue);
-        masm.xchgq(asRegister(result), loadAddress.toAddress());
+        masm.xchgq(asRegister(result), loadAddress.toAddress(masm));
         emitBarrier(crb, masm);
     }
 }

compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/x/AMD64HotSpotXBarrieredOp.java

@@ -65,7 +65,7 @@ protected AMD64HotSpotXBarrieredOp(LIRInstructionClass<? extends AMD64HotSpotXBa
      * Emit a barrier testing a specific register.
      */
     protected void emitBarrier(CompilationResultBuilder crb, AMD64MacroAssembler masm, Register register, Label success) {
-        AMD64HotSpotXBarrierSetLIRGenerator.emitBarrier(crb, masm, success, register, config, callTarget, loadAddress.toAddress(), this);
+        AMD64HotSpotXBarrierSetLIRGenerator.emitBarrier(crb, masm, success, register, config, callTarget, loadAddress.toAddress(masm), this);
     }
 
     /**

compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/x/AMD64HotSpotXCompareAndSwapOp.java

@@ -77,7 +77,7 @@ public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
         if (crb.target.isMP) {
             masm.lock();
         }
-        masm.cmpxchgq(newReg, loadAddress.toAddress());
+        masm.cmpxchgq(newReg, loadAddress.toAddress(masm));
         // if the cmpxchgq succeeds then we are done
         masm.jccb(AMD64Assembler.ConditionFlag.Zero, success);
         /*
@@ -91,7 +91,7 @@ public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
         if (crb.target.isMP) {
             masm.lock();
         }
-        masm.cmpxchgq(newReg, loadAddress.toAddress());
+        masm.cmpxchgq(newReg, loadAddress.toAddress(masm));
         masm.bind(barrierOk);
         masm.cmpq(asRegister(temp), asRegister(result));
         masm.bind(success);

compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/x/AMD64HotSpotXReadBarrierOp.java

@@ -55,7 +55,7 @@ public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
             crb.recordImplicitException(masm.position(), state);
         }
         final Register resultReg = asRegister(result);
-        MOV.emit(masm, AMD64BaseAssembler.OperandSize.QWORD, resultReg, loadAddress.toAddress());
+        MOV.emit(masm, AMD64BaseAssembler.OperandSize.QWORD, resultReg, loadAddress.toAddress(masm));
         emitBarrier(crb, masm);
     }
 }

compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/x/AMD64HotSpotXVectorReadBarrierOp.java

@@ -74,9 +74,9 @@ public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
             crb.recordImplicitException(masm.position(), state);
         }
         Register resultReg = asRegister(result);
-        op.emit(masm, size, resultReg, loadAddress.toAddress());
+        op.emit(masm, size, resultReg, loadAddress.toAddress(masm));
 
-        AMD64Address address = loadAddress.toAddress();
+        AMD64Address address = loadAddress.toAddress(masm);
 
         final Label entryPoint = new Label();
         final Label continuation = new Label();
@@ -119,7 +119,7 @@ public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
             masm.movslq(cArg1, count);
             AMD64Call.directCall(crb, masm, callTarget, null, false, null);
             masm.movq(resultReg, cArg0);
-            op.emit(masm, size, resultReg, loadAddress.toAddress());
+            op.emit(masm, size, resultReg, loadAddress.toAddress(masm));
 
             // Return to inline code
             masm.jmp(continuation);

compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/hotspot/amd64/z/AMD64HotSpotZAtomicReadAndWriteOp.java

@@ -56,7 +56,7 @@ public AMD64HotSpotZAtomicReadAndWriteOp(Variable result, AMD64AddressValue load
     public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
         emitPreWriteBarrier(crb, masm, asRegister(result), null);
         zColor(crb, masm, asRegister(result), asRegister(newValue));
-        masm.xchgq(asRegister(result), storeAddress.toAddress());
+        masm.xchgq(asRegister(result), storeAddress.toAddress(masm));
         Register ref = asRegister(result);
         AMD64HotSpotZBarrierSetLIRGenerator.zUncolor(crb, masm, ref);
     }