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shqkingshqking
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Add "assert" for immI cases
Define helper assert_not_var_shift() and use it for immI cases. Besides, update the copyright year to 2022.
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2 files changed

+30
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‎src/hotspot/cpu/arm/arm.ad‎

Lines changed: 29 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
//
2-
// Copyright (c) 2008, 2021, Oracle and/or its affiliates. All rights reserved.
2+
// Copyright (c) 2008, 2022, Oracle and/or its affiliates. All rights reserved.
33
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
//
55
// This code is free software; you can redistribute it and/or modify it
@@ -123,9 +123,18 @@ public:
123123
};
124124
};
125125

126+
// Assert that the given node is not a var shift.
127+
bool assert_not_var_shift(const Node *n);
126128
%}
127129

128130
source %{
131+
132+
// Assert that the given node is not a var shift.
133+
bool assert_not_var_shift(const Node *n) {
134+
assert(!n->as_ShiftV()->is_var_shift(), "illegal var shift");
135+
return true;
136+
}
137+
129138
#define __ _masm.
130139

131140
static FloatRegister reg_to_FloatRegister_object(int register_encoding);
@@ -10792,7 +10801,7 @@ instruct vsl16B_reg(vecX dst, vecX src, vecX shift) %{
1079210801
%}
1079310802

1079410803
instruct vsl8B_immI(vecD dst, vecD src, immI shift) %{
10795-
predicate(n->as_Vector()->length() == 8 && !n->as_ShiftV()->is_var_shift());
10804+
predicate(n->as_Vector()->length() == 8 && assert_not_var_shift(n));
1079610805
match(Set dst (LShiftVB src (LShiftCntV shift)));
1079710806
size(4);
1079810807
ins_cost(DEFAULT_COST); // FIXME
@@ -10808,7 +10817,7 @@ instruct vsl8B_immI(vecD dst, vecD src, immI shift) %{
1080810817
%}
1080910818

1081010819
instruct vsl16B_immI(vecX dst, vecX src, immI shift) %{
10811-
predicate(n->as_Vector()->length() == 16 && !n->as_ShiftV()->is_var_shift());
10820+
predicate(n->as_Vector()->length() == 16 && assert_not_var_shift(n));
1081210821
match(Set dst (LShiftVB src (LShiftCntV shift)));
1081310822
size(4);
1081410823
ins_cost(DEFAULT_COST); // FIXME
@@ -10845,7 +10854,7 @@ instruct vsl8S_reg(vecX dst, vecX src, vecX shift) %{
1084510854
%}
1084610855

1084710856
instruct vsl4S_immI(vecD dst, vecD src, immI shift) %{
10848-
predicate(n->as_Vector()->length() == 4 && !n->as_ShiftV()->is_var_shift());
10857+
predicate(n->as_Vector()->length() == 4 && assert_not_var_shift(n));
1084910858
match(Set dst (LShiftVS src (LShiftCntV shift)));
1085010859
size(4);
1085110860
ins_cost(DEFAULT_COST); // FIXME
@@ -10861,7 +10870,7 @@ instruct vsl4S_immI(vecD dst, vecD src, immI shift) %{
1086110870
%}
1086210871

1086310872
instruct vsl8S_immI(vecX dst, vecX src, immI shift) %{
10864-
predicate(n->as_Vector()->length() == 8 && !n->as_ShiftV()->is_var_shift());
10873+
predicate(n->as_Vector()->length() == 8 && assert_not_var_shift(n));
1086510874
match(Set dst (LShiftVS src shift));
1086610875
size(4);
1086710876
ins_cost(DEFAULT_COST); // FIXME
@@ -10900,7 +10909,7 @@ instruct vsl4I_reg(vecX dst, vecX src, vecX shift) %{
1090010909
instruct vsl2I_immI(vecD dst, vecD src, immI shift) %{
1090110910
predicate(n->as_Vector()->length() == 2 &&
1090210911
VM_Version::has_simd() &&
10903-
!n->as_ShiftV()->is_var_shift());
10912+
assert_not_var_shift(n));
1090410913
match(Set dst (LShiftVI src (LShiftCntV shift)));
1090510914
size(4);
1090610915
ins_cost(DEFAULT_COST); // FIXME
@@ -10918,7 +10927,7 @@ instruct vsl2I_immI(vecD dst, vecD src, immI shift) %{
1091810927
instruct vsl4I_immI(vecX dst, vecX src, immI shift) %{
1091910928
predicate(n->as_Vector()->length() == 4 &&
1092010929
VM_Version::has_simd() &&
10921-
!n->as_ShiftV()->is_var_shift());
10930+
assert_not_var_shift(n));
1092210931
match(Set dst (LShiftVI src (LShiftCntV shift)));
1092310932
size(4);
1092410933
ins_cost(DEFAULT_COST); // FIXME
@@ -10945,7 +10954,7 @@ instruct vsl2L_reg(vecX dst, vecX src, vecX shift) %{
1094510954
%}
1094610955

1094710956
instruct vsl2L_immI(vecX dst, vecX src, immI shift) %{
10948-
predicate(n->as_Vector()->length() == 2 && !n->as_ShiftV()->is_var_shift());
10957+
predicate(n->as_Vector()->length() == 2 && assert_not_var_shift(n));
1094910958
match(Set dst (LShiftVL src (LShiftCntV shift)));
1095010959
size(4);
1095110960
ins_cost(DEFAULT_COST); // FIXME
@@ -11038,7 +11047,7 @@ instruct vsrl8S_reg_var(vecX dst, vecX src, vecX shift, vecX tmp) %{
1103811047
%}
1103911048

1104011049
instruct vsrl4S_immI(vecD dst, vecD src, immI shift) %{
11041-
predicate(n->as_Vector()->length() == 4 && !n->as_ShiftV()->is_var_shift());
11050+
predicate(n->as_Vector()->length() == 4 && assert_not_var_shift(n));
1104211051
match(Set dst (URShiftVS src (RShiftCntV shift)));
1104311052
size(4);
1104411053
ins_cost(DEFAULT_COST); // FIXME
@@ -11054,7 +11063,7 @@ instruct vsrl4S_immI(vecD dst, vecD src, immI shift) %{
1105411063
%}
1105511064

1105611065
instruct vsrl8S_immI(vecX dst, vecX src, immI shift) %{
11057-
predicate(n->as_Vector()->length() == 8 && !n->as_ShiftV()->is_var_shift());
11066+
predicate(n->as_Vector()->length() == 8 && assert_not_var_shift(n));
1105811067
match(Set dst (URShiftVS src (RShiftCntV shift)));
1105911068
size(4);
1106011069
ins_cost(DEFAULT_COST); // FIXME
@@ -11141,7 +11150,7 @@ instruct vsrl4I_reg_var(vecX dst, vecX src, vecX shift, vecX tmp) %{
1114111150
instruct vsrl2I_immI(vecD dst, vecD src, immI shift) %{
1114211151
predicate(n->as_Vector()->length() == 2 &&
1114311152
VM_Version::has_simd() &&
11144-
!n->as_ShiftV()->is_var_shift());
11153+
assert_not_var_shift(n));
1114511154
match(Set dst (URShiftVI src (RShiftCntV shift)));
1114611155
size(4);
1114711156
ins_cost(DEFAULT_COST); // FIXME
@@ -11159,7 +11168,7 @@ instruct vsrl2I_immI(vecD dst, vecD src, immI shift) %{
1115911168
instruct vsrl4I_immI(vecX dst, vecX src, immI shift) %{
1116011169
predicate(n->as_Vector()->length() == 4 &&
1116111170
VM_Version::has_simd() &&
11162-
!n->as_ShiftV()->is_var_shift());
11171+
assert_not_var_shift(n));
1116311172
match(Set dst (URShiftVI src (RShiftCntV shift)));
1116411173
size(4);
1116511174
ins_cost(DEFAULT_COST); // FIXME
@@ -11206,7 +11215,7 @@ instruct vsrl2L_reg_var(vecX dst, vecX src, vecX shift, vecX tmp) %{
1120611215
%}
1120711216

1120811217
instruct vsrl2L_immI(vecX dst, vecX src, immI shift) %{
11209-
predicate(n->as_Vector()->length() == 2 && !n->as_ShiftV()->is_var_shift());
11218+
predicate(n->as_Vector()->length() == 2 && assert_not_var_shift(n));
1121011219
match(Set dst (URShiftVL src (RShiftCntV shift)));
1121111220
size(4);
1121211221
ins_cost(DEFAULT_COST); // FIXME
@@ -11401,7 +11410,7 @@ instruct vsra16B_reg_var(vecX dst, vecX src, vecX shift, vecX tmp) %{
1140111410
%}
1140211411

1140311412
instruct vsra8B_immI(vecD dst, vecD src, immI shift) %{
11404-
predicate(n->as_Vector()->length() == 8 && !n->as_ShiftV()->is_var_shift());
11413+
predicate(n->as_Vector()->length() == 8 && assert_not_var_shift(n));
1140511414
match(Set dst (RShiftVB src (RShiftCntV shift)));
1140611415
size(4);
1140711416
ins_cost(DEFAULT_COST); // FIXME
@@ -11417,7 +11426,7 @@ instruct vsra8B_immI(vecD dst, vecD src, immI shift) %{
1141711426
%}
1141811427

1141911428
instruct vsra16B_immI(vecX dst, vecX src, immI shift) %{
11420-
predicate(n->as_Vector()->length() == 16 && !n->as_ShiftV()->is_var_shift());
11429+
predicate(n->as_Vector()->length() == 16 && assert_not_var_shift(n));
1142111430
match(Set dst (RShiftVB src (RShiftCntV shift)));
1142211431
size(4);
1142311432
ins_cost(DEFAULT_COST); // FIXME
@@ -11494,7 +11503,7 @@ instruct vsra8S_reg_var(vecX dst, vecX src, vecX shift, vecX tmp) %{
1149411503
%}
1149511504

1149611505
instruct vsra4S_immI(vecD dst, vecD src, immI shift) %{
11497-
predicate(n->as_Vector()->length() == 4 && !n->as_ShiftV()->is_var_shift());
11506+
predicate(n->as_Vector()->length() == 4 && assert_not_var_shift(n));
1149811507
match(Set dst (RShiftVS src (RShiftCntV shift)));
1149911508
size(4);
1150011509
ins_cost(DEFAULT_COST); // FIXME
@@ -11510,7 +11519,7 @@ instruct vsra4S_immI(vecD dst, vecD src, immI shift) %{
1151011519
%}
1151111520

1151211521
instruct vsra8S_immI(vecX dst, vecX src, immI shift) %{
11513-
predicate(n->as_Vector()->length() == 8 && !n->as_ShiftV()->is_var_shift());
11522+
predicate(n->as_Vector()->length() == 8 && assert_not_var_shift(n));
1151411523
match(Set dst (RShiftVS src (RShiftCntV shift)));
1151511524
size(4);
1151611525
ins_cost(DEFAULT_COST); // FIXME
@@ -11587,7 +11596,7 @@ instruct vsra4I_reg_var(vecX dst, vecX src, vecX shift, vecX tmp) %{
1158711596
%}
1158811597

1158911598
instruct vsra2I_immI(vecD dst, vecD src, immI shift) %{
11590-
predicate(n->as_Vector()->length() == 2 && !n->as_ShiftV()->is_var_shift());
11599+
predicate(n->as_Vector()->length() == 2 && assert_not_var_shift(n));
1159111600
match(Set dst (RShiftVI src (RShiftCntV shift)));
1159211601
size(4);
1159311602
ins_cost(DEFAULT_COST); // FIXME
@@ -11603,7 +11612,7 @@ instruct vsra2I_immI(vecD dst, vecD src, immI shift) %{
1160311612
%}
1160411613

1160511614
instruct vsra4I_immI(vecX dst, vecX src, immI shift) %{
11606-
predicate(n->as_Vector()->length() == 4 && !n->as_ShiftV()->is_var_shift());
11615+
predicate(n->as_Vector()->length() == 4 && assert_not_var_shift(n));
1160711616
match(Set dst (RShiftVI src (RShiftCntV shift)));
1160811617
size(4);
1160911618
ins_cost(DEFAULT_COST); // FIXME
@@ -11650,7 +11659,7 @@ instruct vsra2L_reg_var(vecX dst, vecX src, vecX shift, vecX tmp) %{
1165011659
%}
1165111660

1165211661
instruct vsra2L_immI(vecX dst, vecX src, immI shift) %{
11653-
predicate(n->as_Vector()->length() == 2 && !n->as_ShiftV()->is_var_shift());
11662+
predicate(n->as_Vector()->length() == 2 && assert_not_var_shift(n));
1165411663
match(Set dst (RShiftVL src (RShiftCntV shift)));
1165511664
size(4);
1165611665
ins_cost(DEFAULT_COST); // FIXME

‎src/hotspot/share/opto/vectornode.hpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2007, 2021, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 2007, 2022, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it

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