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lewurmlewurm
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AArch64: Avoid usage of r18
1 parent ff65591 commit cd6b2a6

13 files changed

+1370
-1248
lines changed

‎src/hotspot/cpu/aarch64/aarch64-asmtest.py‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,8 @@ class Register(Operand):
1313

1414
def generate(self):
1515
self.number = random.randint(0, 30)
16+
if self.number == 18:
17+
self.number = 17
1618
return self
1719

1820
def astr(self, prefix):
@@ -37,6 +39,8 @@ class GeneralRegisterOrZr(Register):
3739

3840
def generate(self):
3941
self.number = random.randint(0, 31)
42+
if self.number == 18:
43+
self.number = 16
4044
return self
4145

4246
def astr(self, prefix = ""):
@@ -54,6 +58,8 @@ def __str__(self):
5458
class GeneralRegisterOrSp(Register):
5559
def generate(self):
5660
self.number = random.randint(0, 31)
61+
if self.number == 18:
62+
self.number = 15
5763
return self
5864

5965
def astr(self, prefix = ""):

‎src/hotspot/cpu/aarch64/aarch64.ad‎

Lines changed: 18 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -110,8 +110,8 @@ reg_def R16 ( SOC, SOC, Op_RegI, 16, r16->as_VMReg() );
110110
reg_def R16_H ( SOC, SOC, Op_RegI, 16, r16->as_VMReg()->next());
111111
reg_def R17 ( SOC, SOC, Op_RegI, 17, r17->as_VMReg() );
112112
reg_def R17_H ( SOC, SOC, Op_RegI, 17, r17->as_VMReg()->next());
113-
reg_def R18 ( SOC, SOC, Op_RegI, 18, r18->as_VMReg() );
114-
reg_def R18_H ( SOC, SOC, Op_RegI, 18, r18->as_VMReg()->next());
113+
reg_def R18 ( SOC, SOC, Op_RegI, 18, r18_tls->as_VMReg() );
114+
reg_def R18_H ( SOC, SOC, Op_RegI, 18, r18_tls->as_VMReg()->next());
115115
reg_def R19 ( SOC, SOE, Op_RegI, 19, r19->as_VMReg() );
116116
reg_def R19_H ( SOC, SOE, Op_RegI, 19, r19->as_VMReg()->next());
117117
reg_def R20 ( SOC, SOE, Op_RegI, 20, r20->as_VMReg() ); // caller esp
@@ -352,7 +352,6 @@ alloc_class chunk0(
352352
R15, R15_H,
353353
R16, R16_H,
354354
R17, R17_H,
355-
R18, R18_H,
356355

357356
// arg registers
358357
R0, R0_H,
@@ -375,7 +374,7 @@ alloc_class chunk0(
375374
R26, R26_H,
376375

377376
// non-allocatable registers
378-
377+
R18, R18_H, // platform
379378
R27, R27_H, // heapbase
380379
R28, R28_H, // thread
381380
R29, R29_H, // fp
@@ -533,7 +532,10 @@ reg_class no_special_reg32_no_fp(
533532
R15,
534533
R16,
535534
R17,
535+
#ifndef R18_RESERVED
536+
// See comment in register_aarch64.hpp
536537
R18,
538+
#endif
537539
R19,
538540
R20,
539541
R21,
@@ -566,7 +568,10 @@ reg_class no_special_reg32_with_fp(
566568
R15,
567569
R16,
568570
R17,
571+
#ifndef R18_RESERVED
572+
// See comment in register_aarch64.hpp
569573
R18,
574+
#endif
570575
R19,
571576
R20,
572577
R21,
@@ -602,7 +607,10 @@ reg_class no_special_reg_no_fp(
602607
R15, R15_H,
603608
R16, R16_H,
604609
R17, R17_H,
610+
#ifndef R18_RESERVED
611+
// See comment in register_aarch64.hpp
605612
R18, R18_H,
613+
#endif
606614
R19, R19_H,
607615
R20, R20_H,
608616
R21, R21_H,
@@ -635,7 +643,10 @@ reg_class no_special_reg_with_fp(
635643
R15, R15_H,
636644
R16, R16_H,
637645
R17, R17_H,
646+
#ifndef R18_RESERVED
647+
// See comment in register_aarch64.hpp
638648
R18, R18_H,
649+
#endif
639650
R19, R19_H,
640651
R20, R20_H,
641652
R21, R21_H,
@@ -775,7 +786,10 @@ reg_class no_special_ptr_reg(
775786
R15, R15_H,
776787
R16, R16_H,
777788
R17, R17_H,
789+
#ifndef R18_RESERVED
790+
// See comment in register_aarch64.hpp
778791
R18, R18_H,
792+
#endif
779793
R19, R19_H,
780794
R20, R20_H,
781795
R21, R21_H,

‎src/hotspot/cpu/aarch64/assembler_aarch64.cpp‎

Lines changed: 1181 additions & 1181 deletions
Large diffs are not rendered by default.

‎src/hotspot/cpu/aarch64/c1_Defs_aarch64.hpp‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -44,13 +44,13 @@ enum {
4444
pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers, // number of registers used during code emission
4545
pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers, // number of registers used during code emission
4646

47-
pd_nof_caller_save_cpu_regs_frame_map = 19 - 2, // number of registers killed by calls
47+
pd_nof_caller_save_cpu_regs_frame_map = 19 - 2 /* rscratch1 and rscratch2 */ R18_RESERVED_ONLY(- 1), // number of registers killed by calls
4848
pd_nof_caller_save_fpu_regs_frame_map = 32, // number of registers killed by calls
4949

50-
pd_first_callee_saved_reg = 19 - 2,
51-
pd_last_callee_saved_reg = 26 - 2,
50+
pd_first_callee_saved_reg = 19 - 2 /* rscratch1 and rscratch2 */ R18_RESERVED_ONLY(- 1),
51+
pd_last_callee_saved_reg = 26 - 2 /* rscratch1 and rscratch2 */ R18_RESERVED_ONLY(- 1),
5252

53-
pd_last_allocatable_cpu_reg = 16,
53+
pd_last_allocatable_cpu_reg = 16 R18_RESERVED_ONLY(- 1),
5454

5555
pd_nof_cpu_regs_reg_alloc
5656
= pd_last_allocatable_cpu_reg + 1, // number of registers that are visible to register allocator
@@ -60,9 +60,9 @@ enum {
6060
pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan
6161
pd_nof_xmm_regs_linearscan = 0, // like sparc we don't have any of these
6262
pd_first_cpu_reg = 0,
63-
pd_last_cpu_reg = 16,
63+
pd_last_cpu_reg = 16 R18_RESERVED_ONLY(- 1),
6464
pd_first_byte_reg = 0,
65-
pd_last_byte_reg = 16,
65+
pd_last_byte_reg = 16 R18_RESERVED_ONLY(- 1),
6666
pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
6767
pd_last_fpu_reg = pd_first_fpu_reg + 31,
6868

‎src/hotspot/cpu/aarch64/c1_FrameMap_aarch64.cpp‎

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -181,7 +181,10 @@ void FrameMap::initialize() {
181181
map_register(i, r15); r15_opr = LIR_OprFact::single_cpu(i); i++;
182182
map_register(i, r16); r16_opr = LIR_OprFact::single_cpu(i); i++;
183183
map_register(i, r17); r17_opr = LIR_OprFact::single_cpu(i); i++;
184-
map_register(i, r18); r18_opr = LIR_OprFact::single_cpu(i); i++;
184+
#ifndef R18_RESERVED
185+
// See comment in register_aarch64.hpp
186+
map_register(i, r18_tls); r18_opr = LIR_OprFact::single_cpu(i); i++;
187+
#endif
185188
map_register(i, r19); r19_opr = LIR_OprFact::single_cpu(i); i++;
186189
map_register(i, r20); r20_opr = LIR_OprFact::single_cpu(i); i++;
187190
map_register(i, r21); r21_opr = LIR_OprFact::single_cpu(i); i++;
@@ -199,6 +202,11 @@ void FrameMap::initialize() {
199202
map_register(i, r8); r8_opr = LIR_OprFact::single_cpu(i); i++; // rscratch1
200203
map_register(i, r9); r9_opr = LIR_OprFact::single_cpu(i); i++; // rscratch2
201204

205+
#ifdef R18_RESERVED
206+
// See comment in register_aarch64.hpp
207+
map_register(i, r18_tls); r18_opr = LIR_OprFact::single_cpu(i); i++;
208+
#endif
209+
202210
rscratch1_opr = r8_opr;
203211
rscratch2_opr = r9_opr;
204212
rscratch1_long_opr = LIR_OprFact::double_cpu(r8_opr->cpu_regnr(), r8_opr->cpu_regnr());
@@ -227,7 +235,10 @@ void FrameMap::initialize() {
227235
_caller_save_cpu_regs[13] = r15_opr;
228236
_caller_save_cpu_regs[14] = r16_opr;
229237
_caller_save_cpu_regs[15] = r17_opr;
238+
#ifndef R18_RESERVED
239+
// See comment in register_aarch64.hpp
230240
_caller_save_cpu_regs[16] = r18_opr;
241+
#endif
231242

232243
for (int i = 0; i < 8; i++) {
233244
_caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
@@ -253,7 +264,7 @@ void FrameMap::initialize() {
253264
r15_oop_opr = as_oop_opr(r15);
254265
r16_oop_opr = as_oop_opr(r16);
255266
r17_oop_opr = as_oop_opr(r17);
256-
r18_oop_opr = as_oop_opr(r18);
267+
r18_oop_opr = as_oop_opr(r18_tls);
257268
r19_oop_opr = as_oop_opr(r19);
258269
r20_oop_opr = as_oop_opr(r20);
259270
r21_oop_opr = as_oop_opr(r21);

‎src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,4 +53,13 @@ const bool CCallingConventionRequiresIntsAsLongs = false;
5353

5454
#define THREAD_LOCAL_POLL
5555

56+
#if defined(_WIN64)
57+
#define R18_RESERVED
58+
#define R18_RESERVED_ONLY(code) code
59+
#define NOT_R18_RESERVED(code)
60+
#else
61+
#define R18_RESERVED_ONLY(code)
62+
#define NOT_R18_RESERVED(code) code
63+
#endif
64+
5665
#endif // CPU_AARCH64_VM_GLOBALDEFINITIONS_AARCH64_HPP

‎src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2544,9 +2544,17 @@ void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
25442544
}
25452545
}
25462546

2547+
RegSet MacroAssembler::call_clobbered_registers() {
2548+
RegSet regs = RegSet::range(r0, r17) - RegSet::of(rscratch1, rscratch2);
2549+
#ifndef R18_RESERVED
2550+
regs += r18_tls;
2551+
#endif
2552+
return regs;
2553+
}
2554+
25472555
void MacroAssembler::push_call_clobbered_registers() {
25482556
int step = 4 * wordSize;
2549-
push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp);
2557+
push(call_clobbered_registers(), sp);
25502558
sub(sp, sp, step);
25512559
mov(rscratch1, -step);
25522560
// Push v0-v7, v16-v31.
@@ -2566,7 +2574,7 @@ void MacroAssembler::pop_call_clobbered_registers() {
25662574
as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize)));
25672575
}
25682576

2569-
pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp);
2577+
pop(call_clobbered_registers() - RegSet::of(rscratch1, rscratch2), sp);
25702578
}
25712579

25722580
void MacroAssembler::push_CPU_state(bool save_vectors) {

‎src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -460,6 +460,8 @@ class MacroAssembler: public Assembler {
460460
void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
461461
void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
462462

463+
static RegSet call_clobbered_registers();
464+
463465
// Push and pop everything that might be clobbered by a native
464466
// runtime call except rscratch1 and rscratch2. (They are always
465467
// scratch, so we don't have to protect them.) Only save the lower

‎src/hotspot/cpu/aarch64/macroAssembler_aarch64_trig.cpp‎

Lines changed: 13 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -689,7 +689,7 @@ void MacroAssembler::generate__kernel_rem_pio2(address two_over_pi, address pio2
689689
RECOMP_FOR1_CHECK;
690690
Register tmp2 = r1, n = r2, jv = r4, tmp5 = r5, jx = r6,
691691
tmp3 = r7, iqBase = r10, ih = r11, tmp4 = r12, tmp1 = r13,
692-
jz = r14, j = r15, twoOverPiBase = r16, i = r17, qBase = r18;
692+
jz = r14, j = r15, twoOverPiBase = r16, i = r17, qBase = r19;
693693
// jp = jk == init_jk[prec] = init_jk[2] == {2,3,4,6}[2] == 4
694694
// jx = nx - 1
695695
lea(twoOverPiBase, ExternalAddress(two_over_pi));
@@ -1421,6 +1421,12 @@ void MacroAssembler::generate_dsin_dcos(bool isCos, address npio2_hw,
14211421
Label DONE, ARG_REDUCTION, TINY_X, RETURN_SIN, EARLY_CASE;
14221422
Register X = r0, absX = r1, n = r2, ix = r3;
14231423
FloatRegister y0 = v4, y1 = v5;
1424+
1425+
enter();
1426+
// r19 is used in TemplateInterpreterGenerator::generate_math_entry
1427+
RegSet saved_regs = RegSet::of(r19);
1428+
push (saved_regs, sp);
1429+
14241430
block_comment("check |x| ~< pi/4, NaN, Inf and |x| < 2**-27 cases"); {
14251431
fmovd(X, v0);
14261432
mov(rscratch2, 0x3e400000);
@@ -1438,14 +1444,14 @@ void MacroAssembler::generate_dsin_dcos(bool isCos, address npio2_hw,
14381444
// Set last bit unconditionally to make it NaN
14391445
orr(r10, r10, 1);
14401446
fmovd(v0, r10);
1441-
ret(lr);
1447+
b(DONE);
14421448
}
14431449
block_comment("kernel_sin/kernel_cos: if(ix<0x3e400000) {<fast return>}"); {
14441450
bind(TINY_X);
14451451
if (isCos) {
14461452
fmovd(v0, 1.0);
14471453
}
1448-
ret(lr);
1454+
b(DONE);
14491455
}
14501456
bind(ARG_REDUCTION); /* argument reduction needed */
14511457
block_comment("n = __ieee754_rem_pio2(x,y);"); {
@@ -1465,7 +1471,7 @@ void MacroAssembler::generate_dsin_dcos(bool isCos, address npio2_hw,
14651471
tbz(n, 1, DONE);
14661472
}
14671473
fnegd(v0, v0);
1468-
ret(lr);
1474+
b(DONE);
14691475
bind(RETURN_SIN);
14701476
generate_kernel_sin(y0, true, dsin_coef);
14711477
if (isCos) {
@@ -1474,7 +1480,7 @@ void MacroAssembler::generate_dsin_dcos(bool isCos, address npio2_hw,
14741480
tbz(n, 1, DONE);
14751481
}
14761482
fnegd(v0, v0);
1477-
ret(lr);
1483+
b(DONE);
14781484
}
14791485
bind(EARLY_CASE);
14801486
eor(y1, T8B, y1, y1);
@@ -1484,5 +1490,7 @@ void MacroAssembler::generate_dsin_dcos(bool isCos, address npio2_hw,
14841490
generate_kernel_sin(v0, false, dsin_coef);
14851491
}
14861492
bind(DONE);
1493+
pop(saved_regs, sp);
1494+
leave();
14871495
ret(lr);
14881496
}

‎src/hotspot/cpu/aarch64/register_aarch64.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ const char* RegisterImpl::name() const {
3838
"c_rarg0", "c_rarg1", "c_rarg2", "c_rarg3", "c_rarg4", "c_rarg5", "c_rarg6", "c_rarg7",
3939
"rscratch1", "rscratch2",
4040
"r10", "r11", "r12", "r13", "r14", "r15", "r16",
41-
"r17", "r18", "r19",
41+
"r17", "r18_tls", "r19",
4242
"resp", "rdispatch", "rbcp", "r23", "rlocals", "rmonitors", "rcpool", "rheapbase",
4343
"rthread", "rfp", "lr", "sp"
4444
};

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