Skip to content

Commit c55192d

Browse files
committed
Backport ec9bee6
1 parent c816276 commit c55192d

File tree

3 files changed

+131
-156
lines changed

3 files changed

+131
-156
lines changed

src/hotspot/cpu/aarch64/vm_version_aarch64.cpp

Lines changed: 27 additions & 135 deletions
Original file line numberDiff line numberDiff line change
@@ -24,100 +24,35 @@
2424
*/
2525

2626
#include "precompiled.hpp"
27-
#include "asm/macroAssembler.hpp"
28-
#include "asm/macroAssembler.inline.hpp"
29-
#include "memory/resourceArea.hpp"
27+
#include "runtime/arguments.hpp"
28+
#include "runtime/globals_extension.hpp"
3029
#include "runtime/java.hpp"
31-
#include "runtime/stubCodeGenerator.hpp"
30+
#include "runtime/os.hpp"
3231
#include "runtime/vm_version.hpp"
32+
#include "utilities/formatBuffer.hpp"
3333
#include "utilities/macros.hpp"
3434

3535
#include OS_HEADER_INLINE(os)
3636

37-
#include <sys/auxv.h>
38-
#include <asm/hwcap.h>
39-
40-
#ifndef HWCAP_AES
41-
#define HWCAP_AES (1<<3)
42-
#endif
43-
44-
#ifndef HWCAP_PMULL
45-
#define HWCAP_PMULL (1<<4)
46-
#endif
47-
48-
#ifndef HWCAP_SHA1
49-
#define HWCAP_SHA1 (1<<5)
50-
#endif
51-
52-
#ifndef HWCAP_SHA2
53-
#define HWCAP_SHA2 (1<<6)
54-
#endif
55-
56-
#ifndef HWCAP_CRC32
57-
#define HWCAP_CRC32 (1<<7)
58-
#endif
59-
60-
#ifndef HWCAP_ATOMICS
61-
#define HWCAP_ATOMICS (1<<8)
62-
#endif
63-
6437
int VM_Version::_cpu;
6538
int VM_Version::_model;
6639
int VM_Version::_model2;
6740
int VM_Version::_variant;
6841
int VM_Version::_revision;
6942
int VM_Version::_stepping;
70-
VM_Version::PsrInfo VM_Version::_psr_info = { 0, };
71-
72-
static BufferBlob* stub_blob;
73-
static const int stub_size = 550;
74-
75-
extern "C" {
76-
typedef void (*getPsrInfo_stub_t)(void*);
77-
}
78-
static getPsrInfo_stub_t getPsrInfo_stub = NULL;
79-
80-
81-
class VM_Version_StubGenerator: public StubCodeGenerator {
82-
public:
83-
84-
VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
85-
86-
address generate_getPsrInfo() {
87-
StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
88-
# define __ _masm->
89-
address start = __ pc();
90-
91-
// void getPsrInfo(VM_Version::PsrInfo* psr_info);
92-
93-
address entry = __ pc();
9443

95-
__ enter();
44+
int VM_Version::_zva_length;
45+
int VM_Version::_dcache_line_size;
46+
int VM_Version::_icache_line_size;
9647

97-
__ get_dczid_el0(rscratch1);
98-
__ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::dczid_el0_offset())));
99-
100-
__ get_ctr_el0(rscratch1);
101-
__ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::ctr_el0_offset())));
102-
103-
__ leave();
104-
__ ret(lr);
105-
106-
# undef __
107-
108-
return start;
109-
}
110-
};
111-
112-
113-
void VM_Version::get_processor_features() {
48+
void VM_Version::initialize() {
11449
_supports_cx8 = true;
11550
_supports_atomic_getset4 = true;
11651
_supports_atomic_getadd4 = true;
11752
_supports_atomic_getset8 = true;
11853
_supports_atomic_getadd8 = true;
11954

120-
getPsrInfo_stub(&_psr_info);
55+
get_os_cpu_info();
12156

12257
int dcache_line = VM_Version::dcache_line_size();
12358

@@ -163,34 +98,6 @@ void VM_Version::get_processor_features() {
16398
ContendedPaddingWidth = dcache_line;
16499
}
165100

166-
uint64_t auxv = getauxval(AT_HWCAP);
167-
168-
char buf[512];
169-
170-
_features = auxv;
171-
172-
int cpu_lines = 0;
173-
if (FILE *f = fopen("/proc/cpuinfo", "r")) {
174-
char buf[128], *p;
175-
while (fgets(buf, sizeof (buf), f) != NULL) {
176-
if ((p = strchr(buf, ':')) != NULL) {
177-
long v = strtol(p+1, NULL, 0);
178-
if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
179-
_cpu = v;
180-
cpu_lines++;
181-
} else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
182-
_variant = v;
183-
} else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
184-
if (_model != v) _model2 = _model;
185-
_model = v;
186-
} else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
187-
_revision = v;
188-
}
189-
}
190-
}
191-
fclose(f);
192-
}
193-
194101
// Enable vendor specific features
195102

196103
// ThunderX
@@ -256,27 +163,28 @@ void VM_Version::get_processor_features() {
256163
}
257164

258165
if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH;
259-
// If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)
166+
// If an olde style /proc/cpuinfo (cores == 1) then if _model is an A57 (0xd07)
260167
// we assume the worst and assume we could be on a big little system and have
261168
// undisclosed A53 cores which we could be swapped to at any stage
262-
if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC;
169+
if (_cpu == CPU_ARM && os::processor_count() == 1 && _model == 0xd07) _features |= CPU_A53MAC;
263170

171+
char buf[512];
264172
sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
265173
if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
266-
if (auxv & HWCAP_ASIMD) strcat(buf, ", simd");
267-
if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
268-
if (auxv & HWCAP_AES) strcat(buf, ", aes");
269-
if (auxv & HWCAP_SHA1) strcat(buf, ", sha1");
270-
if (auxv & HWCAP_SHA2) strcat(buf, ", sha256");
271-
if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse");
174+
if (_features & CPU_ASIMD) strcat(buf, ", simd");
175+
if (_features & CPU_CRC32) strcat(buf, ", crc");
176+
if (_features & CPU_AES) strcat(buf, ", aes");
177+
if (_features & CPU_SHA1) strcat(buf, ", sha1");
178+
if (_features & CPU_SHA2) strcat(buf, ", sha256");
179+
if (_features & CPU_LSE) strcat(buf, ", lse");
272180

273181
_features_string = os::strdup(buf);
274182

275183
if (FLAG_IS_DEFAULT(UseCRC32)) {
276-
UseCRC32 = (auxv & HWCAP_CRC32) != 0;
184+
UseCRC32 = (_features & CPU_CRC32) != 0;
277185
}
278186

279-
if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) {
187+
if (UseCRC32 && (_features & CPU_CRC32) == 0) {
280188
warning("UseCRC32 specified, but not supported on this CPU");
281189
FLAG_SET_DEFAULT(UseCRC32, false);
282190
}
@@ -290,7 +198,7 @@ void VM_Version::get_processor_features() {
290198
FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
291199
}
292200

293-
if (auxv & HWCAP_ATOMICS) {
201+
if (_features & CPU_LSE) {
294202
if (FLAG_IS_DEFAULT(UseLSE))
295203
FLAG_SET_DEFAULT(UseLSE, true);
296204
} else {
@@ -300,7 +208,7 @@ void VM_Version::get_processor_features() {
300208
}
301209
}
302210

303-
if (auxv & HWCAP_AES) {
211+
if (_features & CPU_AES) {
304212
UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
305213
UseAESIntrinsics =
306214
UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
@@ -328,7 +236,7 @@ void VM_Version::get_processor_features() {
328236
UseCRC32Intrinsics = true;
329237
}
330238

331-
if (auxv & HWCAP_CRC32) {
239+
if (_features & CPU_CRC32) {
332240
if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
333241
FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
334242
}
@@ -341,7 +249,7 @@ void VM_Version::get_processor_features() {
341249
FLAG_SET_DEFAULT(UseFMA, true);
342250
}
343251

344-
if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) {
252+
if (_features & (CPU_SHA1 | CPU_SHA2)) {
345253
if (FLAG_IS_DEFAULT(UseSHA)) {
346254
FLAG_SET_DEFAULT(UseSHA, true);
347255
}
@@ -350,7 +258,7 @@ void VM_Version::get_processor_features() {
350258
FLAG_SET_DEFAULT(UseSHA, false);
351259
}
352260

353-
if (UseSHA && (auxv & HWCAP_SHA1)) {
261+
if (UseSHA && (_features & CPU_SHA1)) {
354262
if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
355263
FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
356264
}
@@ -359,7 +267,7 @@ void VM_Version::get_processor_features() {
359267
FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
360268
}
361269

362-
if (UseSHA && (auxv & HWCAP_SHA2)) {
270+
if (UseSHA && (_features & CPU_SHA2)) {
363271
if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
364272
FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
365273
}
@@ -377,7 +285,7 @@ void VM_Version::get_processor_features() {
377285
FLAG_SET_DEFAULT(UseSHA, false);
378286
}
379287

380-
if (auxv & HWCAP_PMULL) {
288+
if (_features & CPU_PMULL) {
381289
if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
382290
FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
383291
}
@@ -439,22 +347,6 @@ void VM_Version::get_processor_features() {
439347
OptoScheduling = true;
440348
}
441349
#endif
442-
}
443-
444-
void VM_Version::initialize() {
445-
ResourceMark rm;
446-
447-
stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
448-
if (stub_blob == NULL) {
449-
vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
450-
}
451-
452-
CodeBuffer c(stub_blob);
453-
VM_Version_StubGenerator g(&c);
454-
getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
455-
g.generate_getPsrInfo());
456-
457-
get_processor_features();
458350

459351
UNSUPPORTED_OPTION(CriticalJNINatives);
460352
}

src/hotspot/cpu/aarch64/vm_version_aarch64.hpp

Lines changed: 13 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -41,12 +41,12 @@ class VM_Version : public Abstract_VM_Version {
4141
static int _revision;
4242
static int _stepping;
4343

44-
struct PsrInfo {
45-
uint32_t dczid_el0;
46-
uint32_t ctr_el0;
47-
};
48-
static PsrInfo _psr_info;
49-
static void get_processor_features();
44+
static int _zva_length;
45+
static int _dcache_line_size;
46+
static int _icache_line_size;
47+
48+
// Read additional info using OS-specific interfaces
49+
static void get_os_cpu_info();
5050

5151
public:
5252
// Initialization
@@ -91,6 +91,7 @@ class VM_Version : public Abstract_VM_Version {
9191
CPU_SHA2 = (1<<6),
9292
CPU_CRC32 = (1<<7),
9393
CPU_LSE = (1<<8),
94+
// flags above must follow Linux HWCAP
9495
CPU_STXR_PREFETCH= (1 << 29),
9596
CPU_A53MAC = (1 << 30),
9697
CPU_DMB_ATOMICS = (1 << 31),
@@ -101,24 +102,15 @@ class VM_Version : public Abstract_VM_Version {
101102
static int cpu_model2() { return _model2; }
102103
static int cpu_variant() { return _variant; }
103104
static int cpu_revision() { return _revision; }
104-
static ByteSize dczid_el0_offset() { return byte_offset_of(PsrInfo, dczid_el0); }
105-
static ByteSize ctr_el0_offset() { return byte_offset_of(PsrInfo, ctr_el0); }
106-
static bool is_zva_enabled() {
107-
// Check the DZP bit (bit 4) of dczid_el0 is zero
108-
// and block size (bit 0~3) is not zero.
109-
return ((_psr_info.dczid_el0 & 0x10) == 0 &&
110-
(_psr_info.dczid_el0 & 0xf) != 0);
111-
}
105+
106+
static bool is_zva_enabled() { return 0 <= _zva_length; }
112107
static int zva_length() {
113108
assert(is_zva_enabled(), "ZVA not available");
114-
return 4 << (_psr_info.dczid_el0 & 0xf);
115-
}
116-
static int icache_line_size() {
117-
return (1 << (_psr_info.ctr_el0 & 0x0f)) * 4;
118-
}
119-
static int dcache_line_size() {
120-
return (1 << ((_psr_info.ctr_el0 >> 16) & 0x0f)) * 4;
109+
return _zva_length;
121110
}
111+
112+
static int icache_line_size() { return _icache_line_size; }
113+
static int dcache_line_size() { return _dcache_line_size; }
122114
};
123115

124116
#endif // CPU_AARCH64_VM_VM_VERSION_AARCH64_HPP

0 commit comments

Comments
 (0)