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lewurmVladimir Kempik
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8274795: AArch64: avoid spilling and restoring r18 in macro assembler
Reviewed-by: aph Backport-of: ede3f4e94c752a8457b7c24e001bd122845d2f6a
1 parent 914d48c commit b5cae57

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2 files changed

+21
-6
lines changed

2 files changed

+21
-6
lines changed

src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp

Lines changed: 18 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2040,11 +2040,17 @@ void MacroAssembler::increment(Address dst, int value)
20402040

20412041

20422042
void MacroAssembler::pusha() {
2043-
push(0x7fffffff, sp);
2043+
push(RegSet::range(r0, r30), sp);
20442044
}
20452045

20462046
void MacroAssembler::popa() {
2047-
pop(0x7fffffff, sp);
2047+
pop(RegSet::range(r0, r17), sp);
2048+
#ifdef R18_RESERVED
2049+
ldp(zr, r19, Address(post(sp, 2 * wordSize)));
2050+
pop(RegSet::range(r20, r30), sp);
2051+
#else
2052+
pop(RegSet::range(r18_tls, r30), sp);
2053+
#endif
20482054
}
20492055

20502056
// Push lots of registers in the bit set supplied. Don't push sp.
@@ -2579,7 +2585,7 @@ void MacroAssembler::pop_call_clobbered_registers() {
25792585

25802586
void MacroAssembler::push_CPU_state(bool save_vectors) {
25812587
int step = (save_vectors ? 8 : 4) * wordSize;
2582-
push(0x3fffffff, sp); // integer registers except lr & sp
2588+
push(RegSet::range(r0, r29), sp); // integer registers except lr & sp
25832589
mov(rscratch1, -step);
25842590
sub(sp, sp, step);
25852591
for (int i = 28; i >= 4; i -= 4) {
@@ -2594,7 +2600,15 @@ void MacroAssembler::pop_CPU_state(bool restore_vectors) {
25942600
for (int i = 0; i <= 28; i += 4)
25952601
ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
25962602
as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step)));
2597-
pop(0x3fffffff, sp); // integer registers except lr & sp
2603+
2604+
// integer registers except lr & sp
2605+
pop(RegSet::range(r0, r17), sp);
2606+
#ifdef R18_RESERVED
2607+
ldp(zr, r19, Address(post(sp, 2 * wordSize)));
2608+
pop(RegSet::range(r20, r29), sp);
2609+
#else
2610+
pop(RegSet::range(r18_tls, r29), sp);
2611+
#endif
25982612
}
25992613

26002614
/**

src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1458,11 +1458,12 @@ address TemplateInterpreterGenerator::generate_native_entry(bool synchronized) {
14581458
__ cmp(rscratch1, JavaThread::stack_guard_yellow_reserved_disabled);
14591459
__ br(Assembler::NE, no_reguard);
14601460

1461-
__ pusha(); // XXX only save smashed registers
1461+
__ push_call_clobbered_registers();
14621462
__ mov(c_rarg0, rthread);
14631463
__ mov(rscratch2, CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
14641464
__ blr(rscratch2);
1465-
__ popa(); // XXX only restore smashed registers
1465+
__ pop_call_clobbered_registers();
1466+
14661467
__ bind(no_reguard);
14671468
}
14681469

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