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8253284: Zero OrderAccess barrier mappings are incorrect #224

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8253284: Zero OrderAccess barrier mappings are incorrect #224

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9963407
8253284: Zero OrderAccess barrier mappings are incorrect
shipilev Sep 17, 2020
012a59a
Mirror the same in bsd_zero.hpp
shipilev Sep 17, 2020
add14aa
Fix copy-paste omission in bsd_zero
shipilev Sep 17, 2020
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24 changes: 14 additions & 10 deletions src/hotspot/os_cpu/bsd_zero/orderAccess_bsd_zero.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@

// Included in orderAccess.hpp header file.

#ifdef ARM
#if defined(ARM) // ----------------------------------------------------

/*
* ARM Kernel helper for memory barrier.
Expand All @@ -39,28 +39,32 @@
typedef void (__kernel_dmb_t) (void);
#define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0)

#define FULL_MEM_BARRIER __kernel_dmb()
#define LIGHT_MEM_BARRIER __kernel_dmb()
#define FULL_MEM_BARRIER __kernel_dmb()

#else // ARM

#define FULL_MEM_BARRIER __sync_synchronize()

#ifdef PPC
#elif defined(PPC) // ----------------------------------------------------

#ifdef __NO_LWSYNC__
#define LIGHT_MEM_BARRIER __asm __volatile ("sync":::"memory")
#else
#define LIGHT_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
#endif

#else // PPC
#define FULL_MEM_BARRIER __sync_synchronize()

#elif defined(X86) // ----------------------------------------------------

#define LIGHT_MEM_BARRIER __asm __volatile ("":::"memory")
#define FULL_MEM_BARRIER __sync_synchronize()

#else // ----------------------------------------------------

// Default to strongest barriers for correctness.

#endif // PPC
#define LIGHT_MEM_BARRIER __sync_synchronize()
#define FULL_MEM_BARRIER __sync_synchronize()

#endif // ARM
#endif // ----------------------------------------------------

// Note: What is meant by LIGHT_MEM_BARRIER is a barrier which is sufficient
// to provide TSO semantics, i.e. StoreStore | LoadLoad | LoadStore.
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28 changes: 12 additions & 16 deletions src/hotspot/os_cpu/linux_zero/orderAccess_linux_zero.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@

// Included in orderAccess.hpp header file.

#ifdef ARM
#if defined(ARM) // ----------------------------------------------------

/*
* ARM Kernel helper for memory barrier.
Expand All @@ -39,36 +39,32 @@
typedef void (__kernel_dmb_t) (void);
#define __kernel_dmb (*(__kernel_dmb_t *) 0xffff0fa0)

#define FULL_MEM_BARRIER __kernel_dmb()
#define LIGHT_MEM_BARRIER __kernel_dmb()
#define FULL_MEM_BARRIER __kernel_dmb()

#else // ARM

#define FULL_MEM_BARRIER __sync_synchronize()

#ifdef PPC
#elif defined(PPC) // ----------------------------------------------------

#ifdef __NO_LWSYNC__
#define LIGHT_MEM_BARRIER __asm __volatile ("sync":::"memory")
#else
#define LIGHT_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
#endif

#else // PPC
#define FULL_MEM_BARRIER __sync_synchronize()

#ifdef ALPHA

#define LIGHT_MEM_BARRIER __sync_synchronize()

#else // ALPHA
#elif defined(X86) // ----------------------------------------------------

#define LIGHT_MEM_BARRIER __asm __volatile ("":::"memory")
#define FULL_MEM_BARRIER __sync_synchronize()

#else // ----------------------------------------------------

#endif // ALPHA
// Default to strongest barriers for correctness.

#endif // PPC
#define LIGHT_MEM_BARRIER __sync_synchronize()
#define FULL_MEM_BARRIER __sync_synchronize()

#endif // ARM
#endif // ----------------------------------------------------

// Note: What is meant by LIGHT_MEM_BARRIER is a barrier which is sufficient
// to provide TSO semantics, i.e. StoreStore | LoadLoad | LoadStore.
Expand Down