From 1faf13bc2ca37d091f69c63e84296d41f00f8920 Mon Sep 17 00:00:00 2001 From: yadongw Date: Sat, 17 Dec 2022 12:57:33 +0800 Subject: [PATCH 1/3] 8299525: RISC-V: Add backend support for half float conversion intrinsics --- src/hotspot/cpu/riscv/assembler_riscv.hpp | 4 +++ src/hotspot/cpu/riscv/globals_riscv.hpp | 1 + src/hotspot/cpu/riscv/riscv.ad | 42 +++++++++++++++++++++++ 3 files changed, 47 insertions(+) diff --git a/src/hotspot/cpu/riscv/assembler_riscv.hpp b/src/hotspot/cpu/riscv/assembler_riscv.hpp index 62a81bd155196..b39366646c81d 100644 --- a/src/hotspot/cpu/riscv/assembler_riscv.hpp +++ b/src/hotspot/cpu/riscv/assembler_riscv.hpp @@ -798,6 +798,8 @@ enum operand_size { int8, int16, int32, uint32, int64 }; INSN(fsqrt_d, 0b1010011, 0b00000, 0b0101101); INSN(fcvt_s_d, 0b1010011, 0b00001, 0b0100000); INSN(fcvt_d_s, 0b1010011, 0b00000, 0b0100001); + INSN(fcvt_s_h, 0b1010011, 0b00010, 0b0100000); + INSN(fcvt_h_s, 0b1010011, 0b00000, 0b0100010); #undef INSN // Immediate Instruction @@ -1054,6 +1056,7 @@ enum operand_size { int8, int16, int32, uint32, int64 }; INSN(fmv_w_x, 0b1010011, 0b000, 0b00000, 0b1111000); INSN(fmv_d_x, 0b1010011, 0b000, 0b00000, 0b1111001); + INSN(fmv_h_x, 0b1010011, 0b000, 0b00000, 0b1111010); #undef INSN @@ -1074,6 +1077,7 @@ enum operand_size { int8, int16, int32, uint32, int64 }; INSN(fclass_d, 0b1010011, 0b001, 0b00000, 0b1110001); INSN(fmv_x_w, 0b1010011, 0b000, 0b00000, 0b1110000); INSN(fmv_x_d, 0b1010011, 0b000, 0b00000, 0b1110001); + INSN(fmv_x_h, 0b1010011, 0b000, 0b00000, 0b1110010); #undef INSN diff --git a/src/hotspot/cpu/riscv/globals_riscv.hpp b/src/hotspot/cpu/riscv/globals_riscv.hpp index cb7bd99dfb280..a64b135006cd6 100644 --- a/src/hotspot/cpu/riscv/globals_riscv.hpp +++ b/src/hotspot/cpu/riscv/globals_riscv.hpp @@ -103,6 +103,7 @@ define_pd_global(intx, InlineSmallCode, 1000); product(bool, UseZba, false, EXPERIMENTAL, "Use Zba instructions") \ product(bool, UseZbb, false, EXPERIMENTAL, "Use Zbb instructions") \ product(bool, UseZbs, false, EXPERIMENTAL, "Use Zbs instructions") \ + product(bool, UseZfh, false, EXPERIMENTAL, "Use Zfh instructions") \ product(bool, UseZic64b, false, EXPERIMENTAL, "Use Zic64b instructions") \ product(bool, UseZicbom, false, EXPERIMENTAL, "Use Zicbom instructions") \ product(bool, UseZicbop, false, EXPERIMENTAL, "Use Zicbop instructions") \ diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad index cf9d6bc556f2d..ed01ae75b60d7 100644 --- a/src/hotspot/cpu/riscv/riscv.ad +++ b/src/hotspot/cpu/riscv/riscv.ad @@ -1842,6 +1842,10 @@ const bool Matcher::match_rule_supported(int opcode) { case Op_CountTrailingZerosI: case Op_CountTrailingZerosL: return UseZbb; + + case Op_ConvF2HF: + case Op_ConvHF2F: + return UseZfh; } return true; // Per default match rules are supported. @@ -8135,6 +8139,44 @@ instruct convL2F_reg_reg(fRegF dst, iRegL src) %{ ins_pipe(fp_l2f); %} +// float <-> half float + +instruct convHF2F_reg_reg(fRegF dst, iRegINoSp src, fRegF tmp) %{ + predicate(UseZfh); + match(Set dst (ConvHF2F src)); + effect(TEMP tmp); + + ins_cost(XFER_COST); + format %{ "fmv.h.x $tmp, $src\t#@convHF2F_reg_reg\n\t" + "fcvt.s.h $dst, $tmp\t#@convHF2F_reg_reg" + %} + + ins_encode %{ + __ fmv_h_x($tmp$$FloatRegister, $src$$Register); + __ fcvt_s_h($dst$$FloatRegister, $tmp$$FloatRegister); + %} + + ins_pipe(fp_f2d); +%} + +instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF tmp) %{ + predicate(UseZfh); + match(Set dst (ConvF2HF src)); + effect(TEMP tmp); + + ins_cost(XFER_COST); + format %{ "fcvt.h.s $tmp, $src\t#@convF2HF_reg_reg\n\t" + "fmv.x.h $dst, $tmp\t#@convF2HF_reg_reg" + %} + + ins_encode %{ + __ fcvt_h_s($tmp$$FloatRegister, $src$$FloatRegister); + __ fmv_x_h($dst$$Register, $tmp$$FloatRegister); + %} + + ins_pipe(fp_f2d); +%} + // double <-> int instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{ From 8a08bfd9248ef5d5d8e117794cea18ec763fdbb3 Mon Sep 17 00:00:00 2001 From: yadongw Date: Thu, 5 Jan 2023 22:37:03 +0800 Subject: [PATCH 2/3] change Zfh to Zfhmin --- src/hotspot/cpu/riscv/globals_riscv.hpp | 2 +- src/hotspot/cpu/riscv/riscv.ad | 6 +++--- src/hotspot/cpu/riscv/vm_version_riscv.cpp | 3 +++ 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/hotspot/cpu/riscv/globals_riscv.hpp b/src/hotspot/cpu/riscv/globals_riscv.hpp index a64b135006cd6..580ded4b093b5 100644 --- a/src/hotspot/cpu/riscv/globals_riscv.hpp +++ b/src/hotspot/cpu/riscv/globals_riscv.hpp @@ -103,7 +103,7 @@ define_pd_global(intx, InlineSmallCode, 1000); product(bool, UseZba, false, EXPERIMENTAL, "Use Zba instructions") \ product(bool, UseZbb, false, EXPERIMENTAL, "Use Zbb instructions") \ product(bool, UseZbs, false, EXPERIMENTAL, "Use Zbs instructions") \ - product(bool, UseZfh, false, EXPERIMENTAL, "Use Zfh instructions") \ + product(bool, UseZfhmin, false, EXPERIMENTAL, "Use Zfhmin instructions") \ product(bool, UseZic64b, false, EXPERIMENTAL, "Use Zic64b instructions") \ product(bool, UseZicbom, false, EXPERIMENTAL, "Use Zicbom instructions") \ product(bool, UseZicbop, false, EXPERIMENTAL, "Use Zicbop instructions") \ diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad index ed01ae75b60d7..008bd7193d3ab 100644 --- a/src/hotspot/cpu/riscv/riscv.ad +++ b/src/hotspot/cpu/riscv/riscv.ad @@ -1845,7 +1845,7 @@ const bool Matcher::match_rule_supported(int opcode) { case Op_ConvF2HF: case Op_ConvHF2F: - return UseZfh; + return UseZfhmin; } return true; // Per default match rules are supported. @@ -8142,7 +8142,7 @@ instruct convL2F_reg_reg(fRegF dst, iRegL src) %{ // float <-> half float instruct convHF2F_reg_reg(fRegF dst, iRegINoSp src, fRegF tmp) %{ - predicate(UseZfh); + predicate(UseZfhmin); match(Set dst (ConvHF2F src)); effect(TEMP tmp); @@ -8160,7 +8160,7 @@ instruct convHF2F_reg_reg(fRegF dst, iRegINoSp src, fRegF tmp) %{ %} instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF tmp) %{ - predicate(UseZfh); + predicate(UseZfhmin); match(Set dst (ConvF2HF src)); effect(TEMP tmp); diff --git a/src/hotspot/cpu/riscv/vm_version_riscv.cpp b/src/hotspot/cpu/riscv/vm_version_riscv.cpp index 6afef7ae546f2..4db91c2810d5f 100644 --- a/src/hotspot/cpu/riscv/vm_version_riscv.cpp +++ b/src/hotspot/cpu/riscv/vm_version_riscv.cpp @@ -71,6 +71,9 @@ void VM_Version::initialize() { if (FLAG_IS_DEFAULT(UseZicboz)) { FLAG_SET_DEFAULT(UseZicboz, true); } + if (FLAG_IS_DEFAULT(UseZfhmin)) { + FLAG_SET_DEFAULT(UseZfhmin, true); + } } if (UseZic64b) { From 271f6d691c66e3d06f0c68be9bcd48378c06d4d9 Mon Sep 17 00:00:00 2001 From: yadongw Date: Fri, 6 Jan 2023 17:31:51 +0800 Subject: [PATCH 3/3] fix --- src/hotspot/cpu/riscv/riscv.ad | 12 ++++++------ src/hotspot/cpu/riscv/vm_version_riscv.cpp | 3 +++ 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad index 008bd7193d3ab..eb515b6d88ed1 100644 --- a/src/hotspot/cpu/riscv/riscv.ad +++ b/src/hotspot/cpu/riscv/riscv.ad @@ -8152,11 +8152,11 @@ instruct convHF2F_reg_reg(fRegF dst, iRegINoSp src, fRegF tmp) %{ %} ins_encode %{ - __ fmv_h_x($tmp$$FloatRegister, $src$$Register); - __ fcvt_s_h($dst$$FloatRegister, $tmp$$FloatRegister); + __ fmv_h_x($tmp$$FloatRegister, $src$$Register); + __ fcvt_s_h($dst$$FloatRegister, $tmp$$FloatRegister); %} - ins_pipe(fp_f2d); + ins_pipe(fp_i2f); %} instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF tmp) %{ @@ -8170,11 +8170,11 @@ instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF tmp) %{ %} ins_encode %{ - __ fcvt_h_s($tmp$$FloatRegister, $src$$FloatRegister); - __ fmv_x_h($dst$$Register, $tmp$$FloatRegister); + __ fcvt_h_s($tmp$$FloatRegister, $src$$FloatRegister); + __ fmv_x_h($dst$$Register, $tmp$$FloatRegister); %} - ins_pipe(fp_f2d); + ins_pipe(fp_f2i); %} // double <-> int diff --git a/src/hotspot/cpu/riscv/vm_version_riscv.cpp b/src/hotspot/cpu/riscv/vm_version_riscv.cpp index 4db91c2810d5f..9ba73a0080855 100644 --- a/src/hotspot/cpu/riscv/vm_version_riscv.cpp +++ b/src/hotspot/cpu/riscv/vm_version_riscv.cpp @@ -59,6 +59,9 @@ void VM_Version::initialize() { if (FLAG_IS_DEFAULT(UseZbb)) { FLAG_SET_DEFAULT(UseZbb, true); } + if (FLAG_IS_DEFAULT(UseZbs)) { + FLAG_SET_DEFAULT(UseZbs, true); + } if (FLAG_IS_DEFAULT(UseZic64b)) { FLAG_SET_DEFAULT(UseZic64b, true); }